DBT-RISE-TGC/gen_input/TGC5C.core_desc

import "ISA/RVI.core_desc"
import "ISA/RVM.core_desc"
import "ISA/RVC.core_desc"

Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
    architectural_state {
        XLEN=32;
        // definitions for the architecture wrapper
        //                    XL    ZYXWVUTSRQPONMLKJIHGFEDCBA
        unsigned int MISA_VAL = 0b01000000000000000001000100000100;
        unsigned int MARCHID_VAL = 0x80000003;
    }
}