 Eyck Jentzsch
|
a899d30556
|
Implemented basic HiFive1-like platform with PLL,tracing etc.
|
2018-07-13 20:04:07 +02:00 |
|
Eyck Jentzsch
|
fede5b2af1
|
Changed SystemC model to model a platform in a system. Added dedicated
UART Terminal connected via tlm_signals
|
2018-07-12 15:27:36 +02:00 |
|
Eyck Jentzsch
|
dfcc3ace66
|
Adapted generated code to support translation block linking
|
2018-05-15 18:50:11 +02:00 |
|
Eyck Jentzsch
|
19b660962b
|
Adapted descriptions to improved Core DSL and regenerated code
|
2018-05-01 18:33:55 +02:00 |
|
Eyck Jentzsch
|
1102449d38
|
Made plugin call configurable
|
2018-04-24 23:12:07 +02:00 |
|
Eyck Jentzsch
|
142654b0a2
|
Streamline arch descriptions according to latest CoreDSL changes
|
2018-04-24 17:18:24 +02:00 |
|
Eyck Jentzsch
|
ce98e2ad31
|
Added RV32D extension
|
2018-04-24 15:33:21 +02:00 |
|
Eyck Jentzsch
|
48ad30dcae
|
Added RV32F extension, fixed RV32M bugs
|
2018-04-24 11:05:11 +02:00 |
|
Eyck Jentzsch
|
38471b8193
|
Added cycle estimator and remove deprecated functions
|
2018-03-30 17:59:40 +02:00 |
|
Eyck Jentzsch
|
3ea9651665
|
Added use of CCI and support of LLVM 5.0
changed load_file to adhere to API change in DBT-RISE
|
2018-03-27 19:49:11 +02:00 |
|
Eyck Jentzsch
|
36be8b87f1
|
Added simple example plugin creating instruction histogram
|
2018-02-11 21:30:52 +00:00 |
|
Eyck Jentzsch
|
c5a7adcef5
|
Refactored code generation to use custom templates
|
2018-02-09 18:34:26 +00:00 |
|
Eyck Jentzsch
|
7c2539bff0
|
C++11 refactoring
|
2018-02-06 18:26:55 +00:00 |
|
Eyck Jentzsch
|
9d40aa3aab
|
Added instruction enumeration and some cleanup
|
2017-12-31 11:27:51 +01:00 |
|
Eyck Jentzsch
|
873e4257f2
|
Restructured DBT function to encapsulate the compilation process
This should enable the implementation of multi-threading of the
compilation process
|
2017-12-28 17:09:24 +01:00 |
|
Eyck Jentzsch
|
c9fd1303ce
|
Fixed license header
|
2017-11-27 00:14:41 +01:00 |
|
Eyck Jentzsch
|
f1667c195a
|
Initial RV64I verification
|
2017-11-23 14:48:18 +01:00 |
|
Eyck Jentzsch
|
5d508740fd
|
Fixed 64bit integer base instruction set
|
2017-11-18 00:42:33 +01:00 |
|
Eyck Jentzsch
|
eced81b5ea
|
added sc_comm_singleton to coordinate interaction with clients (e.g. web
browser)
|
2017-11-10 22:40:24 +01:00 |
|
Eyck Jentzsch
|
b0dcb3b60e
|
Fixed handling of compressed ISA
|
2017-10-25 22:05:31 +02:00 |
|
Eyck Jentzsch
|
9970303fa4
|
Changed handling of disassembler output so that tarcing becomes possible
|
2017-10-22 19:29:37 +02:00 |
|
Eyck Jentzsch
|
b9c910b283
|
clean up class vs. struct
|
2017-10-12 22:41:37 +02:00 |
|
Eyck Jentzsch
|
f2b9ca84b0
|
Adaptation to changes in libraries
|
2017-10-12 14:49:33 +02:00 |
|
Eyck Jentzsch
|
768df67646
|
Refactored hart vm implementation to use more structured description
|
2017-10-04 23:10:29 +02:00 |
|
Eyck Jentzsch
|
ccc3f5d47d
|
Adapted namespace changes in sc-components
|
2017-10-04 14:30:25 +02:00 |
|
Eyck Jentzsch
|
4867cca187
|
Added SystemC version of HiFive FE310
|
2017-10-04 10:31:11 +02:00 |
|
Eyck Jentzsch
|
d8184abbcc
|
Refactored file dependencies to decouple components
|
2017-09-26 17:48:51 +02:00 |
|
Eyck Jentzsch
|
4ce4b2562b
|
Fixed clang-tidy warnings
|
2017-09-22 22:19:25 +02:00 |
|
Eyck Jentzsch
|
b38319f9c2
|
Applied clang-format
|
2017-09-22 11:23:23 +02:00 |
|
Eyck Jentzsch
|
39150b68c0
|
Adapted to log system
|
2017-09-22 10:11:29 +02:00 |
|
Eyck Jentzsch
|
9a617dab57
|
Restructured project
|
2017-09-21 20:29:23 +02:00 |
|
Eyck Jentzsch
|
aa8c2138c6
|
Added initial SystemC structure and removed easylogging
|
2017-09-21 13:13:01 +02:00 |
|
Eyck Jentzsch
|
1cb492b594
|
Renamed hart name and core wrapper name
|
2017-08-29 16:56:57 +02:00 |
|
Eyck Jentzsch
|
9619de45d0
|
Cleanup of generated code
|
2017-08-27 22:14:59 +02:00 |
|
Eyck Jentzsch
|
4ee7118b70
|
Initial commit
|
2017-08-27 13:04:48 +02:00 |