clean up class vs. struct

.project

@@ -7,7 +7,6 @@
 	<buildSpec>
 		<buildCommand>
 			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
-			<triggers>clean,full,incremental,</triggers>
 			<arguments>
 			</arguments>
 		</buildCommand>

dbt-core

@@ -1 +1 @@
-Subproject commit a0baf6ef660c50a93d079f5208e9d1c354eb304f
+Subproject commit 35d9bbfe6569f2412c2ff98cd3a554c4d750b3de

riscv.sc/incl/sysc/SiFive/clint.h

@@ -21,7 +21,7 @@
 
 namespace iss {
 namespace arch {
-template <typename BASE> struct riscv_hart_msu_vp;
+template <typename BASE> class riscv_hart_msu_vp;
 }
 }
 

riscv.sc/incl/sysc/SiFive/core_complex.h

@@ -37,21 +37,22 @@
 #ifndef _SYSC_SIFIVE_FE310_H_
 #define _SYSC_SIFIVE_FE310_H_
 
+#include "scc/utilities.h"
 #include <tlm>
 #include <tlm_utils/tlm_quantumkeeper.h>
 #include <util/range_lut.h>
 #include "scc/ext_attribute.h"
+#include "scv4tlm/tlm_rec_initiator_socket.h"
 #include "scc/initiator_mixin.h"
 #include "scc/traceable.h"
-#include "scc/utilities.h"
 
 namespace iss {
 class vm_if;
 namespace arch {
-template <typename BASE> struct riscv_hart_msu_vp;
+template <typename BASE> class riscv_hart_msu_vp;
 }
 namespace debugger {
-struct target_adapter_if;
+class target_adapter_if;
 }
 }
 
@@ -74,7 +75,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable {
 public:
     SC_HAS_PROCESS(core_complex);
 
-    scc::initiator_mixin<tlm::tlm_initiator_socket<32>> initiator;
+    scc::initiator_mixin<scv4tlm::tlm_rec_initiator_socket<32>> initiator;
 
     sc_core::sc_in<sc_core::sc_time> clk_i;
 

riscv/incl/iss/arch/riscv_hart_msu_vp.h

@@ -224,23 +224,28 @@ struct vm_info {
     uint64_t ptbase;
 };
 
-struct trap_load_access_fault : public trap_access {
+class trap_load_access_fault : public trap_access {
+public:
     trap_load_access_fault(uint64_t badaddr)
     : trap_access(5 << 16, badaddr) {}
 };
-struct illegal_instruction_fault : public trap_access {
+class illegal_instruction_fault : public trap_access {
+public:
     illegal_instruction_fault(uint64_t badaddr)
     : trap_access(2 << 16, badaddr) {}
 };
-struct trap_instruction_page_fault : public trap_access {
+class trap_instruction_page_fault : public trap_access {
+public:
     trap_instruction_page_fault(uint64_t badaddr)
     : trap_access(12 << 16, badaddr) {}
 };
-struct trap_load_page_fault : public trap_access {
+class trap_load_page_fault : public trap_access {
+public:
     trap_load_page_fault(uint64_t badaddr)
     : trap_access(13 << 16, badaddr) {}
 };
-struct trap_store_page_fault : public trap_access {
+class trap_store_page_fault : public trap_access {
+public:
     trap_store_page_fault(uint64_t badaddr)
     : trap_access(15 << 16, badaddr) {}
 };
@@ -262,7 +267,8 @@ public:
     template<class T, class Enable = void> struct hart_state { };
     // specialization 32bit
     template <typename T>
-    struct hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
+    class hart_state<T, typename std::enable_if<std::is_same<T, uint32_t>::value>::type> {
+    public:
         BEGIN_BF_DECL(mstatus_t, T);
         // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
         BF_FIELD(SD, 31, 1);
@@ -328,7 +334,8 @@ public:
     };
     // specialization 64bit
     template <typename T>
-    struct hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
+    class hart_state<T, typename std::enable_if<std::is_same<T, uint64_t>::value>::type> {
+    public:
         BEGIN_BF_DECL(mstatus_t, T);
         // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11)))
         BF_FIELD(SD, 63, 1);

riscv/incl/iss/arch/rv32imac.h

@@ -43,10 +43,10 @@
 namespace iss {
 namespace arch {
 
-struct rv32imac;
-
-template <> struct traits<rv32imac> {
+class rv32imac;
 
+template <> class traits<rv32imac> {
+public:
     enum constants {
         XLEN = 32,
         XLEN2 = 64,
@@ -132,8 +132,8 @@ template <> struct traits<rv32imac> {
     enum mem_type_e { MEM, CSR, FENCE, RES };
 };
 
-struct rv32imac : public arch_if {
-
+class rv32imac : public arch_if {
+public:
     using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
     using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
     using reg_t = typename traits<rv32imac>::reg_t;

riscv/incl/iss/arch/rv64ia.h

@@ -43,10 +43,10 @@
 namespace iss {
 namespace arch {
 
-struct rv64ia;
-
-template <> struct traits<rv64ia> {
+class rv64ia;
 
+template <> class traits<rv64ia> {
+public:
     enum constants {
         XLEN = 64,
         XLEN2 = 128,
@@ -131,8 +131,8 @@ template <> struct traits<rv64ia> {
     enum mem_type_e { MEM, CSR, FENCE, RES };
 };
 
-struct rv64ia : public arch_if {
-
+class rv64ia : public arch_if {
+public:
     using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
     using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
     using reg_t = typename traits<rv64ia>::reg_t;

riscv/incl/iss/debugger/riscv_target_adapter.h

@@ -21,8 +21,8 @@ namespace debugger {
 using namespace iss::arch;
 using namespace iss::debugger;
 
-template <typename ARCH> struct riscv_target_adapter : public target_adapter_base {
-
+template <typename ARCH> class riscv_target_adapter : public target_adapter_base {
+public:
     riscv_target_adapter(server_if *srv, iss::arch_if *core)
     : target_adapter_base(srv)
     , core(core) {}

riscv/src/internal/vm_riscv.in.cpp

@@ -52,7 +52,8 @@ using namespace iss::arch;
 using namespace llvm;
 using namespace iss::debugger;
 
-template <typename ARCH> struct vm_impl : public vm::vm_base<ARCH> {
+template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
+public:
     using super = typename vm::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;

riscv/src/internal/vm_rv32imac.cpp

@@ -52,7 +52,8 @@ using namespace iss::arch;
 using namespace llvm;
 using namespace iss::debugger;
 
-template <typename ARCH> struct vm_impl : public vm::vm_base<ARCH> {
+template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
+public:
     using super = typename vm::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;

riscv/src/internal/vm_rv64ia.cpp

@@ -52,7 +52,8 @@ using namespace iss::arch;
 using namespace llvm;
 using namespace iss::debugger;
 
-template <typename ARCH> struct vm_impl : public vm::vm_base<ARCH> {
+template <typename ARCH> class vm_impl : public vm::vm_base<ARCH> {
+public:
     using super = typename vm::vm_base<ARCH>;
     using virt_addr_t = typename super::virt_addr_t;
     using phys_addr_t = typename super::phys_addr_t;

sc-components

@@ -1 +1 @@
-Subproject commit 27001d6707071fe4727c698c0f777d587dd99a60
+Subproject commit db46dcd39581618564bd3e589c95c36c277679ed