From b9c910b283eb43b8804ef59eeb0a5b98b11354ca Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Thu, 12 Oct 2017 22:41:37 +0200 Subject: [PATCH] clean up class vs. struct --- .project | 1 - dbt-core | 2 +- riscv.sc/incl/sysc/SiFive/clint.h | 2 +- riscv.sc/incl/sysc/SiFive/core_complex.h | 9 ++++---- riscv/incl/iss/arch/riscv_hart_msu_vp.h | 21 ++++++++++++------- riscv/incl/iss/arch/rv32imac.h | 10 ++++----- riscv/incl/iss/arch/rv64ia.h | 10 ++++----- .../incl/iss/debugger/riscv_target_adapter.h | 4 ++-- riscv/src/internal/vm_riscv.in.cpp | 3 ++- riscv/src/internal/vm_rv32imac.cpp | 3 ++- riscv/src/internal/vm_rv64ia.cpp | 3 ++- sc-components | 2 +- 12 files changed, 40 insertions(+), 30 deletions(-) diff --git a/.project b/.project index 3e68573..43247d2 100644 --- a/.project +++ b/.project @@ -7,7 +7,6 @@ org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, diff --git a/dbt-core b/dbt-core index a0baf6e..35d9bbf 160000 --- a/dbt-core +++ b/dbt-core @@ -1 +1 @@ -Subproject commit a0baf6ef660c50a93d079f5208e9d1c354eb304f +Subproject commit 35d9bbfe6569f2412c2ff98cd3a554c4d750b3de diff --git a/riscv.sc/incl/sysc/SiFive/clint.h b/riscv.sc/incl/sysc/SiFive/clint.h index e1130cb..1e3fbf1 100644 --- a/riscv.sc/incl/sysc/SiFive/clint.h +++ b/riscv.sc/incl/sysc/SiFive/clint.h @@ -21,7 +21,7 @@ namespace iss { namespace arch { -template struct riscv_hart_msu_vp; +template class riscv_hart_msu_vp; } } diff --git a/riscv.sc/incl/sysc/SiFive/core_complex.h b/riscv.sc/incl/sysc/SiFive/core_complex.h index 816b0cf..6a15cca 100644 --- a/riscv.sc/incl/sysc/SiFive/core_complex.h +++ b/riscv.sc/incl/sysc/SiFive/core_complex.h @@ -37,21 +37,22 @@ #ifndef _SYSC_SIFIVE_FE310_H_ #define _SYSC_SIFIVE_FE310_H_ +#include "scc/utilities.h" #include #include #include #include "scc/ext_attribute.h" +#include "scv4tlm/tlm_rec_initiator_socket.h" #include "scc/initiator_mixin.h" #include "scc/traceable.h" -#include "scc/utilities.h" namespace iss { class vm_if; namespace arch { -template struct riscv_hart_msu_vp; +template class riscv_hart_msu_vp; } namespace debugger { -struct target_adapter_if; +class target_adapter_if; } } @@ -74,7 +75,7 @@ class core_complex : public sc_core::sc_module, public scc::traceable { public: SC_HAS_PROCESS(core_complex); - scc::initiator_mixin> initiator; + scc::initiator_mixin> initiator; sc_core::sc_in clk_i; diff --git a/riscv/incl/iss/arch/riscv_hart_msu_vp.h b/riscv/incl/iss/arch/riscv_hart_msu_vp.h index 3742986..e567895 100644 --- a/riscv/incl/iss/arch/riscv_hart_msu_vp.h +++ b/riscv/incl/iss/arch/riscv_hart_msu_vp.h @@ -224,23 +224,28 @@ struct vm_info { uint64_t ptbase; }; -struct trap_load_access_fault : public trap_access { +class trap_load_access_fault : public trap_access { +public: trap_load_access_fault(uint64_t badaddr) : trap_access(5 << 16, badaddr) {} }; -struct illegal_instruction_fault : public trap_access { +class illegal_instruction_fault : public trap_access { +public: illegal_instruction_fault(uint64_t badaddr) : trap_access(2 << 16, badaddr) {} }; -struct trap_instruction_page_fault : public trap_access { +class trap_instruction_page_fault : public trap_access { +public: trap_instruction_page_fault(uint64_t badaddr) : trap_access(12 << 16, badaddr) {} }; -struct trap_load_page_fault : public trap_access { +class trap_load_page_fault : public trap_access { +public: trap_load_page_fault(uint64_t badaddr) : trap_access(13 << 16, badaddr) {} }; -struct trap_store_page_fault : public trap_access { +class trap_store_page_fault : public trap_access { +public: trap_store_page_fault(uint64_t badaddr) : trap_access(15 << 16, badaddr) {} }; @@ -262,7 +267,8 @@ public: template struct hart_state { }; // specialization 32bit template - struct hart_state::value>::type> { + class hart_state::value>::type> { + public: BEGIN_BF_DECL(mstatus_t, T); // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) BF_FIELD(SD, 31, 1); @@ -328,7 +334,8 @@ public: }; // specialization 64bit template - struct hart_state::value>::type> { + class hart_state::value>::type> { + public: BEGIN_BF_DECL(mstatus_t, T); // SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR XS==11))) BF_FIELD(SD, 63, 1); diff --git a/riscv/incl/iss/arch/rv32imac.h b/riscv/incl/iss/arch/rv32imac.h index 607e5ad..7632b3b 100644 --- a/riscv/incl/iss/arch/rv32imac.h +++ b/riscv/incl/iss/arch/rv32imac.h @@ -43,10 +43,10 @@ namespace iss { namespace arch { -struct rv32imac; - -template <> struct traits { +class rv32imac; +template <> class traits { +public: enum constants { XLEN = 32, XLEN2 = 64, @@ -132,8 +132,8 @@ template <> struct traits { enum mem_type_e { MEM, CSR, FENCE, RES }; }; -struct rv32imac : public arch_if { - +class rv32imac : public arch_if { +public: using virt_addr_t = typename traits::virt_addr_t; using phys_addr_t = typename traits::phys_addr_t; using reg_t = typename traits::reg_t; diff --git a/riscv/incl/iss/arch/rv64ia.h b/riscv/incl/iss/arch/rv64ia.h index 3b8f611..6a32c8d 100644 --- a/riscv/incl/iss/arch/rv64ia.h +++ b/riscv/incl/iss/arch/rv64ia.h @@ -43,10 +43,10 @@ namespace iss { namespace arch { -struct rv64ia; - -template <> struct traits { +class rv64ia; +template <> class traits { +public: enum constants { XLEN = 64, XLEN2 = 128, @@ -131,8 +131,8 @@ template <> struct traits { enum mem_type_e { MEM, CSR, FENCE, RES }; }; -struct rv64ia : public arch_if { - +class rv64ia : public arch_if { +public: using virt_addr_t = typename traits::virt_addr_t; using phys_addr_t = typename traits::phys_addr_t; using reg_t = typename traits::reg_t; diff --git a/riscv/incl/iss/debugger/riscv_target_adapter.h b/riscv/incl/iss/debugger/riscv_target_adapter.h index 1ec2f60..84eeeb9 100644 --- a/riscv/incl/iss/debugger/riscv_target_adapter.h +++ b/riscv/incl/iss/debugger/riscv_target_adapter.h @@ -21,8 +21,8 @@ namespace debugger { using namespace iss::arch; using namespace iss::debugger; -template struct riscv_target_adapter : public target_adapter_base { - +template class riscv_target_adapter : public target_adapter_base { +public: riscv_target_adapter(server_if *srv, iss::arch_if *core) : target_adapter_base(srv) , core(core) {} diff --git a/riscv/src/internal/vm_riscv.in.cpp b/riscv/src/internal/vm_riscv.in.cpp index ebe0844..fa7bfac 100644 --- a/riscv/src/internal/vm_riscv.in.cpp +++ b/riscv/src/internal/vm_riscv.in.cpp @@ -52,7 +52,8 @@ using namespace iss::arch; using namespace llvm; using namespace iss::debugger; -template struct vm_impl : public vm::vm_base { +template class vm_impl : public vm::vm_base { +public: using super = typename vm::vm_base; using virt_addr_t = typename super::virt_addr_t; using phys_addr_t = typename super::phys_addr_t; diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp index 79e32ae..d4385ad 100644 --- a/riscv/src/internal/vm_rv32imac.cpp +++ b/riscv/src/internal/vm_rv32imac.cpp @@ -52,7 +52,8 @@ using namespace iss::arch; using namespace llvm; using namespace iss::debugger; -template struct vm_impl : public vm::vm_base { +template class vm_impl : public vm::vm_base { +public: using super = typename vm::vm_base; using virt_addr_t = typename super::virt_addr_t; using phys_addr_t = typename super::phys_addr_t; diff --git a/riscv/src/internal/vm_rv64ia.cpp b/riscv/src/internal/vm_rv64ia.cpp index b9ad8e4..832884e 100644 --- a/riscv/src/internal/vm_rv64ia.cpp +++ b/riscv/src/internal/vm_rv64ia.cpp @@ -52,7 +52,8 @@ using namespace iss::arch; using namespace llvm; using namespace iss::debugger; -template struct vm_impl : public vm::vm_base { +template class vm_impl : public vm::vm_base { +public: using super = typename vm::vm_base; using virt_addr_t = typename super::virt_addr_t; using phys_addr_t = typename super::phys_addr_t; diff --git a/sc-components b/sc-components index 27001d6..db46dcd 160000 --- a/sc-components +++ b/sc-components @@ -1 +1 @@ -Subproject commit 27001d6707071fe4727c698c0f777d587dd99a60 +Subproject commit db46dcd39581618564bd3e589c95c36c277679ed