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Fixed clang-tidy warnings

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eyck committed 2017-09-22 22:19:25 +02:00
1 parent 6f0d7adbf0
commit 4ce4b2562b
12 files changed
+25 -338
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.cproject
+2 -313
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dbt-core
+1 -1
Submodule dbt-core updated: 7902b61b2c...f8b842549e.
riscv.sc/incl/sysc/SiFive/core_complex.h
+1 -1
View File
@@ -51,7 +51,7 @@ public:
sc_core::sc_in<bool> rst_i;
core_complex(sc_core::sc_module_name name);
virtual ~core_complex();
virtual ~core_complex() = default;
};
} /* namespace SiFive */
riscv.sc/incl/sysc/SiFive/gpio.h
+1 -1
View File
@@ -29,7 +29,7 @@ public:
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
gpio(sc_core::sc_module_name nm);
virtual ~gpio();
virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs
protected:
void clock_cb();
riscv.sc/incl/sysc/SiFive/plic.h
+1 -1
View File
@@ -29,7 +29,7 @@ public:
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
plic(sc_core::sc_module_name nm);
virtual ~plic();
virtual ~plic() override;
protected:
void clock_cb();
riscv.sc/incl/sysc/SiFive/spi.h
+1 -1
View File
@@ -29,7 +29,7 @@ public:
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
spi(sc_core::sc_module_name nm);
virtual ~spi();
virtual ~spi() override;
protected:
void clock_cb();
riscv.sc/incl/sysc/SiFive/uart.h
+1 -1
View File
@@ -29,7 +29,7 @@ public:
sc_core::sc_in<sc_core::sc_time> clk_i;
sc_core::sc_in<bool> rst_i;
uart(sc_core::sc_module_name nm);
virtual ~uart();
virtual ~uart() override;
protected:
void clock_cb();
riscv.sc/src/sysc/core_complex.cpp
-3
View File
@@ -43,9 +43,6 @@ core_complex::core_complex(sc_core::sc_module_name name) : sc_core::sc_module(na
// TODO Auto-generated constructor stub
}
core_complex::~core_complex() {
// TODO Auto-generated destructor stub
}
} /* namespace SiFive */
} /* namespace sysc */
riscv.sc/src/sysc/gpio.cpp
+3 -2
View File
@@ -29,10 +29,11 @@ gpio::gpio(sc_core::sc_module_name nm)
sensitive << rst_i;
}
gpio::~gpio() {}
void gpio::clock_cb() {}
gpio::~gpio() {
}
void gpio::reset_cb() {
if (rst_i.read())
regs->reset_start();
riscv/incl/iss/arch/riscv_hart_msu_vp.h
+9 -11
View File
@@ -240,7 +240,7 @@ struct trap_store_page_fault : public trap_access {
};
}
typedef union {
using mstatus32_t = union {
uint32_t val;
struct /*mstatus*/ {
uint32_t SD : 1, // SD bit is read-only and is set when either the FS or XS
@@ -277,9 +277,9 @@ typedef union {
uint32_t SD : 1, _WPRI4 : 11, MXR : 1, SUM : 1, _WPRI3 : 1, XS : 2, FS : 2, _WPRI2 : 8, UPIE : 1, _WPRI0 : 3,
UIE : 1;
} u;
} mstatus32_t;
} ;
typedef union {
using mstatus64_t = union {
uint64_t val;
struct /*mstatus*/ {
uint64_t SD : 1, // SD bit is read-only and is set when either the FS or XS
@@ -324,7 +324,7 @@ typedef union {
UXL : 2, // value of XLEN for U-mode
_WPRI3 : 12, MXR : 1, SUM : 1, _WPRI2 : 1, XS : 2, FS : 2, _WPRI1 : 8, UPIE : 1, _WPRI0 : 3, UIE : 1;
} u;
} mstatus64_t;
} ;
template <unsigned L> inline vm_info decode_vm_info(uint32_t state, uint64_t sptbr);
@@ -424,19 +424,19 @@ template <typename BASE> struct riscv_hart_msu_vp : public BASE {
}
riscv_hart_msu_vp();
virtual ~riscv_hart_msu_vp();
virtual ~riscv_hart_msu_vp() = default;
virtual void load_file(std::string name, int type = -1);
virtual phys_addr_t v2p(const iss::addr_t &addr);
virtual iss::status read(const iss::addr_t &addr, unsigned length, uint8_t *const data) override;
virtual iss::status write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) override;
iss::status read(const iss::addr_t &addr, unsigned length, uint8_t *const data) override;
iss::status write(const iss::addr_t &addr, unsigned length, const uint8_t *const data) override;
virtual uint64_t enter_trap(uint64_t flags) override { return riscv_hart_msu_vp::enter_trap(flags, fault_data); }
virtual uint64_t enter_trap(uint64_t flags, uint64_t addr) override;
virtual uint64_t leave_trap(uint64_t flags) override;
virtual void wait_until(uint64_t flags) override;
void wait_until(uint64_t flags) override;
virtual std::string get_additional_disass_info() {
std::stringstream s;
@@ -517,8 +517,6 @@ template <typename BASE> riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp() : mstatus_
csr_wr_cb[satp] = &riscv_hart_msu_vp<BASE>::write_satp;
}
template <typename BASE> riscv_hart_msu_vp<BASE>::~riscv_hart_msu_vp() {}
template <typename BASE> void riscv_hart_msu_vp<BASE>::load_file(std::string name, int type) {
FILE *fp = fopen(name.c_str(), "r");
if (fp) {
@@ -941,7 +939,7 @@ typename riscv_hart_msu_vp<BASE>::phys_addr_t riscv_hart_msu_vp<BASE>::v2p(const
return ret;
}
const access_type type = (access_type)(addr.getAccessType() & ~iss::DEBUG);
const auto type = (access_type)(addr.getAccessType() & ~iss::DEBUG);
uint32_t mode = type != iss::FETCH && bit_sub<17, 1>(mstatus_r) ? // MPRV
mode = bit_sub<11, 2>(mstatus_r)
: // MPV
riscv/src/main.cpp
+4 -2
View File
@@ -67,7 +67,7 @@ int main(int argc, char *argv[]) {
iss::init_jit(argc, argv);
bool dump = vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr;
std::unique_ptr<iss::vm_if> cpu{nullptr};
if (vm.count("rv64") == 1) {
if (vm.count("gdb-port") == 1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
@@ -102,7 +102,9 @@ int main(int argc, char *argv[]) {
} else {
cpu->reset();
}
return cpu->start(vm["cycles"].as<int64_t>());
int64_t cycles = -1;
cycles = vm["cycles"].as<int64_t>();
return cpu->start(cycles);
} catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"
<< std::endl;
sc-components
+1 -1
Submodule sc-components updated: a5c9101b71...8272a27a0e.