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7a9802f68b
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add SPI RTL representation
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2020-12-21 07:02:36 +00:00 |
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c50da08b18
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build on ubuntu20.04
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2020-08-11 11:22:05 +02:00 |
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6ee0cd1b29
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update submodule pointers
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2020-06-18 07:39:18 +02:00 |
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255b379c20
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Updated to latest versions
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2019-07-14 16:51:43 +02:00 |
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74601e280e
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Merge branch 'master' of https://git.minres.com/VP/RISCV.git
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2019-06-28 22:43:24 +02:00 |
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679f311c52
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Fixed clint interrupt method invokation
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2019-06-28 20:59:16 +02:00 |
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eb8365f4c3
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Updated SC-Components
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2019-04-11 05:40:02 +00:00 |
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cb3a0d8411
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Merge branch 'develop'
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2019-01-10 11:15:02 +00:00 |
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d5d236bf10
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Adapted changes in SCC
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2018-11-24 21:38:02 +01:00 |
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20b3665003
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Back-ported DVCon turorial changes
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2018-11-12 19:36:44 +01:00 |
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38099e3fc6
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Added ADC, H-Bridge and motor models, refactored project structure
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2018-07-28 09:45:49 +02:00 |
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