removes instruction decoder
This commit is contained in:
parent
0fd9c94067
commit
cb6af695b9
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@ -67,12 +67,12 @@ if(ENABLE_CODEGEN AND EXISTS ${GENERATOR_JAR})
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if(${CORE_NAME} STREQUAL "TGC_C")
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if(${CORE_NAME} STREQUAL "TGC_C")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.h.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}.h")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.h.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}.h")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_decoder.cpp.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}_decoder.cpp")
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#list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_decoder.cpp.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}_decoder.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/vm/interp/vm_${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/vm/interp/vm_${CORE_NAMEL}.cpp")
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else()
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else()
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.h.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}.h")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.h.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}.h")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_decoder.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}_decoder.cpp")
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#list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_decoder.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}_decoder.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/vm/interp/vm_${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/vm/interp/vm_${CORE_NAMEL}.cpp")
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endif()
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endif()
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_instr.yaml.gtl:${DBT_CORE_TGC_DIR}/${CORE_NAME}_instr.yaml")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_instr.yaml.gtl:${DBT_CORE_TGC_DIR}/${CORE_NAME}_instr.yaml")
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@ -1 +1 @@
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Subproject commit 18f33b4a6809997a4d73824c5fdb4dd7c70e626a
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Subproject commit feaa49d367e1c9a4d0e8df884ca27c46c05c01b2
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