refactors decoder as separate component
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parent
41116a975e
commit
0fd9c94067
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@ -56,7 +56,6 @@ set(JAVA_OPTS --add-modules ALL-SYSTEM --add-opens=java.base/java.io=ALL-UNNAMED
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--add-opens=java.rmi/java.rmi.server=ALL-UNNAMED --add-opens=java.sql/java.sql=ALL-UNNAMED)
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set(GENERATOR java ${JAVA_OPTS} -jar ${GENERATOR_JAR})
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set(REPO_DIR ${DBT_CORE_TGC_DIR}/gen_input/CoreDSL-Instruction-Set-Description)
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set(TMPL_DIR ${DBT_CORE_TGC_DIR}/gen_input/templates/)
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if(ENABLE_CODEGEN AND EXISTS ${GENERATOR_JAR})
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@ -65,35 +64,21 @@ if(ENABLE_CODEGEN AND EXISTS ${GENERATOR_JAR})
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string(TOUPPER ${BACKEND} BE_UPPER)
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string(TOLOWER ${CORE_NAME} CORE_NAMEL)
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if(EXISTS ${DBT_CORE_TGC_DIR}/generate.sh AND NOT EXISTS ${DBT_CORE_TGC_DIR}/incl/iss/arch/${CORE_NAMEL}.h)
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# make sure source file exist initially
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execute_process(
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COMMAND /bin/bash ${DBT_CORE_TGC_DIR}/../generate.sh -c $CORE_NAME -b $BACKEND
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WORKING_DIRECTORY ${DBT_CORE_TGC_DIR}/..
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RESULT_VARIABLE return_code)
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endif()
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if(${CORE_NAME} STREQUAL "TGC_C")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.h.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}.h")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_decoder.cpp.gtl:${DBT_CORE_TGC_DIR}/src/iss/arch/${CORE_NAMEL}_decoder.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src/vm/interp/vm_${CORE_NAMEL}.cpp")
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else()
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.h.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}.h")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_decoder.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/iss/arch/${CORE_NAMEL}_decoder.cpp")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl:${DBT_CORE_TGC_DIR}/src-gen/vm/interp/vm_${CORE_NAMEL}.cpp")
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endif()
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_instr.yaml.gtl:${DBT_CORE_TGC_DIR}/${CORE_NAME}_instr.yaml")
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list(APPEND ${CORE_NAME}_MAPPING -m "${TMPL_DIR}/CORENAME_cyles.txt.gtl:${DBT_CORE_TGC_DIR}/${CORE_NAME}_cycles.json:no")
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set(${CORE_NAME}_OUTPUT_FILES ${DBT_CORE_TGC_DIR}/incl/iss/arch/${CORE_NAMEL}.h ${DBT_CORE_TGC_DIR}/src/iss/${CORE_NAMEL}.cpp ${DBT_CORE_TGC_DIR}/src/vm/interp/vm_${CORE_NAMEL}.cpp)
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#add_custom_command(
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# COMMAND ${GENERATOR} -b ${BE_UPPER} -c ${CORE_NAME} -r ${REPO_DIR} ${${CORE_NAME}_MAPPING} ${INPUT_FILE}
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# DEPENDS ${GENERATOR_JAR} ${INPUT_FILE} ${TMPL_DIR}/CORENAME.h.gtl ${TMPL_DIR}/CORENAME.cpp.gtl ${TMPL_DIR}/${BACKEND}/CORENAME.cpp.gtl
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# OUTPUT ${${CORE_NAME}_OUTPUT_FILES}
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# COMMENT "Generating code for ${CORE_NAME}."
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# USES_TERMINAL VERBATIM
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#)
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if(NOT DEFINED ENV{CI})
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add_custom_target(${CORE_NAME}_cpp
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COMMAND ${GENERATOR} -b ${BE_UPPER} -c ${CORE_NAME} ${${CORE_NAME}_MAPPING} ${INPUT_FILE}
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2
coredsl
2
coredsl
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@ -1 +1 @@
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Subproject commit 7695153ef5acc042fa68bd3c8376fc6008636941
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Subproject commit ee31e383001a8b223571667ee041e42fde32c0e6
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@ -1 +1 @@
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Subproject commit e55026b8fe000ddb0c546a14967ac669b430cd65
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Subproject commit 00c4420f04b11be07e2b43c0f3ed59a0c855d214
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@ -1 +1 @@
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Subproject commit cb5375258a315b77f51bf8454ee7d8c9351fe636
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Subproject commit 18f33b4a6809997a4d73824c5fdb4dd7c70e626a
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