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mateo-patc
Author | SHA1 | Date | |
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d39fad0fbe |
@ -1,3 +1,4 @@
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---
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Language: Cpp
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# BasedOnStyle: LLVM
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# should be in line with IndentWidth
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@ -12,8 +13,8 @@ AllowAllParametersOfDeclarationOnNextLine: true
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AllowShortBlocksOnASingleLine: false
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AllowShortCaseLabelsOnASingleLine: false
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AllowShortFunctionsOnASingleLine: All
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AllowShortIfStatementsOnASingleLine: false
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AllowShortLoopsOnASingleLine: false
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AllowShortIfStatementsOnASingleLine: true
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AllowShortLoopsOnASingleLine: true
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AlwaysBreakAfterDefinitionReturnType: None
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AlwaysBreakAfterReturnType: None
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AlwaysBreakBeforeMultilineStrings: false
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@ -38,8 +39,8 @@ BreakBeforeTernaryOperators: true
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BreakConstructorInitializersBeforeComma: true
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BreakAfterJavaFieldAnnotations: false
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BreakStringLiterals: true
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ColumnLimit: 120
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CommentPragmas: '^ IWYU pragma:'
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ConstructorInitializerAllOnOneLineOrOnePerLine: false
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ConstructorInitializerIndentWidth: 0
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ContinuationIndentWidth: 4
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@ -75,13 +76,13 @@ PenaltyBreakFirstLessLess: 120
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PointerAlignment: Left
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PointerAlignment: Right
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ReflowComments: true
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SortIncludes: true
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SpaceAfterCStyleCast: false
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SpaceAfterTemplateKeyword: true
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SpaceBeforeAssignmentOperators: true
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SpaceBeforeParens: Never
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SpaceBeforeParens: ControlStatements
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SpaceInEmptyParentheses: false
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SpacesBeforeTrailingComments: 1
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SpacesInAngles: false
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|
@ -1,3 +0,0 @@
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---
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Checks: 'clang-diagnostic-*,clang-analyzer-*,clang-diagnostic-*,clang-analyzer-*'
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WarningsAsErrors: ''
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266
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266
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<folderInfo id="cdt.managedbuild.toolchain.gnu.base.2088633632.189704729." name="/" resourcePath="">
|
||||
<toolChain id="cdt.managedbuild.toolchain.gnu.base.1533669881" name="Linux GCC" nonInternalBuilderId="de.marw.cdt.cmake.core.genscriptbuilder" superClass="cdt.managedbuild.toolchain.gnu.base">
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF;org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.base.1980352144" name="Debug Platform" osList="linux,hpux,aix,qnx" superClass="cdt.managedbuild.target.gnu.platform.base"/>
|
||||
<builder buildPath="/SystemC-Components-Test/build/Debug" id="de.marw.cdt.cmake.core.genscriptbuilder.1624220242" keepEnvironmentInBuildfile="false" name="CMake Builder" parallelBuildOn="true" parallelizationNumber="12" superClass="de.marw.cdt.cmake.core.genscriptbuilder"/>
|
||||
<tool id="cdt.managedbuild.tool.gnu.archiver.base.1454830600" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
|
||||
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.base.2080395177" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.base">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.417030753" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="cdt.managedbuild.tool.gnu.c.compiler.base.1370621613" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.base">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.2047855378" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="cdt.managedbuild.tool.gnu.c.linker.base.1443225475" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.base">
|
||||
<option defaultValue="true" id="gnu.c.link.option.shared.744235987" name="Shared (-shared)" superClass="gnu.c.link.option.shared" valueType="boolean"/>
|
||||
</tool>
|
||||
<tool id="cdt.managedbuild.tool.gnu.cpp.linker.base.1807518655" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.base">
|
||||
<option defaultValue="true" id="gnu.cpp.link.option.shared.1677301696" name="Shared (-shared)" superClass="gnu.cpp.link.option.shared" valueType="boolean"/>
|
||||
<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.963702466" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="cdt.managedbuild.tool.gnu.assembler.base.1835960936" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.base">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1907222697" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule buildDir="build/${ConfigName}" dirtyTs="1703253448607" moduleId="de.marw.cmake4eclipse.mbs.settings">
|
||||
<storageModule buildDir="build/${ConfigName}" moduleId="de.marw.cdt.cmake.core.settings">
|
||||
<options/>
|
||||
<linux command="cmake" generator="UnixMakefiles" use-default="true">
|
||||
</linux>
|
||||
<win32 command="cmake" generator="MinGWMakefiles" use-default="true">
|
||||
</win32>
|
||||
<defs>
|
||||
<def name="CMAKE_BUILD_TYPE" type="STRING" val="Debug"/>
|
||||
<def name="BUILD_SCC_DOCUMENTATION" type="BOOL" val="OFF"/>
|
||||
<def name="ENABLE_CLANG_TIDY" type="STRING" val="ON"/>
|
||||
<def name="CMAKE_BUILD_TYPE" type="STRING" val="${ConfigName}"/>
|
||||
<def name="NO_SUBMODULE_CHECK" type="STRING" val="TRUE"/>
|
||||
<def name="ENABLE_CLANG_TIDY" type="BOOL" val="ON"/>
|
||||
</defs>
|
||||
<undefs/>
|
||||
</storageModule>
|
||||
</cconfiguration>
|
||||
<cconfiguration id="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257">
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257" moduleId="org.eclipse.cdt.core.settings" name="RelWithDebInfo">
|
||||
<externalSettings/>
|
||||
<extensions>
|
||||
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
</extensions>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactName="${ProjName}" buildProperties="" description="" id="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257" name="RelWithDebInfo" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.enablement=false,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="org.eclipse.cdt.build.core.emptycfg">
|
||||
<folderInfo id="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257." name="/" resourcePath="">
|
||||
<toolChain id="cdt.managedbuild.toolchain.gnu.base.1034987349" name="Linux GCC" nonInternalBuilderId="de.marw.cdt.cmake.core.genscriptbuilder" superClass="cdt.managedbuild.toolchain.gnu.base">
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.GNU_ELF;org.eclipse.cdt.core.ELF" id="cdt.managedbuild.target.gnu.platform.base.1322268158" name="Debug Platform" osList="linux,hpux,aix,qnx" superClass="cdt.managedbuild.target.gnu.platform.base"/>
|
||||
<builder buildPath="/SystemC-Components-Test/build/Release" id="de.marw.cdt.cmake.core.genscriptbuilder.1768026598" keepEnvironmentInBuildfile="false" name="CMake Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="de.marw.cdt.cmake.core.genscriptbuilder"/>
|
||||
<tool id="cdt.managedbuild.tool.gnu.archiver.base.1250964668" name="GCC Archiver" superClass="cdt.managedbuild.tool.gnu.archiver.base"/>
|
||||
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.base.115120293" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.base">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1734129580" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="cdt.managedbuild.tool.gnu.c.compiler.base.472854336" name="GCC C Compiler" superClass="cdt.managedbuild.tool.gnu.c.compiler.base">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1116994769" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
|
||||
</tool>
|
||||
<tool id="cdt.managedbuild.tool.gnu.c.linker.base.400939074" name="GCC C Linker" superClass="cdt.managedbuild.tool.gnu.c.linker.base"/>
|
||||
<tool id="cdt.managedbuild.tool.gnu.cpp.linker.base.346574626" name="GCC C++ Linker" superClass="cdt.managedbuild.tool.gnu.cpp.linker.base">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.2024821854" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
|
||||
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
|
||||
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
|
||||
</inputType>
|
||||
</tool>
|
||||
<tool id="cdt.managedbuild.tool.gnu.assembler.base.1925887219" name="GCC Assembler" superClass="cdt.managedbuild.tool.gnu.assembler.base">
|
||||
<inputType id="cdt.managedbuild.tool.gnu.assembler.input.341131009" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
|
||||
</tool>
|
||||
</toolChain>
|
||||
</folderInfo>
|
||||
</configuration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule buildDir="build/${ConfigName}" moduleId="de.marw.cdt.cmake.core.settings">
|
||||
<options/>
|
||||
<linux command="cmake" generator="UnixMakefiles" use-default="true">
|
||||
<defs/>
|
||||
<undefs/>
|
||||
</linux>
|
||||
<win32 command="cmake" generator="MinGWMakefiles" use-default="true">
|
||||
<defs/>
|
||||
<undefs/>
|
||||
</win32>
|
||||
<defs>
|
||||
<def name="CMAKE_BUILD_TYPE" type="STRING" val="${ConfigName}"/>
|
||||
</defs>
|
||||
<undefs/>
|
||||
</storageModule>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="SystemC-Components-Test.null.276784792" name="SystemC-Components-Test"/>
|
||||
<project id="SystemC-Components-Test.null.720884563" name="SystemC-Components-Test"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
<configuration configurationName="ClangTidy">
|
||||
<resource resourceType="PROJECT" workspacePath="/SystemC-Components-Test"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Debug+Tidy"/>
|
||||
<configuration configurationName="Default">
|
||||
<resource resourceType="PROJECT" workspacePath="/SystemC-Components-Test"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Debug"/>
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="FOLDER" workspacePath="/SystemC-Components-Test/build"/>
|
||||
</configuration>
|
||||
<configuration configurationName="Release"/>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
|
||||
<storageModule cmakelistsFolder="" moduleId="de.marw.cmake4eclipse.mbs.settings">
|
||||
<targets>
|
||||
<target name=""/>
|
||||
</targets>
|
||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="cmake4eclipse.mbs.toolchain.cmake.134761605;cmake4eclipse.mbs.toolchain.cmake.134761605.1159094612;cmake4eclipse.mbs.toolchain.tool.dummy.326050058;cmake4eclipse.mbs.inputType.c.1524512146">
|
||||
<scannerConfigBuildInfo instanceId="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890;cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.;cdt.managedbuild.tool.gnu.cpp.compiler.base.1213265767;cdt.managedbuild.tool.gnu.cpp.compiler.input.2118017099">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="cmake4eclipse.mbs.toolchain.cmake.134761605.1198783022;cmake4eclipse.mbs.toolchain.cmake.134761605.1198783022.;cmake4eclipse.mbs.toolchain.tool.dummy.1269675407;cmake4eclipse.mbs.inputType.c.2145364949">
|
||||
<scannerConfigBuildInfo instanceId="cdt.managedbuild.toolchain.gnu.base.2088633632;cdt.managedbuild.toolchain.gnu.base.2088633632.654284138;cdt.managedbuild.tool.gnu.cpp.compiler.base.2062399929;cdt.managedbuild.tool.gnu.cpp.compiler.input.770113519">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="cmake4eclipse.mbs.toolchain.cmake.134761605;cmake4eclipse.mbs.toolchain.cmake.134761605.1159094612;cmake4eclipse.mbs.toolchain.tool.dummy.326050058;cmake4eclipse.mbs.inputType.cpp.459033018">
|
||||
<scannerConfigBuildInfo instanceId="cdt.managedbuild.toolchain.gnu.base.2088633632;cdt.managedbuild.toolchain.gnu.base.2088633632.654284138;cdt.managedbuild.tool.gnu.c.compiler.base.1686982336;cdt.managedbuild.tool.gnu.c.compiler.input.1800687036">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="cmake4eclipse.mbs.toolchain.cmake.134761605.1198783022;cmake4eclipse.mbs.toolchain.cmake.134761605.1198783022.;cmake4eclipse.mbs.toolchain.tool.dummy.1269675407;cmake4eclipse.mbs.inputType.cpp.143816444">
|
||||
<scannerConfigBuildInfo instanceId="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890;cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.;cdt.managedbuild.tool.gnu.c.compiler.base.1199035274;cdt.managedbuild.tool.gnu.c.compiler.input.471260944">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
</storageModule>
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
|
||||
<buildTargets>
|
||||
<target name="test" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
|
||||
<buildCommand>make</buildCommand>
|
||||
<buildCommand>CMAKE_BUILD_TOOL</buildCommand>
|
||||
<buildArguments>$<cmake4eclipse_dyn></buildArguments>
|
||||
<buildTarget>test</buildTarget>
|
||||
<stopOnError>true</stopOnError>
|
||||
<useDefaultCommand>true</useDefaultCommand>
|
||||
<runAllBuilders>true</runAllBuilders>
|
||||
</target>
|
||||
<target name="format" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
|
||||
<buildCommand>make</buildCommand>
|
||||
<buildArguments>$<cmake4eclipse_dyn></buildArguments>
|
||||
<buildTarget>format</buildTarget>
|
||||
<stopOnError>true</stopOnError>
|
||||
<useDefaultCommand>true</useDefaultCommand>
|
||||
<runAllBuilders>true</runAllBuilders>
|
||||
</target>
|
||||
<target name="format-check" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
|
||||
<buildCommand>make</buildCommand>
|
||||
<buildArguments>$<cmake4eclipse_dyn></buildArguments>
|
||||
<buildTarget>format-check</buildTarget>
|
||||
<stopOnError>true</stopOnError>
|
||||
<useDefaultCommand>true</useDefaultCommand>
|
||||
<runAllBuilders>true</runAllBuilders>
|
||||
</target>
|
||||
</buildTargets>
|
||||
</storageModule>
|
||||
</cproject>
|
||||
</cproject>
|
||||
|
10
.envrc
10
.envrc
@ -1,10 +0,0 @@
|
||||
module load ./Modulefile
|
||||
distro=`/bin/lsb_release -i -s`
|
||||
if [ $distro == "CentOS" ]; then
|
||||
. /opt/rh/devtoolset-8/enable
|
||||
. /opt/rh/rh-python38/enable
|
||||
elif [ $distro == "Rocky" ]; then
|
||||
. /opt/rh/gcc-toolset-11/enable
|
||||
fi
|
||||
layout python3
|
||||
[ -f .envrc.$USER ] && . .envrc.$USER
|
13
.gitignore
vendored
13
.gitignore
vendored
@ -34,16 +34,3 @@
|
||||
/build/
|
||||
/simple_system.txlog
|
||||
/my_db*
|
||||
/.settings/
|
||||
/Debug/
|
||||
/*.txlog
|
||||
/*.vcd
|
||||
/.venv/
|
||||
/.pydevproject
|
||||
/*.fst
|
||||
/*.ftr
|
||||
/*.gtkw
|
||||
/.envrc.*
|
||||
/.direnv/
|
||||
/.venv/
|
||||
/.cache
|
||||
|
5
.project
5
.project
@ -5,11 +5,6 @@
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.python.pydev.PyDevBuilder</name>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
|
53
.settings/language.settings.xml
Normal file
53
.settings/language.settings.xml
Normal file
@ -0,0 +1,53 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project>
|
||||
<configuration id="cdt.managedbuild.toolchain.gnu.base.2088633632" name="Debug">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1471514668944563477" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="de.marw.cmake.cdt.language.settings.providers.CompileCommandsJsonParser" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
<configuration id="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890" name="Release">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1471514668944563477" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
<configuration id="cdt.managedbuild.toolchain.gnu.base.2088633632.189704729" name="Debug+Tidy">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1471514668944563477" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider-reference id="de.marw.cmake.cdt.language.settings.providers.CompileCommandsJsonParser" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
<configuration id="cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257" name="RelWithDebInfo">
|
||||
<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
|
||||
<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
|
||||
<provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
|
||||
<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-1471514668944563477" id="org.eclipse.cdt.managedbuilder.core.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD "${INPUTS}"" prefer-non-shared="true">
|
||||
<language-scope id="org.eclipse.cdt.core.gcc"/>
|
||||
<language-scope id="org.eclipse.cdt.core.g++"/>
|
||||
</provider>
|
||||
<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
|
||||
</extension>
|
||||
</configuration>
|
||||
</project>
|
37
.settings/org.eclipse.cdt.managedbuilder.core.prefs
Normal file
37
.settings/org.eclipse.cdt.managedbuilder.core.prefs
Normal file
@ -0,0 +1,37 @@
|
||||
eclipse.preferences.version=1
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/CPATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/CPATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/CPLUS_INCLUDE_PATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/CPLUS_INCLUDE_PATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/C_INCLUDE_PATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/C_INCLUDE_PATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/append=true
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/appendContributed=true
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/CPATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/CPATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/CPLUS_INCLUDE_PATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/CPLUS_INCLUDE_PATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/C_INCLUDE_PATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/C_INCLUDE_PATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/append=true
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/appendContributed=true
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/CPATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/CPATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/CPLUS_INCLUDE_PATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/CPLUS_INCLUDE_PATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/C_INCLUDE_PATH/delimiter=\:
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/C_INCLUDE_PATH/operation=remove
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/append=true
|
||||
environment/buildEnvironmentInclude/cdt.managedbuild.toolchain.gnu.base.2088633632/appendContributed=true
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/LIBRARY_PATH/delimiter=\:
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/LIBRARY_PATH/operation=remove
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/append=true
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890.1052785257/appendContributed=true
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/LIBRARY_PATH/delimiter=\:
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/LIBRARY_PATH/operation=remove
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/append=true
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632.342506890/appendContributed=true
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632/LIBRARY_PATH/delimiter=\:
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632/LIBRARY_PATH/operation=remove
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632/append=true
|
||||
environment/buildEnvironmentLibrary/cdt.managedbuild.toolchain.gnu.base.2088633632/appendContributed=true
|
25
.vscode/launch.json
vendored
25
.vscode/launch.json
vendored
@ -1,25 +0,0 @@
|
||||
{
|
||||
// Use IntelliSense to learn about possible attributes.
|
||||
// Hover to view descriptions of existing attributes.
|
||||
// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387
|
||||
"version": "0.2.0",
|
||||
"configurations": [{
|
||||
"name": "cci_param_restricted",
|
||||
"type": "cppdbg",
|
||||
"request": "launch",
|
||||
"cwd": "${workspaceRoot}",
|
||||
"program": "${workspaceRoot}/build/tests/cci_param_restricted/cci_param_restricted",
|
||||
"linux": {
|
||||
"MIMode": "gdb",
|
||||
"miDebuggerPath": "/usr/bin/gdb"
|
||||
},
|
||||
"setupCommands": [
|
||||
{
|
||||
"description": "Enable pretty-printing for gdb",
|
||||
"text": "-enable-pretty-printing",
|
||||
"ignoreFailures": true
|
||||
}
|
||||
],
|
||||
"preLaunchTask": "CMake: build"
|
||||
}]
|
||||
}
|
16
.vscode/tasks.json
vendored
16
.vscode/tasks.json
vendored
@ -1,16 +0,0 @@
|
||||
{
|
||||
"version": "2.0.0",
|
||||
"tasks": [
|
||||
{
|
||||
"type": "cmake",
|
||||
"label": "CMake: build",
|
||||
"command": "build",
|
||||
"targets": [
|
||||
"all"
|
||||
],
|
||||
"group": "build",
|
||||
"problemMatcher": ["$gcc"],
|
||||
"detail": "CMake template build task",
|
||||
}
|
||||
]
|
||||
}
|
@ -1,18 +1,36 @@
|
||||
cmake_minimum_required(VERSION 3.16)
|
||||
list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/scc/cmake)
|
||||
cmake_policy(SET CMP0110 NEW)
|
||||
cmake_minimum_required(VERSION 3.12)
|
||||
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake ${CMAKE_CURRENT_SOURCE_DIR}/scc/cmake)
|
||||
|
||||
project(SCC_Test)
|
||||
|
||||
option(FULL_TEST_SUITE "enable also long-running tests" OFF)
|
||||
option(ENABLE_SCV "Enable use of SCV" OFF)
|
||||
option(ENABLE_CLANG_TIDY "Enable clang-tidy checks" OFF)
|
||||
set(ENABLE_SCV TRUE CACHE BOOL "Enable use of SCV")
|
||||
|
||||
set(ENABLE_SHARED TRUE CACHE BOOL "Build shared libraries")
|
||||
|
||||
set(NO_SUBMODULE_CHECK FALSE CACHE BOOL "Disable the submodule check")
|
||||
|
||||
set(ENABLE_CLANG_TIDY FALSE CACHE BOOL "Enable clang-tidy checks")
|
||||
include(GitFunctions)
|
||||
get_info_from_git()
|
||||
|
||||
### set the directory names of the submodules
|
||||
set(GIT_SUBMODULES scc)
|
||||
set(GIT_SUBMODULE_DIR_sc-components .)
|
||||
### set each submodules's commit or tag that is to be checked out
|
||||
### (leave empty if you want master)
|
||||
#set(GIT_SUBMODULE_VERSION_sc-components 3af6b9836589b082c19d9131c5d0b7afa8ddd7cd)
|
||||
set(GIT_SUBMODULE_BRANCH_sc-components ${GIT_BRANCH})
|
||||
|
||||
include(ConanInline)
|
||||
include(GNUInstallDirs)
|
||||
if(NOT NO_SUBMODULE_CHECK)
|
||||
include(Submodules)
|
||||
endif()
|
||||
include(Conan)
|
||||
include(BuildType)
|
||||
|
||||
set(CMAKE_CXX_STANDARD 14)
|
||||
#enable_testing()
|
||||
|
||||
set(CMAKE_CXX_STANDARD 11)
|
||||
set(CMAKE_CXX_STANDARD_REQUIRED ON)
|
||||
set(CMAKE_CXX_EXTENSIONS OFF)
|
||||
set(CMAKE_POSITION_INDEPENDENT_CODE ON)
|
||||
@ -42,44 +60,50 @@ if(ENABLE_COVERAGE)
|
||||
set(COVERAGE_EXCLUDES "osci-lib/scc/*" "/engr/dev/tools/*")
|
||||
endif()
|
||||
|
||||
find_program(CLANG_TIDY_EXE NAMES "clang-tidy")
|
||||
find_program(CLANG_TIDY_EXE NAMES "clang-tidy-9")
|
||||
if(ENABLE_CLANG_TIDY)
|
||||
if(CLANG_TIDY_EXE)
|
||||
message(STATUS "clang-tidy found: ${CLANG_TIDY_EXE}")
|
||||
#set(CLANG_TIDY_CHECKS "-*,modernize-*,-modernize-use-trailing-return-type,clang-analyzer-core.*,clang-analyzer-cplusplus.*")
|
||||
set(CMAKE_CXX_CLANG_TIDY ${CLANG_TIDY_EXE};-fix)
|
||||
else()
|
||||
message(AUTHOR_WARNING "clang-tidy not found!")
|
||||
set(CMAKE_CXX_CLANG_TIDY "" CACHE STRING "" FORCE) # delete it
|
||||
endif()
|
||||
if(CLANG_TIDY_EXE)
|
||||
message(STATUS "clang-tidy found: ${CLANG_TIDY_EXE}")
|
||||
set(CLANG_TIDY_CHECKS "-*,modernize-*,-modernize-use-trailing-return-type,clang-analyzer-core.*,clang-analyzer-cplusplus.*")
|
||||
set(CMAKE_CXX_CLANG_TIDY
|
||||
${CLANG_TIDY_EXE};
|
||||
-checks=${CLANG_TIDY_CHECKS};
|
||||
-fix;)
|
||||
else()
|
||||
message(AUTHOR_WARNING "clang-tidy not found!")
|
||||
set(CMAKE_CXX_CLANG_TIDY "" CACHE STRING "" FORCE) # delete it
|
||||
endif()
|
||||
endif()
|
||||
|
||||
set(CLANG_FORMAT_EXCLUDE_PATTERNS "/third_party/")
|
||||
find_package(ClangFormat)
|
||||
setup_conan(TARGETS)
|
||||
|
||||
set(CONAN_CMAKE_SILENT_OUTPUT ON)
|
||||
conan_check()
|
||||
conan_configure(REQUIRES jsoncpp/1.9.5 yaml-cpp/0.6.3 spdlog/1.9.2 fmt/8.0.1 boost/1.85.0 gsl-lite/0.37.0 systemc/2.3.4 catch2/3.1.0 zlib/1.2.11 lz4/1.9.4
|
||||
GENERATORS cmake_find_package
|
||||
OPTIONS fmt:header_only=True spdlog:header_only=True
|
||||
)
|
||||
conan_install()
|
||||
|
||||
find_package(ZLIB)
|
||||
find_package(lz4)
|
||||
# This line finds the boost lib and headers.
|
||||
set(Boost_NO_BOOST_CMAKE ON) # Don't do a find_package in config mode before searching for a regular boost install.
|
||||
find_package(Boost COMPONENTS program_options filesystem system thread REQUIRED)
|
||||
find_package(fmt REQUIRED)
|
||||
find_package(spdlog REQUIRED)
|
||||
find_package(Catch2)
|
||||
|
||||
include(SystemCPackage)
|
||||
include(CTest)
|
||||
include(Catch)
|
||||
# set-up SystemC and SCV
|
||||
find_package(OSCISystemC)
|
||||
if(NOT SystemC_FOUND)
|
||||
message( FATAL_ERROR "SystemC library not found." )
|
||||
endif()
|
||||
|
||||
enable_testing()
|
||||
|
||||
add_subdirectory(scc)
|
||||
add_subdirectory(src)
|
||||
add_subdirectory(examples)
|
||||
add_subdirectory(tests)
|
||||
|
||||
#
|
||||
# SYSTEM PACKAGING (RPM, TGZ, ...)
|
||||
# _____________________________________________________________________________
|
||||
|
||||
#include(CPackConfig)
|
||||
|
||||
#
|
||||
# CMAKE PACKAGING (for other CMake projects to use this one easily)
|
||||
# _____________________________________________________________________________
|
||||
|
||||
#include(PackageConfigurator)
|
||||
|
||||
#include(FeatureSummary)
|
||||
#feature_summary(WHAT ENABLED_FEATURES DISABLED_FEATURES PACKAGES_FOUND)
|
||||
|
122
Jenkinsfile
vendored
122
Jenkinsfile
vendored
@ -1,26 +1,13 @@
|
||||
def getBranch() {
|
||||
if (env.BRANCH_NAME != null && !env.BRANCH_NAME.isEmpty() ) {
|
||||
return env.BRANCH_NAME
|
||||
} else {
|
||||
return 'develop'
|
||||
}
|
||||
}
|
||||
|
||||
void checkout_project() {
|
||||
checkout([
|
||||
$class: 'GitSCM',
|
||||
branches: [
|
||||
[name: 'refs/heads/' + getBranch()]
|
||||
],
|
||||
branches: [
|
||||
[name: '*/master']
|
||||
],
|
||||
doGenerateSubmoduleConfigurations: false,
|
||||
extensions: [
|
||||
[$class: 'CleanBeforeCheckout'],
|
||||
[$class: 'SubmoduleOption',
|
||||
disableSubmodules: false,
|
||||
recursiveSubmodules: true,
|
||||
trackingSubmodules: false,
|
||||
parentCredentials: true,
|
||||
shallow: true
|
||||
]
|
||||
[$class: 'SubmoduleOption', disableSubmodules: false, parentCredentials: true, recursiveSubmodules: true, reference: '', trackingSubmodules: false]
|
||||
],
|
||||
submoduleCfg: [],
|
||||
userRemoteConfigs: [
|
||||
@ -29,21 +16,30 @@ void checkout_project() {
|
||||
])
|
||||
}
|
||||
|
||||
void setup_conan() {
|
||||
sh'''
|
||||
pip3 install --user "conan<2.0" pyucis
|
||||
void setup_conan_stdc() {
|
||||
sh"""
|
||||
conan profile new default --detect --force
|
||||
conan remote list | grep minres > /dev/null
|
||||
[ $? ] || conan remote add minres https://git.minres.com/api/packages/Tooling/conan
|
||||
'''
|
||||
conan profile update settings.compiler.libcxx=libstdc++ default
|
||||
"""
|
||||
}
|
||||
|
||||
void build_n_test_project() {
|
||||
sh'''
|
||||
cmake -S . -B build
|
||||
cmake --build build -j12
|
||||
cmake --build build --target test
|
||||
'''
|
||||
void setup_conan_stdc11() {
|
||||
sh"""
|
||||
conan profile new default --detect --force
|
||||
conan profile update settings.compiler.libcxx=libstdc++11 default
|
||||
"""
|
||||
}
|
||||
|
||||
void build_project() {
|
||||
sh"""
|
||||
mkdir build; cd build
|
||||
cmake .. -DCMAKE_BUILD_TYPE=Release
|
||||
make -j10 VERBOSE=1
|
||||
"""
|
||||
}
|
||||
|
||||
void test_project() {
|
||||
sh 'cd build; ctest -C Debug -V -j10 '
|
||||
}
|
||||
|
||||
pipeline {
|
||||
@ -57,50 +53,40 @@ pipeline {
|
||||
stages {
|
||||
stage('SCC test pipeline') {
|
||||
parallel {
|
||||
stage('U22.04') {
|
||||
agent {docker { image 'ubuntu-22.04' } }
|
||||
stage('U18.04') {
|
||||
agent {docker { image 'ubuntu-18.04' } }
|
||||
stages {
|
||||
stage('Checkout') { steps { checkout_project() }}
|
||||
stage('Setup') { steps { setup_conan() }}
|
||||
stage('Build & test') { steps { build_n_test_project() }}
|
||||
stage('Ubuntu18.04: checkout') { steps { checkout_project() }}
|
||||
stage('Ubuntu18.04: Conan') { steps { setup_conan_stdc11() }}
|
||||
stage('Ubuntu18.04: Build') { steps { build_project() }}
|
||||
stage('Ubuntu18.04: Test') { steps { test_project() }}
|
||||
}
|
||||
}
|
||||
stage('U20.04') {
|
||||
agent {docker { image 'ubuntu-20.04' } }
|
||||
stages {
|
||||
stage('Checkout') { steps { checkout_project() }}
|
||||
stage('Setup') { steps { setup_conan() }}
|
||||
stage('Build & test') { steps { build_n_test_project() }}
|
||||
stage('Ubuntu20.04: checkout') { steps { checkout_project() }}
|
||||
stage('Ubuntu20.04: Conan') { steps { setup_conan_stdc11() }}
|
||||
stage('Ubuntu20.04: Build') { steps { build_project() }}
|
||||
stage('Ubuntu20.04: Test') { steps { test_project() }}
|
||||
}
|
||||
}
|
||||
stage('COS7') {
|
||||
agent {docker { image 'centos7' } }
|
||||
stages {
|
||||
stage('Checkout') { steps { checkout_project() }}
|
||||
stage('Setup') { steps { setup_conan() }}
|
||||
stage('Build & test') { steps { build_n_test_project() }}
|
||||
stage('CentOS7: checkout') { steps { checkout_project() }}
|
||||
stage('CentOS7: conan') { steps { setup_conan_stdc() }}
|
||||
stage('CentOS7: build') { steps { build_project() }}
|
||||
stage('CentOS7: test') { steps { test_project() }}
|
||||
}
|
||||
}
|
||||
stage('RCK8') {
|
||||
agent {docker { image 'rockylinux8' } }
|
||||
stage('COS8') {
|
||||
agent {docker { image 'centos8' } }
|
||||
stages {
|
||||
stage('Checkout') { steps { checkout_project() }}
|
||||
stage('Setup') { steps { setup_conan() }}
|
||||
stage('Build & test') { steps { build_n_test_project() }}
|
||||
}
|
||||
}
|
||||
//
|
||||
stage('Format check') {
|
||||
agent {docker { image 'ubuntu-riscv' } }
|
||||
stages {
|
||||
stage('Checkout') { steps { checkout_project() }}
|
||||
stage('Setup') { steps { setup_conan() }}
|
||||
stage('Build & check format') { steps {
|
||||
sh'''
|
||||
cmake -S . -B build
|
||||
cmake --build build --target format-check
|
||||
'''
|
||||
}}
|
||||
stage('CentOS8: checkout') { steps { checkout_project() }}
|
||||
stage('CentOS8: conan') { steps { setup_conan_stdc11() }}
|
||||
stage('CentOS8: build') { steps { build_project() }}
|
||||
stage('CentOS8: test') { steps { test_project() }}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -109,16 +95,12 @@ pipeline {
|
||||
|
||||
post {
|
||||
success {
|
||||
rocketSend ":thumbsup: SCC test run passed, results at ${env.RUN_DISPLAY_URL} "
|
||||
echo 'SCC tests PASSED!'
|
||||
}
|
||||
failure {
|
||||
rocketSend ":thumbsdown: SCC test failed, please check ${env.RUN_DISPLAY_URL} "
|
||||
emailext recipientProviders: [culprits(), requestor()],
|
||||
subject: "SCC Test Pipeline Failed: ${currentBuild.fullDisplayName}",
|
||||
body: """
|
||||
<p>Build Status: ${currentBuild.currentResult}</p>
|
||||
<p> Check logs at <a href='${env.BUILD_URL}console'> Build Console Logs </a> or at <a href='${env.RUN_DISPLAY_URL}'> Overview </a></p>
|
||||
"""
|
||||
mail to: 'stas@minres.com',
|
||||
subject: "SCC Test Pipeline Failed: ${currentBuild.fullDisplayName}",
|
||||
body: "Something is wrong with ${env.BUILD_URL}"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
@ -12,6 +12,5 @@ if { $distro == "CentOS" && ![info exists ::env(PROJECT)] && ![info exists ::env
|
||||
puts stderr "Don't forget to execute 'scl enable devtoolset-7 llvm-toolset-7 bash'"
|
||||
}
|
||||
|
||||
module load tools/utilities
|
||||
module load tools/cmake
|
||||
module load tools/clang/14.0
|
||||
|
||||
|
37
README.md
37
README.md
@ -1,20 +1,29 @@
|
||||
[![Build Status](https://jenkins.minres.com/view/SystemC/job/SCC%20Test/job/develop/badge/icon)](https://jenkins.minres.com/view/SystemC/job/SCC%20Test/job/develop/)
|
||||
|
||||
# SystemC-Components-Test
|
||||
Examples and tests for the SystemC-Components
|
||||
|
||||
## Prerequisites:
|
||||
|
||||
In Console:
|
||||
|
||||
git clone --recursive -b develop https://git.minres.com/SystemC/SystemC-Components-Test.git
|
||||
cd SystemC-Components-Test/
|
||||
module load ./Modulefile
|
||||
python3 -mvenv .venv
|
||||
. .venv/bin/activate
|
||||
pip3 install conan==1.59.0
|
||||
cmake -S . -B build
|
||||
cmake --build build -j30
|
||||
|
||||
-Check for needed modules in ~/.bashrc #TODO add the specific requirements and versions of the modules
|
||||
they should be available directly in the linux installation if not, install it and add it to $PATH with:
|
||||
|
||||
export PATH="needed-path:$PATH"
|
||||
|
||||
-Edit bashrc and add:
|
||||
|
||||
./opt/shared/modules/4.4.1/init/bash
|
||||
module use /opt/shared/modules/modulefiles
|
||||
|
||||
at end of file.
|
||||
|
||||
-Install conan and run this comands:
|
||||
|
||||
module load ./Modulefile
|
||||
|
||||
conan profile new default --detect --force
|
||||
conan profile update settings.compiler.libcxx=libstdc++11 default
|
||||
|
||||
-Add conan to $PATH
|
||||
|
||||
|
||||
In SystemC Project:
|
||||
|
||||
-Check conanfile.txt for anomalies and requirements. #TODO add specific requirements.
|
||||
|
15
conanfile.txt
Normal file
15
conanfile.txt
Normal file
@ -0,0 +1,15 @@
|
||||
[requires]
|
||||
fmt/6.1.2
|
||||
boost/1.75.0
|
||||
gsl-lite/0.37.0
|
||||
systemc/2.3.3
|
||||
#systemc-scv/2.0.1
|
||||
systemc-cci/1.0.0
|
||||
|
||||
[generators]
|
||||
cmake
|
||||
|
||||
[options]
|
||||
fmt:header_only=True
|
||||
systemc:shared=True
|
||||
systemc-cci:shared=True
|
@ -1,111 +0,0 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
|
||||
[*] Sun Oct 2 10:21:33 2022
|
||||
[*]
|
||||
[dumpfile] "/home/eyck/git/SystemC-Components-Test/axi4_pin_level.vcd"
|
||||
[dumpfile_mtime] "Sun Oct 2 10:15:49 2022"
|
||||
[dumpfile_size] 129942
|
||||
[savefile] "/home/eyck/git/SystemC-Components-Test/contrib/axi4_pin_level.gtkw"
|
||||
[timestart] 0
|
||||
[size] 1956 1062
|
||||
[pos] 1287 112
|
||||
*-17.469423 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] SystemC.
|
||||
[treeopen] SystemC.testbench.
|
||||
[sst_width] 214
|
||||
[signals_width] 254
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 314
|
||||
@28
|
||||
SystemC.testbench.clk
|
||||
SystemC.testbench.rst
|
||||
@800200
|
||||
-AR
|
||||
@28
|
||||
SystemC.testbench.ar_valid
|
||||
SystemC.testbench.ar_ready
|
||||
@22
|
||||
SystemC.testbench.ar_addr[31:0]
|
||||
@28
|
||||
SystemC.testbench.ar_burst[1:0]
|
||||
@22
|
||||
SystemC.testbench.ar_cache[3:0]
|
||||
SystemC.testbench.ar_id[3:0]
|
||||
SystemC.testbench.ar_len[7:0]
|
||||
@28
|
||||
SystemC.testbench.ar_lock[1:0]
|
||||
SystemC.testbench.ar_prot[2:0]
|
||||
@22
|
||||
SystemC.testbench.ar_qos[3:0]
|
||||
SystemC.testbench.ar_region[3:0]
|
||||
@28
|
||||
SystemC.testbench.ar_size[2:0]
|
||||
SystemC.testbench.ar_user
|
||||
@1000200
|
||||
-AR
|
||||
@800200
|
||||
-R
|
||||
@28
|
||||
SystemC.testbench.r_valid
|
||||
SystemC.testbench.r_ready
|
||||
SystemC.testbench.r_last
|
||||
@22
|
||||
SystemC.testbench.r_data[63:0]
|
||||
SystemC.testbench.r_id[3:0]
|
||||
@28
|
||||
SystemC.testbench.r_resp[1:0]
|
||||
SystemC.testbench.r_user
|
||||
@1000200
|
||||
-R
|
||||
@800201
|
||||
-AW
|
||||
@29
|
||||
SystemC.testbench.aw_valid
|
||||
SystemC.testbench.aw_ready
|
||||
@23
|
||||
SystemC.testbench.aw_addr[31:0]
|
||||
@29
|
||||
SystemC.testbench.aw_burst[1:0]
|
||||
@23
|
||||
SystemC.testbench.aw_cache[3:0]
|
||||
SystemC.testbench.aw_id[3:0]
|
||||
SystemC.testbench.aw_len[7:0]
|
||||
@29
|
||||
SystemC.testbench.aw_lock[1:0]
|
||||
SystemC.testbench.aw_prot[2:0]
|
||||
@23
|
||||
SystemC.testbench.aw_qos[3:0]
|
||||
SystemC.testbench.aw_region[3:0]
|
||||
@29
|
||||
SystemC.testbench.aw_size[2:0]
|
||||
SystemC.testbench.aw_user
|
||||
@1000201
|
||||
-AW
|
||||
@800200
|
||||
-W
|
||||
@28
|
||||
SystemC.testbench.w_valid
|
||||
SystemC.testbench.w_ready
|
||||
SystemC.testbench.w_last
|
||||
@22
|
||||
SystemC.testbench.w_data[63:0]
|
||||
SystemC.testbench.w_id[3:0]
|
||||
SystemC.testbench.w_strb[7:0]
|
||||
@28
|
||||
SystemC.testbench.w_user
|
||||
@1000200
|
||||
-W
|
||||
@c00200
|
||||
-B
|
||||
@28
|
||||
SystemC.testbench.b_valid
|
||||
SystemC.testbench.b_ready
|
||||
@22
|
||||
SystemC.testbench.b_id[3:0]
|
||||
@28
|
||||
SystemC.testbench.b_resp[1:0]
|
||||
SystemC.testbench.b_user
|
||||
@1401200
|
||||
-B
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
60
etc/irq_wave.sav
Normal file
60
etc/irq_wave.sav
Normal file
@ -0,0 +1,60 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
|
||||
[*] Fri Sep 22 20:16:21 2017
|
||||
[*]
|
||||
[dumpfile] "/home/valid/project/minres2/SystemC-Components-Test/simple_system.vcd"
|
||||
[dumpfile_mtime] "Fri Sep 22 20:15:38 2017"
|
||||
[dumpfile_size] 69714
|
||||
[savefile] "/home/valid/project/minres2/SystemC-Components-Test/etc/irq_wave.sav"
|
||||
[timestart] 4
|
||||
[size] 1920 924
|
||||
[pos] -1 -1
|
||||
*-3.538420 30 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[sst_width] 397
|
||||
[signals_width] 422
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 334
|
||||
@200
|
||||
-System signals
|
||||
@28
|
||||
SystemC.\i_simple_system.s_rst
|
||||
@24
|
||||
SystemC.\i_simple_system.s_clk[63:0]
|
||||
@28
|
||||
SystemC.\i_simple_system.s_core_interrupt
|
||||
SystemC.\i_simple_system.s_global_interrupts_0
|
||||
SystemC.\i_simple_system.s_global_interrupts_1
|
||||
SystemC.\i_simple_system.s_global_interrupts_2
|
||||
SystemC.\i_simple_system.s_global_interrupts_3
|
||||
SystemC.\i_simple_system.s_global_interrupts_4
|
||||
@200
|
||||
-Master
|
||||
@28
|
||||
SystemC.\i_simple_system.i_master.rst_i
|
||||
SystemC.\i_simple_system.i_master.core_interrupt_i
|
||||
@200
|
||||
-PLIC ports
|
||||
@24
|
||||
SystemC.\i_simple_system.i_plic.rst_i
|
||||
SystemC.\i_simple_system.i_plic.clk_i[63:0]
|
||||
@28
|
||||
SystemC.\i_simple_system.i_plic.global_interrupts_i_0
|
||||
SystemC.\i_simple_system.i_plic.global_interrupts_i_1
|
||||
SystemC.\i_simple_system.i_plic.global_interrupts_i_2
|
||||
SystemC.\i_simple_system.i_plic.global_interrupts_i_3
|
||||
SystemC.\i_simple_system.i_plic.global_interrupts_i_4
|
||||
@200
|
||||
-PLIC regs
|
||||
@22
|
||||
SystemC.\i_simple_system.i_plic.regs.enabled[31:0]
|
||||
SystemC.\i_simple_system.i_plic.regs.pending[31:0]
|
||||
@23
|
||||
SystemC.\i_simple_system.i_plic.regs.priority0[31:0]
|
||||
@22
|
||||
SystemC.\i_simple_system.i_plic.regs.priority1[31:0]
|
||||
SystemC.\i_simple_system.i_plic.regs.priority2[31:0]
|
||||
SystemC.\i_simple_system.i_plic.regs.priority3[31:0]
|
||||
SystemC.\i_simple_system.i_plic.regs.threshold[31:0]
|
||||
SystemC.\i_simple_system.i_plic.regs.claim_complete[31:0]
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
44
etc/simple_system.launch
Normal file
44
etc/simple_system.launch
Normal file
@ -0,0 +1,44 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="org.eclipse.cdt.launch.applicationLaunchType">
|
||||
<booleanAttribute key="de.toem.impulse.launchactivateLaunch" value="false"/>
|
||||
<booleanAttribute key="de.toem.impulse.launchactivateTermination" value="false"/>
|
||||
<intAttribute key="de.toem.impulse.launchdelayLaunch" value="0"/>
|
||||
<intAttribute key="de.toem.impulse.launchlaunch" value="2"/>
|
||||
<intAttribute key="de.toem.impulse.launchmode" value="3"/>
|
||||
<stringAttribute key="de.toem.impulse.launchport" value=""/>
|
||||
<booleanAttribute key="de.toem.impulse.launchrestart" value="true"/>
|
||||
<intAttribute key="de.toem.impulse.launchterminate" value="1"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB" value="true"/>
|
||||
<listAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB_LIST"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="gdb"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=".gdbinit"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
|
||||
<listAttribute key="org.eclipse.cdt.dsf.gdb.SOLIB_PATH"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.internal.ui.launching.LocalApplicationCDebuggerTab.DEFAULTS_SET" value="true"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="sc_main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_ARGUMENTS" value="-d"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/Debug/bin/simple_system"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="sc-components-test"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="cdt.managedbuild.config.gnu.macosx.exe.debug.133691581"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/sc-components-test"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<mapAttribute key="org.eclipse.debug.core.environmentVariables">
|
||||
<mapEntry key="SC_SIGNAL_WRITE_CHECK" value="DISABLE"/>
|
||||
</mapAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
8
examples/CMakeLists.txt
Normal file
8
examples/CMakeLists.txt
Normal file
@ -0,0 +1,8 @@
|
||||
cmake_minimum_required(VERSION 3.12)
|
||||
|
||||
if(SCV_FOUND)
|
||||
add_subdirectory(transaction_recording)
|
||||
endif()
|
||||
|
||||
add_subdirectory(simple_system)
|
||||
add_subdirectory(ahb_bfm)
|
10
examples/ahb_bfm/CMakeLists.txt
Normal file
10
examples/ahb_bfm/CMakeLists.txt
Normal file
@ -0,0 +1,10 @@
|
||||
cmake_minimum_required(VERSION 3.3)
|
||||
# Add executable called "transaction_recording" that is built from the source files
|
||||
# "scv_tr_recording_example.cpp". The extensions are automatically found.
|
||||
add_executable (ahb_bfm
|
||||
sc_main.cpp
|
||||
)
|
||||
# Link the executable to the sc_components library. Since the sc_components library has
|
||||
# public include directories we will use those link directories when building
|
||||
# transaction_recording
|
||||
target_link_libraries (ahb_bfm LINK_PUBLIC scc)
|
@ -1,43 +1,42 @@
|
||||
#include <ahb/pin/initiator.h>
|
||||
#include <ahb/pin/target.h>
|
||||
#include <cci_utils/broker.h>
|
||||
#include <fstream>
|
||||
#include <ahb/bfm/initiator.h>
|
||||
#include <ahb/bfm/target.h>
|
||||
#include <tlm/scc/initiator_mixin.h>
|
||||
#include <tlm/scc/target_mixin.h>
|
||||
#include <scc/configurable_tracer.h>
|
||||
#include <scc/configurer.h>
|
||||
#include <scc/report.h>
|
||||
#include <scc/traceable.h>
|
||||
#include <scc/tracer.h>
|
||||
#include <tlm/scc/initiator_mixin.h>
|
||||
#include <tlm/scc/target_mixin.h>
|
||||
#include <scc/traceable.h>
|
||||
#include <cci_utils/broker.h>
|
||||
#include <fstream>
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace scc;
|
||||
|
||||
class testbench : public sc_module, public scc::traceable {
|
||||
class testbench: public sc_module, public scc::traceable {
|
||||
public:
|
||||
enum { WIDTH = 64 };
|
||||
enum { WIDTH=64};
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<WIDTH>> isck{"isck"};
|
||||
ahb::pin::initiator<WIDTH> intor{"intor"};
|
||||
sc_core::sc_clock HCLK{"HCLK", 10_ns};
|
||||
sc_core::sc_signal<bool> HRESETn{"HRESETn"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<32>> HADDR{"HADDR"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<3>> HBURST{"HBURST"};
|
||||
sc_core::sc_signal<bool> HMASTLOCK{"HMASTLOCK"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<4>> HPROT{"HPROT"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<3>> HSIZE{"HSIZE"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<2>> HTRANS{"HTRANS"};
|
||||
ahb::bfm::initiator<WIDTH> intor{"intor"};
|
||||
sc_core::sc_clock HCLK{"HCLK", 10_ns};
|
||||
sc_core::sc_signal<bool> HRESETn{"HRESETn"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<32>> HADDR{"HADDR"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<3>> HBURST{"HBURST"};
|
||||
sc_core::sc_signal<bool> HMASTLOCK{"HMASTLOCK"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<4>> HPROT{"HPROT"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<3>> HSIZE{"HSIZE"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<2>> HTRANS{"HTRANS"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<WIDTH>> HWDATA{"HWDATA"};
|
||||
sc_core::sc_signal<bool> HWRITE{"HWRITE"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<WIDTH>> HRDATA{"HRDATA"};
|
||||
sc_core::sc_signal<bool> HREADY{"HREADY"};
|
||||
sc_core::sc_signal<bool> HRESP{"HRESP"};
|
||||
sc_core::sc_signal<bool> HSEL{"HSEL"};
|
||||
sc_core::sc_signal<bool> HWRITE{"HWRITE"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<WIDTH>> HRDATA{"HRDATA"};
|
||||
sc_core::sc_signal<bool> HREADY{"HREADY"};
|
||||
sc_core::sc_signal<bool> HRESP{"HRESP"};
|
||||
sc_core::sc_signal<bool> HSEL{"HSEL"};
|
||||
|
||||
ahb::pin::target<WIDTH> target{"target"};
|
||||
ahb::bfm::target<WIDTH> target{"target"};
|
||||
tlm::scc::target_mixin<tlm::tlm_target_socket<WIDTH>> tsck{"tsck"};
|
||||
|
||||
testbench(sc_module_name nm)
|
||||
: sc_module(nm) {
|
||||
testbench(sc_module_name nm):sc_module(nm){
|
||||
SC_HAS_PROCESS(testbench);
|
||||
isck(intor.tsckt);
|
||||
intor.HCLK_i(HCLK);
|
||||
@ -69,28 +68,27 @@ public:
|
||||
target.HRESP_o(HRESP);
|
||||
target.isckt(tsck);
|
||||
SC_THREAD(run);
|
||||
tsck.register_b_transport([this](tlm::tlm_generic_payload& gp, sc_time& delay) {
|
||||
tsck.register_b_transport([this](tlm::tlm_generic_payload& gp, sc_time& delay){
|
||||
gp.set_response_status(tlm::TLM_OK_RESPONSE);
|
||||
if(gp.is_write()) {
|
||||
SCCINFO(SCMOD) << "Received write access to addr 0x" << std::hex << gp.get_address();
|
||||
} else {
|
||||
if(gp.is_write()){
|
||||
SCCINFO(SCMOD)<<"Received write access to addr 0x"<<std::hex<<gp.get_address();
|
||||
} else{
|
||||
memset(gp.get_data_ptr(), 0x55, gp.get_data_length());
|
||||
SCCINFO(SCMOD) << "Received read access from addr 0x" << std::hex << gp.get_address();
|
||||
SCCINFO(SCMOD)<<"Received read access from addr 0x"<<std::hex<<gp.get_address();
|
||||
}
|
||||
});
|
||||
}
|
||||
|
||||
void run() {
|
||||
void run(){
|
||||
HRESETn.write(false);
|
||||
for(size_t i = 0; i < 10; ++i)
|
||||
wait(HCLK.posedge_event());
|
||||
for(size_t i=0; i<10; ++i) wait(HCLK.posedge_event());
|
||||
HRESETn.write(true);
|
||||
wait(HCLK.posedge_event());
|
||||
HSEL.write(true);
|
||||
tlm::tlm_generic_payload gp;
|
||||
uint8_t data[8];
|
||||
data[0] = 2;
|
||||
data[1] = 4;
|
||||
data[0]=2;
|
||||
data[1]=4;
|
||||
gp.set_address(0x1000);
|
||||
gp.set_data_length(8);
|
||||
gp.set_data_ptr(data);
|
||||
@ -103,16 +101,16 @@ public:
|
||||
gp.set_data_ptr(data);
|
||||
gp.set_streaming_width(8);
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
delay = SC_ZERO_TIME;
|
||||
delay=SC_ZERO_TIME;
|
||||
isck->b_transport(gp, delay);
|
||||
for(size_t i = 0; i < 10; ++i)
|
||||
wait(HCLK.posedge_event());
|
||||
for(size_t i=0; i<10; ++i) wait(HCLK.posedge_event());
|
||||
sc_stop();
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
int sc_main(int argc, char* argv[]) {
|
||||
sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING);
|
||||
int sc_main (int argc , char *argv[]){
|
||||
sc_core::sc_report_handler::set_actions( "/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING );
|
||||
sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// configure logging
|
||||
@ -130,8 +128,7 @@ int sc_main(int argc, char* argv[]) {
|
||||
trace.add_control();
|
||||
{
|
||||
std::ofstream of{"ahb_test.default.json"};
|
||||
if(of.is_open())
|
||||
cfg.dump_configuration(of);
|
||||
if (of.is_open()) cfg.dump_configuration(of);
|
||||
}
|
||||
cfg.configure();
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
@ -139,10 +136,10 @@ int sc_main(int argc, char* argv[]) {
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
try {
|
||||
sc_core::sc_start(1_us);
|
||||
if(!sc_core::sc_end_of_simulation_invoked())
|
||||
sc_core::sc_stop();
|
||||
} catch(sc_core::sc_report& rep) {
|
||||
if (!sc_core::sc_end_of_simulation_invoked()) sc_core::sc_stop();
|
||||
} catch (sc_core::sc_report &rep) {
|
||||
sc_core::sc_report_handler::get_handler()(rep, sc_core::SC_DISPLAY | sc_core::SC_STOP);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
14
examples/simple_system/CMakeLists.txt
Normal file
14
examples/simple_system/CMakeLists.txt
Normal file
@ -0,0 +1,14 @@
|
||||
cmake_minimum_required(VERSION 3.12)
|
||||
add_executable (simple_system
|
||||
plic.cpp
|
||||
uart.cpp
|
||||
spi.cpp
|
||||
gpio.cpp
|
||||
test_initiator.cpp
|
||||
simple_system.cpp
|
||||
sc_main.cpp
|
||||
)
|
||||
target_link_libraries (simple_system LINK_PUBLIC scc)
|
||||
target_link_libraries (simple_system LINK_PUBLIC ${Boost_LIBRARIES} )
|
||||
|
||||
add_test(NAME simple_system_test COMMAND simple_system)
|
27
examples/simple_system/gen/e300_plat_t.h
Normal file
27
examples/simple_system/gen/e300_plat_t.h
Normal file
@ -0,0 +1,27 @@
|
||||
/*******************************************************************************
|
||||
* Copyright 2017 eyck@minres.com
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
* use this file except in compliance with the License. You may obtain a copy
|
||||
* of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations under
|
||||
* the License.
|
||||
******************************************************************************/
|
||||
#ifndef _E300_PLAT_MAP_H_
|
||||
#define _E300_PLAT_MAP_H_
|
||||
// need double braces, see
|
||||
// https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
|
||||
const std::array<scc::target_name_map_entry<32>, 4> e300_plat_map = {{
|
||||
{"plic", 0x0c000000, 0x200008},
|
||||
{"gpio", 0x10012000, 0x1000},
|
||||
{"uart", 0x10013000, 0x1000},
|
||||
{"spi", 0x10014000, 0x1000},
|
||||
}};
|
||||
|
||||
#endif /* _E300_PLAT_MAP_H_ */
|
152
examples/simple_system/gen/gpio_regs.h
Normal file
152
examples/simple_system/gen/gpio_regs.h
Normal file
@ -0,0 +1,152 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Created on: Wed Sep 20 11:47:24 CEST 2017
|
||||
// * gpio_regs.h Author: <RDL Generator>
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _GPIO_REGS_H_
|
||||
#define _GPIO_REGS_H_
|
||||
|
||||
#include <util/bit_field.h>
|
||||
#include "scc/register.h"
|
||||
#include "scc/tlm_target.h"
|
||||
#include "scc/utilities.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class gpio_regs : public sc_core::sc_module, public scc::resetable {
|
||||
public:
|
||||
// storage declarations
|
||||
uint32_t r_value;
|
||||
|
||||
uint32_t r_input_en;
|
||||
|
||||
uint32_t r_output_en;
|
||||
|
||||
uint32_t r_port;
|
||||
|
||||
uint32_t r_pue;
|
||||
|
||||
uint32_t r_ds;
|
||||
|
||||
uint32_t r_rise_ie;
|
||||
|
||||
uint32_t r_rise_ip;
|
||||
|
||||
uint32_t r_fall_ie;
|
||||
|
||||
uint32_t r_fall_ip;
|
||||
|
||||
uint32_t r_high_ie;
|
||||
|
||||
uint32_t r_high_ip;
|
||||
|
||||
uint32_t r_low_ie;
|
||||
|
||||
uint32_t r_low_ip;
|
||||
|
||||
uint32_t r_iof_en;
|
||||
|
||||
uint32_t r_iof_sel;
|
||||
|
||||
uint32_t r_out_xor;
|
||||
|
||||
// register declarations
|
||||
scc::sc_register<uint32_t> value;
|
||||
scc::sc_register<uint32_t> input_en;
|
||||
scc::sc_register<uint32_t> output_en;
|
||||
scc::sc_register<uint32_t> port;
|
||||
scc::sc_register<uint32_t> pue;
|
||||
scc::sc_register<uint32_t> ds;
|
||||
scc::sc_register<uint32_t> rise_ie;
|
||||
scc::sc_register<uint32_t> rise_ip;
|
||||
scc::sc_register<uint32_t> fall_ie;
|
||||
scc::sc_register<uint32_t> fall_ip;
|
||||
scc::sc_register<uint32_t> high_ie;
|
||||
scc::sc_register<uint32_t> high_ip;
|
||||
scc::sc_register<uint32_t> low_ie;
|
||||
scc::sc_register<uint32_t> low_ip;
|
||||
scc::sc_register<uint32_t> iof_en;
|
||||
scc::sc_register<uint32_t> iof_sel;
|
||||
scc::sc_register<uint32_t> out_xor;
|
||||
|
||||
public:
|
||||
gpio_regs(sc_core::sc_module_name nm);
|
||||
|
||||
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
|
||||
};
|
||||
}
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// member functions
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
inline sysc::gpio_regs::gpio_regs(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, NAMED(value, r_value, 0, *this)
|
||||
, NAMED(input_en, r_input_en, 0, *this)
|
||||
, NAMED(output_en, r_output_en, 0, *this)
|
||||
, NAMED(port, r_port, 0, *this)
|
||||
, NAMED(pue, r_pue, 0, *this)
|
||||
, NAMED(ds, r_ds, 0, *this)
|
||||
, NAMED(rise_ie, r_rise_ie, 0, *this)
|
||||
, NAMED(rise_ip, r_rise_ip, 0, *this)
|
||||
, NAMED(fall_ie, r_fall_ie, 0, *this)
|
||||
, NAMED(fall_ip, r_fall_ip, 0, *this)
|
||||
, NAMED(high_ie, r_high_ie, 0, *this)
|
||||
, NAMED(high_ip, r_high_ip, 0, *this)
|
||||
, NAMED(low_ie, r_low_ie, 0, *this)
|
||||
, NAMED(low_ip, r_low_ip, 0, *this)
|
||||
, NAMED(iof_en, r_iof_en, 0, *this)
|
||||
, NAMED(iof_sel, r_iof_sel, 0, *this)
|
||||
, NAMED(out_xor, r_out_xor, 0, *this) {}
|
||||
|
||||
template <unsigned BUSWIDTH> inline void sysc::gpio_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
|
||||
target.addResource(value, 0x0UL);
|
||||
target.addResource(input_en, 0x4UL);
|
||||
target.addResource(output_en, 0x8UL);
|
||||
target.addResource(port, 0xcUL);
|
||||
target.addResource(pue, 0x10UL);
|
||||
target.addResource(ds, 0x14UL);
|
||||
target.addResource(rise_ie, 0x18UL);
|
||||
target.addResource(rise_ip, 0x1cUL);
|
||||
target.addResource(fall_ie, 0x20UL);
|
||||
target.addResource(fall_ip, 0x24UL);
|
||||
target.addResource(high_ie, 0x28UL);
|
||||
target.addResource(high_ip, 0x2cUL);
|
||||
target.addResource(low_ie, 0x30UL);
|
||||
target.addResource(low_ip, 0x34UL);
|
||||
target.addResource(iof_en, 0x38UL);
|
||||
target.addResource(iof_sel, 0x3cUL);
|
||||
target.addResource(out_xor, 0x40UL);
|
||||
}
|
||||
|
||||
#endif // _GPIO_REGS_H_
|
96
examples/simple_system/gen/plic_regs.h
Normal file
96
examples/simple_system/gen/plic_regs.h
Normal file
@ -0,0 +1,96 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Created on: Wed Sep 20 22:30:45 CEST 2017
|
||||
// * plic_regs.h Author: <RDL Generator>
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _PLIC_REGS_H_
|
||||
#define _PLIC_REGS_H_
|
||||
|
||||
#include <util/bit_field.h>
|
||||
#include "scc/register.h"
|
||||
#include "scc/tlm_target.h"
|
||||
#include "scc/utilities.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class plic_regs : public sc_core::sc_module, public scc::resetable {
|
||||
public:
|
||||
// storage declarations
|
||||
BEGIN_BF_DECL(priority_t, uint32_t);
|
||||
BF_FIELD(priority, 0, 3);
|
||||
END_BF_DECL();
|
||||
std::array<priority_t, 255> r_priority;
|
||||
|
||||
uint32_t r_pending;
|
||||
|
||||
uint32_t r_enabled;
|
||||
|
||||
BEGIN_BF_DECL(threshold_t, uint32_t);
|
||||
BF_FIELD(threshold, 0, 3);
|
||||
END_BF_DECL() r_threshold;
|
||||
|
||||
uint32_t r_claim_complete;
|
||||
|
||||
// register declarations
|
||||
scc::sc_register_indexed<priority_t, 255> priority;
|
||||
scc::sc_register<uint32_t> pending;
|
||||
scc::sc_register<uint32_t> enabled;
|
||||
scc::sc_register<threshold_t> threshold;
|
||||
scc::sc_register<uint32_t> claim_complete;
|
||||
|
||||
plic_regs(sc_core::sc_module_name nm);
|
||||
|
||||
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
|
||||
};
|
||||
}
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// member functions
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
inline sysc::plic_regs::plic_regs(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, NAMED(priority, r_priority, 0, *this)
|
||||
, NAMED(pending, r_pending, 0, *this)
|
||||
, NAMED(enabled, r_enabled, 0, *this)
|
||||
, NAMED(threshold, r_threshold, 0, *this)
|
||||
, NAMED(claim_complete, r_claim_complete, 0, *this) {}
|
||||
|
||||
template <unsigned BUSWIDTH> inline void sysc::plic_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
|
||||
target.addResource(priority, 0x4UL);
|
||||
target.addResource(pending, 0x1000UL);
|
||||
target.addResource(enabled, 0x2000UL);
|
||||
target.addResource(threshold, 0x00200000UL);
|
||||
target.addResource(claim_complete, 0x00200004UL);
|
||||
}
|
||||
|
||||
#endif // _PLIC_REGS_H_
|
192
examples/simple_system/gen/spi_regs.h
Normal file
192
examples/simple_system/gen/spi_regs.h
Normal file
@ -0,0 +1,192 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Created on: Wed Sep 20 22:30:45 CEST 2017
|
||||
// * spi_regs.h Author: <RDL Generator>
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _SPI_REGS_H_
|
||||
#define _SPI_REGS_H_
|
||||
|
||||
#include <util/bit_field.h>
|
||||
#include "scc/register.h"
|
||||
#include "scc/tlm_target.h"
|
||||
#include "scc/utilities.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class spi_regs : public sc_core::sc_module, public scc::resetable {
|
||||
protected:
|
||||
// storage declarations
|
||||
BEGIN_BF_DECL(sckdiv_t, uint32_t);
|
||||
BF_FIELD(div, 0, 12);
|
||||
END_BF_DECL() r_sckdiv;
|
||||
|
||||
BEGIN_BF_DECL(sckmode_t, uint32_t);
|
||||
BF_FIELD(pha, 0, 1);
|
||||
BF_FIELD(pol, 1, 1);
|
||||
END_BF_DECL() r_sckmode;
|
||||
|
||||
uint32_t r_csid;
|
||||
|
||||
uint32_t r_csdef;
|
||||
|
||||
BEGIN_BF_DECL(csmode_t, uint32_t);
|
||||
BF_FIELD(mode, 0, 2);
|
||||
END_BF_DECL() r_csmode;
|
||||
|
||||
BEGIN_BF_DECL(delay0_t, uint32_t);
|
||||
BF_FIELD(cssck, 0, 8);
|
||||
BF_FIELD(sckcs, 16, 8);
|
||||
END_BF_DECL() r_delay0;
|
||||
|
||||
BEGIN_BF_DECL(delay1_t, uint32_t);
|
||||
BF_FIELD(intercs, 0, 16);
|
||||
BF_FIELD(interxfr, 16, 8);
|
||||
END_BF_DECL() r_delay1;
|
||||
|
||||
BEGIN_BF_DECL(fmt_t, uint32_t);
|
||||
BF_FIELD(proto, 0, 2);
|
||||
BF_FIELD(endian, 2, 1);
|
||||
BF_FIELD(dir, 3, 1);
|
||||
BF_FIELD(len, 16, 4);
|
||||
END_BF_DECL() r_fmt;
|
||||
|
||||
BEGIN_BF_DECL(txdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(full, 31, 1);
|
||||
END_BF_DECL() r_txdata;
|
||||
|
||||
BEGIN_BF_DECL(rxdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(empty, 31, 1);
|
||||
END_BF_DECL() r_rxdata;
|
||||
|
||||
BEGIN_BF_DECL(txmark_t, uint32_t);
|
||||
BF_FIELD(txmark, 0, 3);
|
||||
END_BF_DECL() r_txmark;
|
||||
|
||||
BEGIN_BF_DECL(rxmark_t, uint32_t);
|
||||
BF_FIELD(rxmark, 0, 3);
|
||||
END_BF_DECL() r_rxmark;
|
||||
|
||||
BEGIN_BF_DECL(fctrl_t, uint32_t);
|
||||
BF_FIELD(en, 0, 1);
|
||||
END_BF_DECL() r_fctrl;
|
||||
|
||||
BEGIN_BF_DECL(ffmt_t, uint32_t);
|
||||
BF_FIELD(cmd_en, 0, 1);
|
||||
BF_FIELD(addr_len, 1, 2);
|
||||
BF_FIELD(pad_cnt, 3, 4);
|
||||
BF_FIELD(cmd_proto, 7, 2);
|
||||
BF_FIELD(addr_proto, 9, 2);
|
||||
BF_FIELD(data_proto, 11, 2);
|
||||
BF_FIELD(cmd_code, 16, 8);
|
||||
BF_FIELD(pad_code, 24, 8);
|
||||
END_BF_DECL() r_ffmt;
|
||||
|
||||
BEGIN_BF_DECL(ie_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL() r_ie;
|
||||
|
||||
BEGIN_BF_DECL(ip_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL() r_ip;
|
||||
|
||||
// register declarations
|
||||
scc::sc_register<sckdiv_t> sckdiv;
|
||||
scc::sc_register<sckmode_t> sckmode;
|
||||
scc::sc_register<uint32_t> csid;
|
||||
scc::sc_register<uint32_t> csdef;
|
||||
scc::sc_register<csmode_t> csmode;
|
||||
scc::sc_register<delay0_t> delay0;
|
||||
scc::sc_register<delay1_t> delay1;
|
||||
scc::sc_register<fmt_t> fmt;
|
||||
scc::sc_register<txdata_t> txdata;
|
||||
scc::sc_register<rxdata_t> rxdata;
|
||||
scc::sc_register<txmark_t> txmark;
|
||||
scc::sc_register<rxmark_t> rxmark;
|
||||
scc::sc_register<fctrl_t> fctrl;
|
||||
scc::sc_register<ffmt_t> ffmt;
|
||||
scc::sc_register<ie_t> ie;
|
||||
scc::sc_register<ip_t> ip;
|
||||
|
||||
public:
|
||||
spi_regs(sc_core::sc_module_name nm);
|
||||
|
||||
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
|
||||
};
|
||||
}
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// member functions
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
inline sysc::spi_regs::spi_regs(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, NAMED(sckdiv, r_sckdiv, 0, *this)
|
||||
, NAMED(sckmode, r_sckmode, 0, *this)
|
||||
, NAMED(csid, r_csid, 0, *this)
|
||||
, NAMED(csdef, r_csdef, 0, *this)
|
||||
, NAMED(csmode, r_csmode, 0, *this)
|
||||
, NAMED(delay0, r_delay0, 0, *this)
|
||||
, NAMED(delay1, r_delay1, 0, *this)
|
||||
, NAMED(fmt, r_fmt, 0, *this)
|
||||
, NAMED(txdata, r_txdata, 0, *this)
|
||||
, NAMED(rxdata, r_rxdata, 0, *this)
|
||||
, NAMED(txmark, r_txmark, 0, *this)
|
||||
, NAMED(rxmark, r_rxmark, 0, *this)
|
||||
, NAMED(fctrl, r_fctrl, 0, *this)
|
||||
, NAMED(ffmt, r_ffmt, 0, *this)
|
||||
, NAMED(ie, r_ie, 0, *this)
|
||||
, NAMED(ip, r_ip, 0, *this) {}
|
||||
|
||||
template <unsigned BUSWIDTH> inline void sysc::spi_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
|
||||
target.addResource(sckdiv, 0x0UL);
|
||||
target.addResource(sckmode, 0x4UL);
|
||||
target.addResource(csid, 0x10UL);
|
||||
target.addResource(csdef, 0x14UL);
|
||||
target.addResource(csmode, 0x18UL);
|
||||
target.addResource(delay0, 0x28UL);
|
||||
target.addResource(delay1, 0x2cUL);
|
||||
target.addResource(fmt, 0x40UL);
|
||||
target.addResource(txdata, 0x48UL);
|
||||
target.addResource(rxdata, 0x4cUL);
|
||||
target.addResource(txmark, 0x50UL);
|
||||
target.addResource(rxmark, 0x54UL);
|
||||
target.addResource(fctrl, 0x60UL);
|
||||
target.addResource(ffmt, 0x64UL);
|
||||
target.addResource(ie, 0x70UL);
|
||||
target.addResource(ip, 0x74UL);
|
||||
}
|
||||
|
||||
#endif // _SPI_REGS_H_
|
125
examples/simple_system/gen/uart_regs.h
Normal file
125
examples/simple_system/gen/uart_regs.h
Normal file
@ -0,0 +1,125 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Created on: Wed Sep 20 22:30:45 CEST 2017
|
||||
// * uart_regs.h Author: <RDL Generator>
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _UART_REGS_H_
|
||||
#define _UART_REGS_H_
|
||||
|
||||
#include <util/bit_field.h>
|
||||
#include "scc/register.h"
|
||||
#include "scc/tlm_target.h"
|
||||
#include "scc/utilities.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class uart_regs : public sc_core::sc_module, public scc::resetable {
|
||||
protected:
|
||||
// storage declarations
|
||||
BEGIN_BF_DECL(txdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(full, 31, 1);
|
||||
END_BF_DECL() r_txdata;
|
||||
|
||||
BEGIN_BF_DECL(rxdata_t, uint32_t);
|
||||
BF_FIELD(data, 0, 8);
|
||||
BF_FIELD(empty, 31, 1);
|
||||
END_BF_DECL() r_rxdata;
|
||||
|
||||
BEGIN_BF_DECL(txctrl_t, uint32_t);
|
||||
BF_FIELD(txen, 0, 1);
|
||||
BF_FIELD(nstop, 1, 1);
|
||||
BF_FIELD(reserved, 2, 14);
|
||||
BF_FIELD(txcnt, 16, 3);
|
||||
END_BF_DECL() r_txctrl;
|
||||
|
||||
BEGIN_BF_DECL(rxctrl_t, uint32_t);
|
||||
BF_FIELD(rxen, 0, 1);
|
||||
BF_FIELD(reserved, 1, 15);
|
||||
BF_FIELD(rxcnt, 16, 3);
|
||||
END_BF_DECL() r_rxctrl;
|
||||
|
||||
BEGIN_BF_DECL(ie_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL() r_ie;
|
||||
|
||||
BEGIN_BF_DECL(ip_t, uint32_t);
|
||||
BF_FIELD(txwm, 0, 1);
|
||||
BF_FIELD(rxwm, 1, 1);
|
||||
END_BF_DECL() r_ip;
|
||||
|
||||
BEGIN_BF_DECL(div_t, uint32_t);
|
||||
BF_FIELD(div, 0, 16);
|
||||
END_BF_DECL() r_div;
|
||||
|
||||
// register declarations
|
||||
scc::sc_register<txdata_t> txdata;
|
||||
scc::sc_register<rxdata_t> rxdata;
|
||||
scc::sc_register<txctrl_t> txctrl;
|
||||
scc::sc_register<rxctrl_t> rxctrl;
|
||||
scc::sc_register<ie_t> ie;
|
||||
scc::sc_register<ip_t> ip;
|
||||
scc::sc_register<div_t> div;
|
||||
|
||||
public:
|
||||
uart_regs(sc_core::sc_module_name nm);
|
||||
|
||||
template <unsigned BUSWIDTH = 32> void registerResources(scc::tlm_target<BUSWIDTH> &target);
|
||||
};
|
||||
}
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
// member functions
|
||||
//////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
inline sysc::uart_regs::uart_regs(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, NAMED(txdata, r_txdata, 0, *this)
|
||||
, NAMED(rxdata, r_rxdata, 0, *this)
|
||||
, NAMED(txctrl, r_txctrl, 0, *this)
|
||||
, NAMED(rxctrl, r_rxctrl, 0, *this)
|
||||
, NAMED(ie, r_ie, 0, *this)
|
||||
, NAMED(ip, r_ip, 0, *this)
|
||||
, NAMED(div, r_div, 0, *this) {}
|
||||
|
||||
template <unsigned BUSWIDTH> inline void sysc::uart_regs::registerResources(scc::tlm_target<BUSWIDTH> &target) {
|
||||
target.addResource(txdata, 0x0UL);
|
||||
target.addResource(rxdata, 0x4UL);
|
||||
target.addResource(txctrl, 0x8UL);
|
||||
target.addResource(rxctrl, 0xcUL);
|
||||
target.addResource(ie, 0x10UL);
|
||||
target.addResource(ip, 0x14UL);
|
||||
target.addResource(div, 0x18UL);
|
||||
}
|
||||
|
||||
#endif // _UART_REGS_H_
|
220
examples/simple_system/gpio.cpp
Normal file
220
examples/simple_system/gpio.cpp
Normal file
@ -0,0 +1,220 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Contributors:
|
||||
// eyck@minres.com - initial implementation
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "gpio.h"
|
||||
#include "scc/report.h"
|
||||
#include "scc/utilities.h"
|
||||
#include "gen/gpio_regs.h"
|
||||
#include <limits>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
gpio::gpio(sc_module_name nm)
|
||||
: sc_module(nm)
|
||||
, tlm_target<>(clk)
|
||||
, NAMED(clk_i)
|
||||
, NAMED(rst_i)
|
||||
, NAMED(pins_o, 32)
|
||||
, NAMED(pins_i, 32)
|
||||
, NAMED(iof0_o, 32)
|
||||
, NAMED(iof1_o, 32)
|
||||
, NAMED(iof0_i, 32)
|
||||
, NAMED(iof1_i, 32)
|
||||
, NAMEDD(regs, gpio_regs)
|
||||
{
|
||||
regs->registerResources(*this);
|
||||
SC_METHOD(clock_cb);
|
||||
sensitive << clk_i;
|
||||
SC_METHOD(reset_cb);
|
||||
sensitive << rst_i;
|
||||
dont_initialize();
|
||||
auto pins_i_cb =[this](unsigned int tag, tlm::scc::tlm_signal_gp<>& gp,
|
||||
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
|
||||
this->pin_input(tag, gp, delay);
|
||||
return tlm::TLM_COMPLETED;
|
||||
};
|
||||
auto i=0U;
|
||||
for(auto& s:pins_i){
|
||||
s.register_nb_transport(pins_i_cb, i);
|
||||
++i;
|
||||
}
|
||||
auto iof0_i_cb =[this](unsigned int tag, tlm::scc::tlm_signal_gp<>& gp,
|
||||
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
|
||||
last_iof0[tag]=gp.get_value();
|
||||
this->iof_input(tag, 0, gp, delay);
|
||||
return tlm::TLM_COMPLETED;
|
||||
};
|
||||
i=0;
|
||||
for(auto& s:iof0_i){
|
||||
s.register_nb_transport(iof0_i_cb, i);
|
||||
++i;
|
||||
}
|
||||
auto iof1_i_cb =[this](unsigned int tag, tlm::scc::tlm_signal_gp<>& gp,
|
||||
tlm::tlm_phase& phase, sc_time& delay)->tlm::tlm_sync_enum{
|
||||
last_iof1[tag]=gp.get_value();
|
||||
this->iof_input(tag, 1, gp, delay);
|
||||
return tlm::TLM_COMPLETED;
|
||||
};
|
||||
i=0;
|
||||
for(auto& s:iof1_i){
|
||||
s.register_nb_transport(iof1_i_cb, i);
|
||||
++i;
|
||||
}
|
||||
auto update_pins_cb = [this](scc::sc_register<uint32_t> ®, uint32_t data, sc_time d) -> bool {
|
||||
if (!this->regs->in_reset()) {
|
||||
auto changed_bits = (reg.get()^data);
|
||||
reg.put(data);
|
||||
update_pins(changed_bits);
|
||||
}
|
||||
return true;
|
||||
};
|
||||
regs->port.set_write_cb(update_pins_cb);
|
||||
regs->output_en.set_write_cb(update_pins_cb);
|
||||
regs->out_xor.set_write_cb(update_pins_cb);
|
||||
regs->iof_en.set_write_cb(update_pins_cb);
|
||||
regs->iof_sel.set_write_cb(update_pins_cb);
|
||||
}
|
||||
|
||||
gpio::~gpio() = default;
|
||||
|
||||
void gpio::reset_cb() {
|
||||
if (rst_i.read()){
|
||||
regs->reset_start();
|
||||
} else {
|
||||
regs->reset_stop();
|
||||
}
|
||||
update_pins(std::numeric_limits<uint32_t>::max());
|
||||
}
|
||||
|
||||
void gpio::clock_cb() {
|
||||
this->clk = clk_i.read();
|
||||
}
|
||||
|
||||
tlm::tlm_phase gpio::write_output(tlm::scc::tlm_signal_gp<bool>& gp, size_t i, bool val) {
|
||||
sc_time delay{SC_ZERO_TIME};
|
||||
tlm::tlm_phase phase{ tlm::BEGIN_REQ };
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_response_status(tlm::TLM_OK_RESPONSE);
|
||||
gp.set_value(val);
|
||||
pins_o.at(i)->nb_transport_fw(gp, phase, delay);
|
||||
return phase;
|
||||
}
|
||||
|
||||
void gpio::update_pins(uint32_t changed_bits) {
|
||||
sc_inout_rv<32>::data_type out_val;
|
||||
tlm::scc::tlm_signal_gp<bool> gp;
|
||||
bool val{false};
|
||||
for(size_t i=0, mask = 1; i<32; ++i, mask<<=1){
|
||||
if(changed_bits&mask){
|
||||
if(((regs->r_iof_en&mask)!=0) && (iof0_i[i].size()==0 || iof1_i[i].size()==0)){
|
||||
if((regs->r_iof_sel&mask)==0 && iof0_i[i].size()>0){
|
||||
val=last_iof0[i]?sc_dt::Log_1:sc_dt::Log_0;
|
||||
} else if((regs->r_iof_sel&mask)==1 && iof1_i[i].size()>0)
|
||||
val=last_iof1[i]?sc_dt::Log_1:sc_dt::Log_0;
|
||||
} else {
|
||||
if((regs->r_output_en&mask) && (regs->r_port&mask))
|
||||
val=true;
|
||||
else
|
||||
val=false;
|
||||
if(regs->r_out_xor&mask)
|
||||
val=~val;
|
||||
}
|
||||
tlm::tlm_phase phase = write_output(gp, i, val);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void gpio::pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<bool>& gp, sc_time& delay) {
|
||||
if(delay>SC_ZERO_TIME){
|
||||
wait(delay);
|
||||
delay=SC_ZERO_TIME;
|
||||
}
|
||||
auto mask = 1u<<tag;
|
||||
if((regs->r_output_en&mask)==0){
|
||||
if(gp.get_value())
|
||||
regs->r_value|=mask;
|
||||
else
|
||||
regs->r_value&=~mask;
|
||||
forward_pin_input(tag, gp);
|
||||
}
|
||||
}
|
||||
|
||||
void gpio::forward_pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<bool>& gp) {
|
||||
const auto mask = 1U<<tag;
|
||||
if(regs->iof_en&mask){
|
||||
auto& socket = regs->iof_sel&mask?iof1_o[tag]:iof0_o[tag];
|
||||
tlm::scc::tlm_signal_gp<> new_gp;
|
||||
for(size_t i=0; i<socket.size(); ++i){
|
||||
sc_time delay{SC_ZERO_TIME};
|
||||
tlm::tlm_phase phase{tlm::BEGIN_REQ};
|
||||
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
new_gp.set_response_status(tlm::TLM_OK_RESPONSE);
|
||||
new_gp.set_value(gp.get_value());
|
||||
new_gp.update_extensions_from(gp);
|
||||
socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void gpio::iof_input(unsigned int tag, unsigned iof_idx, tlm::scc::tlm_signal_gp<>& gp, sc_time& delay) {
|
||||
if(delay>SC_ZERO_TIME){
|
||||
wait(delay);
|
||||
delay=SC_ZERO_TIME;
|
||||
}
|
||||
const auto mask = 1U<<tag;
|
||||
if(regs->r_iof_en&mask){
|
||||
const auto idx = regs->r_iof_sel&mask?1:0;
|
||||
if(iof_idx == idx){
|
||||
auto& socket = pins_o[tag];
|
||||
for(size_t i=0; i<socket.size(); ++i){
|
||||
sc_time delay{SC_ZERO_TIME};
|
||||
tlm::tlm_phase phase{tlm::BEGIN_REQ};
|
||||
tlm::scc::tlm_signal_gp<> new_gp;
|
||||
new_gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
auto val = gp.get_value();
|
||||
new_gp.set_value(val);
|
||||
new_gp.copy_extensions_from(gp);
|
||||
socket->nb_transport_fw(new_gp, phase, delay); // we don't care about phase and sync enum
|
||||
gp.update_extensions_from(new_gp);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
} /* namespace sysc */
|
||||
|
86
examples/simple_system/gpio.h
Normal file
86
examples/simple_system/gpio.h
Normal file
@ -0,0 +1,86 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Contributors:
|
||||
// eyck@minres.com - initial implementation
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _GPIO_H_
|
||||
#define _GPIO_H_
|
||||
|
||||
#include "scc/tlm_target.h"
|
||||
#include "tlm/scc/signal_target_mixin.h"
|
||||
#include "tlm/scc/signal_initiator_mixin.h"
|
||||
#include <tlm/scc/tlm_signal.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class gpio_regs;
|
||||
class WsHandler;
|
||||
|
||||
class gpio : public sc_core::sc_module, public scc::tlm_target<> {
|
||||
public:
|
||||
SC_HAS_PROCESS(gpio);
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i;
|
||||
sc_core::sc_in<bool> rst_i;
|
||||
// sc_core::sc_inout_rv<32> pins_io;
|
||||
|
||||
sc_core::sc_vector<tlm::scc::tlm_signal_bool_out> pins_o;
|
||||
sc_core::sc_vector<tlm::scc::tlm_signal_bool_in> pins_i;
|
||||
|
||||
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> iof0_o;
|
||||
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_out> iof1_o;
|
||||
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> iof0_i;
|
||||
sc_core::sc_vector<tlm::scc::tlm_signal_bool_opt_in> iof1_i;
|
||||
|
||||
gpio(sc_core::sc_module_name nm);
|
||||
virtual ~gpio() override; // need to keep it in source file because of fwd declaration of gpio_regs
|
||||
|
||||
protected:
|
||||
void clock_cb();
|
||||
void reset_cb();
|
||||
void update_pins(uint32_t changed_bits);
|
||||
void pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
|
||||
void forward_pin_input(unsigned int tag, tlm::scc::tlm_signal_gp<>& gp);
|
||||
void iof_input(unsigned int tag, unsigned iof_idx, tlm::scc::tlm_signal_gp<>& gp, sc_core::sc_time& delay);
|
||||
sc_core::sc_time clk;
|
||||
std::array<bool, 32> last_iof0, last_iof1;
|
||||
std::unique_ptr<gpio_regs> regs;
|
||||
std::shared_ptr<sysc::WsHandler> handler;
|
||||
|
||||
private:
|
||||
tlm::tlm_phase write_output(tlm::scc::tlm_signal_gp<>& gp, size_t i, bool val);
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _GPIO_H_ */
|
177
examples/simple_system/plic.cpp
Normal file
177
examples/simple_system/plic.cpp
Normal file
@ -0,0 +1,177 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (C) 2017, MINRES Technologies GmbH
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice,
|
||||
// this list of conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
// this list of conditions and the following disclaimer in the documentation
|
||||
// and/or other materials provided with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors
|
||||
// may be used to endorse or promote products derived from this software
|
||||
// without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
|
||||
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
// CONTRACT, STRICT LIABILITY0x200004, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
// POSSIBILITY OF SUCH DAMAGE.
|
||||
//
|
||||
// Contributors:
|
||||
// eyck@minres.com - initial API and implementation
|
||||
//
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// todo: truncate values beyond 7 (in prio_threshold write_cb)
|
||||
|
||||
#include "plic.h"
|
||||
#include "gen/plic_regs.h"
|
||||
#include "scc/utilities.h"
|
||||
#include <scc/report.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
plic::plic(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, tlm_target<>(clk)
|
||||
, NAMED(clk_i)
|
||||
, NAMED(rst_i)
|
||||
, NAMED(global_interrupts_i, 256)
|
||||
, NAMED(core_interrupt_o)
|
||||
, NAMEDD(regs, plic_regs)
|
||||
{
|
||||
regs->registerResources(*this);
|
||||
// register callbacks
|
||||
init_callbacks();
|
||||
regs->claim_complete.set_write_cb(m_claim_complete_write_cb);
|
||||
|
||||
// port callbacks
|
||||
SC_METHOD(global_int_port_cb);
|
||||
for (uint8_t i = 0; i < 255; i++) {
|
||||
sensitive << global_interrupts_i[i].pos();
|
||||
}
|
||||
dont_initialize();
|
||||
|
||||
// register event callbacks
|
||||
SC_METHOD(clock_cb);
|
||||
sensitive << clk_i;
|
||||
SC_METHOD(reset_cb);
|
||||
sensitive << rst_i;
|
||||
}
|
||||
|
||||
plic::~plic() = default;
|
||||
|
||||
void plic::init_callbacks() {
|
||||
m_claim_complete_write_cb = [=](scc::sc_register<uint32_t> reg, uint32_t v) -> bool {
|
||||
reg.put(v);
|
||||
reset_pending_int(v);
|
||||
// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
|
||||
// todo: reset related interrupt and find next high-prio interrupt
|
||||
return true;
|
||||
};
|
||||
}
|
||||
|
||||
void plic::clock_cb() { this->clk = clk_i.read(); }
|
||||
|
||||
void plic::reset_cb() {
|
||||
if (rst_i.read())
|
||||
regs->reset_start();
|
||||
else
|
||||
regs->reset_stop();
|
||||
}
|
||||
|
||||
// Functional handling of interrupts:
|
||||
// - global_int_port_cb()
|
||||
// - set pending register bits
|
||||
// - called by: incoming global_int
|
||||
// - handle_pending_int()
|
||||
// - update claim register content
|
||||
// - generate core-interrupt pulse
|
||||
// - called by:
|
||||
// - incoming global_int
|
||||
// - complete-register write access
|
||||
// - reset_pending_int(int-id)
|
||||
// - reset pending bit
|
||||
// - call next handle_pending_int()
|
||||
// - called by:
|
||||
// - complete-reg write register content
|
||||
|
||||
void plic::global_int_port_cb() {
|
||||
|
||||
// set related pending bit if enable is set for incoming global_interrupt
|
||||
|
||||
// todo: extend up to 255 bits (limited to 32 right now)
|
||||
for (uint32_t i = 1; i < 32; i++) {
|
||||
uint32_t enable_bits = regs->r_enabled;
|
||||
bool enable = enable_bits & (0x1 << i); // read enable bit
|
||||
|
||||
if (enable && global_interrupts_i[i].read() == 1) {
|
||||
regs->r_pending = regs->r_pending | (0x1 << i);
|
||||
SCCDEBUG("plic") << "pending interrupt identified: " << i;
|
||||
}
|
||||
}
|
||||
|
||||
handle_pending_int();
|
||||
}
|
||||
|
||||
void plic::handle_pending_int() {
|
||||
// identify high-prio pending interrupt and raise a core-interrupt
|
||||
uint32_t claim_int = 0; // claim interrupt
|
||||
uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race)
|
||||
bool raise_int = false;
|
||||
uint32_t thold = regs->r_threshold.threshold; // threshold value
|
||||
|
||||
// todo: extend up to 255 bits (limited to 32 right now)
|
||||
for (uint32_t i = 1; i < 32; i++) {
|
||||
uint32_t pending_bits = regs->r_pending;
|
||||
bool pending = (pending_bits & (0x1 << i)) ? true : false;
|
||||
uint32_t prio = regs->r_priority[i - 1].priority; // read priority value
|
||||
|
||||
if (pending && thold < prio) {
|
||||
regs->r_pending = regs->r_pending | (0x1 << i);
|
||||
// below condition ensures implicitly that lowest id is selected in case of multiple identical
|
||||
// priority-interrupts
|
||||
if (prio > claim_prio) {
|
||||
claim_prio = prio;
|
||||
claim_int = i;
|
||||
raise_int = true;
|
||||
SCCDEBUG("plic") << "pending interrupt activated: " << i;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (raise_int) {
|
||||
regs->r_claim_complete = claim_int;
|
||||
core_interrupt_o.write(true);
|
||||
// todo: evluate clock period
|
||||
} else {
|
||||
regs->r_claim_complete = 0;
|
||||
SCCDEBUG("plic") << "no further pending interrupt.";
|
||||
}
|
||||
}
|
||||
|
||||
void plic::reset_pending_int(uint32_t irq) {
|
||||
// todo: evaluate enable register (see spec)
|
||||
// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
|
||||
SCCDEBUG("plic") << "reset pending interrupt: " << irq;
|
||||
// reset related pending bit
|
||||
regs->r_pending &= ~(0x1 << irq);
|
||||
core_interrupt_o.write(false);
|
||||
|
||||
// evaluate next pending interrupt
|
||||
handle_pending_int();
|
||||
}
|
||||
|
||||
} /* namespace sysc */
|
57
examples/simple_system/plic.h
Normal file
57
examples/simple_system/plic.h
Normal file
@ -0,0 +1,57 @@
|
||||
/*******************************************************************************
|
||||
* Copyright 2017 eyck@minres.com
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
* use this file except in compliance with the License. You may obtain a copy
|
||||
* of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations under
|
||||
* the License.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _PLIC_H_
|
||||
#define _PLIC_H_
|
||||
|
||||
#include <scc/register.h>
|
||||
#include <scc/tlm_target.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class plic_regs;
|
||||
|
||||
class plic : public sc_core::sc_module, public scc::tlm_target<> {
|
||||
public:
|
||||
SC_HAS_PROCESS(plic);
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i;
|
||||
sc_core::sc_in<bool> rst_i;
|
||||
sc_core::sc_vector<sc_core::sc_in<bool>> global_interrupts_i;
|
||||
sc_core::sc_out<bool> core_interrupt_o;
|
||||
sc_core::sc_event raise_int_ev;
|
||||
sc_core::sc_event clear_int_ev;
|
||||
plic(sc_core::sc_module_name nm);
|
||||
virtual ~plic();
|
||||
|
||||
protected:
|
||||
void clock_cb();
|
||||
void reset_cb();
|
||||
void init_callbacks();
|
||||
|
||||
void global_int_port_cb();
|
||||
void handle_pending_int();
|
||||
void reset_pending_int(uint32_t irq);
|
||||
|
||||
void raise_core_interrupt();
|
||||
void clear_core_interrupt();
|
||||
sc_core::sc_time clk;
|
||||
std::unique_ptr<plic_regs> regs;
|
||||
std::function<bool(scc::sc_register<uint32_t>, uint32_t)> m_claim_complete_write_cb;
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _PLIC_H_ */
|
92
examples/simple_system/sc_main.cpp
Normal file
92
examples/simple_system/sc_main.cpp
Normal file
@ -0,0 +1,92 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright 2017 eyck@minres.com
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
// use this file except in compliance with the License. You may obtain a copy
|
||||
// of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
// License for the specific language governing permissions and limitations under
|
||||
// the License.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/*
|
||||
* sc_main.cpp
|
||||
*
|
||||
* Created on: 17.09.2017
|
||||
* Author: eyck@minres.com
|
||||
*/
|
||||
|
||||
#include "simple_system.h"
|
||||
#include <scc/report.h>
|
||||
#include <scc/tracer.h>
|
||||
#include <boost/program_options.hpp>
|
||||
|
||||
using namespace sysc;
|
||||
using namespace scc;
|
||||
namespace po = boost::program_options;
|
||||
|
||||
namespace {
|
||||
const size_t ERROR_IN_COMMAND_LINE = 1;
|
||||
const size_t SUCCESS = 0;
|
||||
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
|
||||
} // namespace
|
||||
|
||||
int sc_main(int argc, char *argv[]) {
|
||||
sc_core::sc_report_handler::set_actions( "/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING );
|
||||
sc_core::sc_report_handler::set_actions(sc_core::SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, sc_core::SC_DO_NOTHING);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// CLI argument parsing
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
po::options_description desc("Options");
|
||||
// clang-format off
|
||||
desc.add_options()
|
||||
("help,h", "Print help message")
|
||||
("debug,d", "set debug level")
|
||||
("trace,t", "trace SystemC signals");
|
||||
// clang-format on
|
||||
po::variables_map vm;
|
||||
try {
|
||||
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
|
||||
// --help option
|
||||
if (vm.count("help")) {
|
||||
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
|
||||
return SUCCESS;
|
||||
}
|
||||
po::notify(vm); // throws on error, so do after help in case
|
||||
// there are any problems
|
||||
} catch (po::error &e) {
|
||||
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
|
||||
std::cerr << desc << std::endl;
|
||||
return ERROR_IN_COMMAND_LINE;
|
||||
}
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// configure logging
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
scc::init_logging(vm.count("debug")?scc::log::DEBUG:scc::log::INFO);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// set up tracing & transaction recording
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
tracer trace("simple_system", tracer::COMPRESSED, vm.count("trace"));
|
||||
// todo: fix displayed clock period in VCD
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// instantiate top level
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
simple_system i_simple_system("i_simple_system");
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// run simulation
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
sc_start(sc_core::sc_time(1, sc_core::SC_MS));
|
||||
// todo: provide end-of-simulation macros
|
||||
|
||||
if (!sc_core::sc_end_of_simulation_invoked()) {
|
||||
SCCERR() << "simulation timed out";
|
||||
sc_core::sc_stop();
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
87
examples/simple_system/simple_system.cpp
Normal file
87
examples/simple_system/simple_system.cpp
Normal file
@ -0,0 +1,87 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright 2017 eyck@minres.com
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
// use this file except in compliance with the License. You may obtain a copy
|
||||
// of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
// License for the specific language governing permissions and limitations under
|
||||
// the License.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/*
|
||||
* simplesystem.cpp
|
||||
*
|
||||
* Created on: 17.09.2017
|
||||
* Author: eyck@minres.com
|
||||
*/
|
||||
|
||||
#include "simple_system.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
simple_system::simple_system(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, NAMED(i_master)
|
||||
, NAMED(i_router, 4, 1)
|
||||
, NAMED(i_uart)
|
||||
, NAMED(i_spi)
|
||||
, NAMED(i_gpio)
|
||||
, NAMED(i_plic)
|
||||
, NAMED(s_clk)
|
||||
, NAMED(s_rst)
|
||||
, NAMED(s_global_interrupts, 256)
|
||||
, NAMED(s_core_interrupt)
|
||||
, NAMED(s_gpio, 32)
|
||||
{
|
||||
// todo: discuss naming conventions (s_<signal> vs. <port>_i/_o) --> covnert into _s
|
||||
|
||||
// bus connections
|
||||
i_master.intor(i_router.target[0]);
|
||||
i_router.bind_target(i_plic.socket, 0, "plic");
|
||||
i_router.bind_target(i_uart.socket, 1, "uart");
|
||||
i_router.bind_target(i_spi.socket, 2, "spi");
|
||||
i_router.bind_target(i_gpio.socket, 3, "gpio");
|
||||
|
||||
// target address ranges
|
||||
for (const auto &e : e300_plat_map)
|
||||
i_router.add_target_range(e.name, e.start, e.size);
|
||||
|
||||
// clock/reset connections
|
||||
i_uart.clk_i(s_clk);
|
||||
i_spi.clk_i(s_clk);
|
||||
i_gpio.clk_i(s_clk);
|
||||
i_plic.clk_i(s_clk);
|
||||
s_clk.write(10_ns);
|
||||
|
||||
i_uart.rst_i(s_rst);
|
||||
i_spi.rst_i(s_rst);
|
||||
i_gpio.rst_i(s_rst);
|
||||
i_plic.rst_i(s_rst);
|
||||
i_master.rst_i(s_rst);
|
||||
|
||||
// interrupt connections
|
||||
i_plic.core_interrupt_o(s_core_interrupt);
|
||||
i_plic.global_interrupts_i.bind(s_global_interrupts);
|
||||
i_master.global_interrupts_o(s_global_interrupts);
|
||||
i_master.core_interrupt_i(s_core_interrupt);
|
||||
|
||||
for(auto i=0U; i<s_gpio.size(); ++i){
|
||||
s_gpio[i].in(i_gpio.pins_o[i]);
|
||||
i_gpio.pins_i[i](s_gpio[i].out);
|
||||
}
|
||||
|
||||
SC_THREAD(gen_reset);
|
||||
}
|
||||
|
||||
void simple_system::gen_reset() {
|
||||
s_rst = true;
|
||||
wait(10_ns);
|
||||
s_rst = false;
|
||||
}
|
||||
|
||||
} /* namespace sysc */
|
64
examples/simple_system/simple_system.h
Normal file
64
examples/simple_system/simple_system.h
Normal file
@ -0,0 +1,64 @@
|
||||
/*******************************************************************************
|
||||
* Copyright 2017 eyck@minres.com
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
* use this file except in compliance with the License. You may obtain a copy
|
||||
* of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations under
|
||||
* the License.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* simplesystem.h
|
||||
*
|
||||
* Created on: 17.09.2017
|
||||
* Author: eyck@minres.com
|
||||
*/
|
||||
|
||||
#ifndef SIMPLESYSTEM_H_
|
||||
#define SIMPLESYSTEM_H_
|
||||
|
||||
#include "gpio.h"
|
||||
#include "plic.h"
|
||||
#include "spi.h"
|
||||
#include "uart.h"
|
||||
|
||||
#include "test_initiator.h"
|
||||
#include <array>
|
||||
#include <sysc/kernel/sc_module.h>
|
||||
#include <scc/router.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class simple_system : public sc_core::sc_module {
|
||||
public:
|
||||
SC_HAS_PROCESS(simple_system);
|
||||
|
||||
test_initiator i_master;
|
||||
scc::router<> i_router;
|
||||
uart i_uart;
|
||||
spi i_spi;
|
||||
gpio i_gpio;
|
||||
plic i_plic;
|
||||
sc_core::sc_signal<sc_core::sc_time> s_clk;
|
||||
sc_core::sc_signal<bool> s_rst;
|
||||
sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_interrupts;
|
||||
sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> s_core_interrupt;
|
||||
sc_core::sc_vector<tlm::scc::tlm_signal<>> s_gpio;
|
||||
|
||||
simple_system(sc_core::sc_module_name nm);
|
||||
|
||||
protected:
|
||||
void gen_reset();
|
||||
|
||||
#include "gen/e300_plat_t.h"
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* SIMPLESYSTEM_H_ */
|
47
examples/simple_system/spi.cpp
Normal file
47
examples/simple_system/spi.cpp
Normal file
@ -0,0 +1,47 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright 2017 eyck@minres.com
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
// use this file except in compliance with the License. You may obtain a copy
|
||||
// of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
// License for the specific language governing permissions and limitations under
|
||||
// the License.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "spi.h"
|
||||
#include "gen/spi_regs.h"
|
||||
#include "scc/utilities.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
spi::spi(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, tlm_target<>(clk)
|
||||
, NAMED(clk_i)
|
||||
, NAMED(rst_i)
|
||||
, NAMEDD(regs, spi_regs) {
|
||||
regs->registerResources(*this);
|
||||
SC_METHOD(clock_cb);
|
||||
sensitive << clk_i;
|
||||
SC_METHOD(reset_cb);
|
||||
sensitive << rst_i;
|
||||
}
|
||||
|
||||
spi::~spi() {} // NOLINT
|
||||
|
||||
void spi::clock_cb() { this->clk = clk_i.read(); }
|
||||
|
||||
void spi::reset_cb() {
|
||||
if (rst_i.read())
|
||||
regs->reset_start();
|
||||
else
|
||||
regs->reset_stop();
|
||||
}
|
||||
|
||||
} /* namespace sysc */
|
43
examples/simple_system/spi.h
Normal file
43
examples/simple_system/spi.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*******************************************************************************
|
||||
* Copyright 2017 eyck@minres.com
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
* use this file except in compliance with the License. You may obtain a copy
|
||||
* of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations under
|
||||
* the License.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _SPI_H_
|
||||
#define _SPI_H_
|
||||
|
||||
#include <scc/tlm_target.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class spi_regs;
|
||||
|
||||
class spi : public sc_core::sc_module, public scc::tlm_target<> {
|
||||
public:
|
||||
SC_HAS_PROCESS(spi);
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i;
|
||||
sc_core::sc_in<bool> rst_i;
|
||||
spi(sc_core::sc_module_name nm);
|
||||
virtual ~spi();
|
||||
|
||||
protected:
|
||||
void clock_cb();
|
||||
void reset_cb();
|
||||
sc_core::sc_time clk;
|
||||
std::unique_ptr<spi_regs> regs;
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _SPI_H_ */
|
272
examples/simple_system/test_initiator.cpp
Normal file
272
examples/simple_system/test_initiator.cpp
Normal file
@ -0,0 +1,272 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright 2017 eyck@minres.com
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
// use this file except in compliance with the License. You may obtain a copy
|
||||
// of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
// License for the specific language governing permissions and limitations under
|
||||
// the License.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/*
|
||||
* test_initiator.cpp
|
||||
*
|
||||
* Created on: 17.09.2017
|
||||
* Author: eyck@minres.com
|
||||
*/
|
||||
|
||||
#include "test_initiator.h"
|
||||
#include <array>
|
||||
#include <scc/report.h>
|
||||
#include <scc/utilities.h>
|
||||
|
||||
// todo: move into gen folder somewhere (adapt code-generator)
|
||||
#define PLIC_PRIO1_REG 0x0C000004
|
||||
#define PLIC_PRIO2_REG 0x0C000008
|
||||
#define PLIC_PRIO3_REG 0x0C00000C
|
||||
#define PLIC_PRIO4_REG 0x0C000010
|
||||
#define PLIC_PENDING_REG 0x0C001000
|
||||
#define PLIC_ENABLE_REG 0x0C002000
|
||||
#define PLIC_PRIO_TRESHOLD_REG 0x0C200000
|
||||
#define PLIC_CLAIM_COMPLETE_REG 0x0C200004
|
||||
|
||||
namespace sysc {
|
||||
using namespace sc_core;
|
||||
|
||||
test_initiator::test_initiator(sc_module_name nm)
|
||||
: sc_module(nm)
|
||||
, NAMED(intor)
|
||||
, NAMED(rst_i)
|
||||
, NAMED(global_interrupts_o, 256)
|
||||
, NAMED(core_interrupt_i) {
|
||||
SC_THREAD(run);
|
||||
|
||||
SC_METHOD(core_irq_handler);
|
||||
sensitive << core_interrupt_i;
|
||||
dont_initialize();
|
||||
}
|
||||
|
||||
void test_initiator::run() {
|
||||
// wait for reset
|
||||
if (rst_i.read() == false) wait(rst_i.posedge_event());
|
||||
wait(rst_i.negedge_event());
|
||||
wait(10_ns);
|
||||
|
||||
// apply test-sequences
|
||||
test_unique_irq();
|
||||
test_frequent_irq();
|
||||
test_parallel_irq();
|
||||
test_irq_stress();
|
||||
|
||||
// todo: review irq sequences from FW point of view ... expected ???
|
||||
wait(100_ns);
|
||||
sc_stop();
|
||||
}
|
||||
|
||||
void test_initiator::test_unique_irq() {
|
||||
|
||||
//// enable reg is not set
|
||||
// -> irq to be ignored
|
||||
// -> no core_interrupt
|
||||
// -> no entry in pending reg
|
||||
|
||||
// generate interrupt pulse (note: 1 is lowest usable register)
|
||||
global_interrupts_o[2].write(true);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[2].write(false);
|
||||
wait(10_ns);
|
||||
|
||||
reg_check(PLIC_PENDING_REG, 0x0);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
|
||||
wait(10_ns);
|
||||
|
||||
//// enable reg is set, then
|
||||
// -> pending bit change expected
|
||||
// -> core_interrupt expected
|
||||
|
||||
read_bus(PLIC_PRIO1_REG);
|
||||
wait(10_ns);
|
||||
|
||||
// enable single interrupt
|
||||
write_bus(PLIC_PRIO1_REG, 0x1);
|
||||
wait(10_ns);
|
||||
|
||||
write_bus(PLIC_ENABLE_REG, 0x2);
|
||||
wait(10_ns);
|
||||
|
||||
// generate interrupt pulse (note: 1 is lowest usable register)
|
||||
global_interrupts_o[1].write(true);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[1].write(false);
|
||||
wait(10_ns);
|
||||
|
||||
// read claim_complete register
|
||||
reg_check(PLIC_PENDING_REG, 0x2);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x1);
|
||||
wait(10_ns);
|
||||
|
||||
//// after writing to claim_complete reg (per fw)
|
||||
// -> pending bit expected to be unset
|
||||
// -> enable bit expected to be set ... test with / without enable being set
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x1);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0x0);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
|
||||
wait(10_ns);
|
||||
|
||||
// todo: remove wait statements once the tlm_initiator is in place
|
||||
// todo: evaluate error messages ... provide correct pass/fail verdict
|
||||
|
||||
wait(100_ns);
|
||||
}
|
||||
|
||||
void test_initiator::test_frequent_irq() {}
|
||||
|
||||
void test_initiator::test_parallel_irq() {
|
||||
|
||||
//// create three parallel global_int requests
|
||||
// -> read and clear bits one after the other
|
||||
// -> different priorities applied (reverse order)
|
||||
// -> correct priority handing expected
|
||||
// -> three core interrupts expected in total
|
||||
|
||||
// reverse order priority configuration
|
||||
write_bus(PLIC_PRIO1_REG, 0x3);
|
||||
wait(10_ns);
|
||||
write_bus(PLIC_PRIO2_REG, 0x2);
|
||||
wait(10_ns);
|
||||
write_bus(PLIC_PRIO3_REG, 0x1);
|
||||
wait(10_ns);
|
||||
|
||||
// enable all three interrupts
|
||||
write_bus(PLIC_ENABLE_REG, 0xE);
|
||||
wait(10_ns);
|
||||
|
||||
// generate interrupt pulse (note: 1 is lowest usable register)
|
||||
global_interrupts_o[1].write(true);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[1].write(false);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[2].write(true);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[2].write(false);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[3].write(true);
|
||||
wait(10_ns);
|
||||
global_interrupts_o[3].write(false);
|
||||
wait(10_ns);
|
||||
|
||||
// expect three pending registers
|
||||
reg_check(PLIC_PENDING_REG, 0xE);
|
||||
wait(10_ns);
|
||||
|
||||
// expect lowest interrupt id to be highest int
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x1);
|
||||
wait(10_ns);
|
||||
|
||||
//// after writing to claim_complete reg (per fw)
|
||||
// -> next int to become highest irq
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x1);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0xC);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x2);
|
||||
wait(10_ns);
|
||||
|
||||
//// after writing to claim_complete reg again (per fw)
|
||||
// -> next int to become highest irq
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x2);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0x8);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x3);
|
||||
wait(10_ns);
|
||||
|
||||
//// after last writing to claim_complete reg again (per fw)
|
||||
// -> no further pending irq expected
|
||||
write_bus(PLIC_CLAIM_COMPLETE_REG, 0x3);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_PENDING_REG, 0x0);
|
||||
wait(10_ns);
|
||||
reg_check(PLIC_CLAIM_COMPLETE_REG, 0x0);
|
||||
wait(10_ns);
|
||||
|
||||
// todo: advance upon register-write access ... remove above 10_ns waits
|
||||
// todo: evaluate error messages ... provide correct pass/fail verdict
|
||||
|
||||
wait(100_ns);
|
||||
}
|
||||
|
||||
void test_initiator::test_irq_stress() {}
|
||||
|
||||
void test_initiator::write_bus(std::uint32_t adr, std::uint32_t dat) {
|
||||
tlm::tlm_generic_payload gp;
|
||||
std::array<uint8_t, 4> data;
|
||||
data[3] = 0xff & dat >> 24;
|
||||
data[2] = 0xff & dat >> 16;
|
||||
data[1] = 0xff & dat >> 8;
|
||||
data[0] = 0xff & dat;
|
||||
|
||||
SCCDEBUG("test_initiator") << "write_bus(0x" << std::hex << adr << ") : " << dat;
|
||||
|
||||
gp.set_command(tlm::TLM_WRITE_COMMAND);
|
||||
gp.set_address(adr);
|
||||
gp.set_data_ptr(data.data());
|
||||
gp.set_data_length(data.size());
|
||||
gp.set_streaming_width(4);
|
||||
sc_time delay;
|
||||
intor->b_transport(gp, delay);
|
||||
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
throw std::exception();
|
||||
}
|
||||
}
|
||||
|
||||
std::uint32_t test_initiator::read_bus(std::uint32_t adr) {
|
||||
|
||||
tlm::tlm_generic_payload gp;
|
||||
std::array<uint8_t, 4> data;
|
||||
|
||||
gp.set_command(tlm::TLM_READ_COMMAND);
|
||||
gp.set_address(adr);
|
||||
gp.set_data_ptr(data.data());
|
||||
gp.set_data_length(data.size());
|
||||
gp.set_streaming_width(4);
|
||||
sc_time delay;
|
||||
intor->b_transport(gp, delay);
|
||||
|
||||
if (gp.get_response_status() != tlm::TLM_OK_RESPONSE) {
|
||||
// todo: improve output in case of exception, define own exception class to carry transaction-infos
|
||||
// ... i.e. out-of-range report with info about legal mem boundaries
|
||||
throw std::exception();
|
||||
}
|
||||
|
||||
// todo: use reinterpret_cast instead
|
||||
std::uint32_t rdat = data[3] << 24 | data[2] << 16 | data[1] << 8 | data[0];
|
||||
|
||||
SCCDEBUG("test_initiator") << "read_bus(0x" << std::hex << adr << ") -> " << rdat;
|
||||
return rdat;
|
||||
}
|
||||
|
||||
void test_initiator::reg_check(std::uint32_t adr, std::uint32_t exp) {
|
||||
uint32_t dat = read_bus(adr);
|
||||
if (dat != exp) {
|
||||
SCCERR("test_initiator") << "register check failed for address 0x" << std::hex << adr << ": " << dat << " != " << exp;
|
||||
} else {
|
||||
SCCDEBUG("test_initiator") << "register check passed for address 0x" << std::hex << adr << ": " << dat;
|
||||
}
|
||||
}
|
||||
|
||||
void test_initiator::core_irq_handler() {
|
||||
SCCDEBUG("test_initiator") << "core_interrupt_i edge detected -> " << core_interrupt_i.read();
|
||||
}
|
||||
|
||||
} /* namespace sysc */
|
55
examples/simple_system/test_initiator.h
Normal file
55
examples/simple_system/test_initiator.h
Normal file
@ -0,0 +1,55 @@
|
||||
/*******************************************************************************
|
||||
* Copyright 2017 eyck@minres.com
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
* use this file except in compliance with the License. You may obtain a copy
|
||||
* of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations under
|
||||
* the License.
|
||||
******************************************************************************/
|
||||
/*
|
||||
* test_initiator.h
|
||||
*
|
||||
* Created on: 17.09.2017
|
||||
* Author: eyck@minres.com
|
||||
*/
|
||||
|
||||
#ifndef _TEST_INITIATOR_H_
|
||||
#define _TEST_INITIATOR_H_
|
||||
|
||||
#include <scc/utilities.h>
|
||||
#include <tlm_utils/simple_initiator_socket.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class test_initiator : public sc_core::sc_module {
|
||||
public:
|
||||
SC_HAS_PROCESS(test_initiator);
|
||||
tlm_utils::simple_initiator_socket<test_initiator, 32> intor;
|
||||
sc_core::sc_vector<sc_core::sc_out<bool>> global_interrupts_o;
|
||||
sc_core::sc_in<bool> core_interrupt_i;
|
||||
sc_core::sc_in<bool> rst_i;
|
||||
test_initiator(sc_core::sc_module_name nm);
|
||||
|
||||
protected:
|
||||
void run();
|
||||
void test_unique_irq();
|
||||
void test_frequent_irq();
|
||||
void test_parallel_irq();
|
||||
void test_irq_stress();
|
||||
void write_bus(std::uint32_t adr, std::uint32_t dat);
|
||||
std::uint32_t read_bus(std::uint32_t adr);
|
||||
void reg_check(std::uint32_t adr, std::uint32_t exp);
|
||||
|
||||
void core_irq_handler();
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _TEST_INITIATOR_H_ */
|
47
examples/simple_system/uart.cpp
Normal file
47
examples/simple_system/uart.cpp
Normal file
@ -0,0 +1,47 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright 2017 eyck@minres.com
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
// use this file except in compliance with the License. You may obtain a copy
|
||||
// of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
// License for the specific language governing permissions and limitations under
|
||||
// the License.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "uart.h"
|
||||
#include "gen/uart_regs.h"
|
||||
#include "scc/utilities.h"
|
||||
|
||||
namespace sysc {
|
||||
|
||||
uart::uart(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, tlm_target<>(clk)
|
||||
, NAMED(clk_i)
|
||||
, NAMED(rst_i)
|
||||
, NAMEDD(regs, uart_regs) {
|
||||
regs->registerResources(*this);
|
||||
SC_METHOD(clock_cb);
|
||||
sensitive << clk_i;
|
||||
SC_METHOD(reset_cb);
|
||||
sensitive << rst_i;
|
||||
}
|
||||
|
||||
uart::~uart() {} // NOLINT
|
||||
|
||||
void uart::clock_cb() { this->clk = clk_i.read(); }
|
||||
|
||||
void uart::reset_cb() {
|
||||
if (rst_i.read())
|
||||
regs->reset_start();
|
||||
else
|
||||
regs->reset_stop();
|
||||
}
|
||||
|
||||
} /* namespace sysc */
|
43
examples/simple_system/uart.h
Normal file
43
examples/simple_system/uart.h
Normal file
@ -0,0 +1,43 @@
|
||||
/*******************************************************************************
|
||||
* Copyright 2017 eyck@minres.com
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
* use this file except in compliance with the License. You may obtain a copy
|
||||
* of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations under
|
||||
* the License.
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef _UART_H_
|
||||
#define _UART_H_
|
||||
|
||||
#include <scc/tlm_target.h>
|
||||
|
||||
namespace sysc {
|
||||
|
||||
class uart_regs;
|
||||
|
||||
class uart : public sc_core::sc_module, public scc::tlm_target<> {
|
||||
public:
|
||||
SC_HAS_PROCESS(uart);
|
||||
sc_core::sc_in<sc_core::sc_time> clk_i;
|
||||
sc_core::sc_in<bool> rst_i;
|
||||
uart(sc_core::sc_module_name nm);
|
||||
virtual ~uart();
|
||||
|
||||
protected:
|
||||
void clock_cb();
|
||||
void reset_cb();
|
||||
sc_core::sc_time clk;
|
||||
std::unique_ptr<uart_regs> regs;
|
||||
};
|
||||
|
||||
} /* namespace sysc */
|
||||
|
||||
#endif /* _UART_H_ */
|
7
examples/transaction_recording/CMakeLists.txt
Normal file
7
examples/transaction_recording/CMakeLists.txt
Normal file
@ -0,0 +1,7 @@
|
||||
cmake_minimum_required(VERSION 3.12)
|
||||
add_executable (transaction_recording
|
||||
scv_tr_recording_example.cpp
|
||||
)
|
||||
target_link_libraries (transaction_recording LINK_PUBLIC scc)
|
||||
|
||||
add_test(NAME tx_rec_test COMMAND transaction_recording)
|
406
examples/transaction_recording/scv_tr_recording_example.cpp
Normal file
406
examples/transaction_recording/scv_tr_recording_example.cpp
Normal file
@ -0,0 +1,406 @@
|
||||
// -*- C++ -*- <this line is for emacs to recognize it as C++ code>
|
||||
/*****************************************************************************
|
||||
|
||||
The following code is derived, directly or indirectly, from the SystemC
|
||||
source code Copyright (c) 1996-2014 by all Contributors.
|
||||
All Rights reserved.
|
||||
|
||||
The contents of this file are subject to the restrictions and limitations
|
||||
set forth in the SystemC Open Source License (the "License");
|
||||
You may not use this file except in compliance with such restrictions and
|
||||
limitations. You may obtain instructions on how to receive a copy of the
|
||||
License at http://www.accellera.org/. Software distributed by Contributors
|
||||
under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF
|
||||
ANY KIND, either express or implied. See the License for the specific
|
||||
language governing rights and limitations under the License.
|
||||
|
||||
*****************************************************************************/
|
||||
#include "scv.h"
|
||||
#include "scc/scv_tr_db.h"
|
||||
#include "scc/report.h"
|
||||
#include "scc/value_registry.h"
|
||||
#include <chrono>
|
||||
|
||||
// text 11308µs/11602µs
|
||||
// compressed 10365µs/ 9860µs
|
||||
// binary 13233µs/10698µs
|
||||
// SQLite 30363µs/30018µs
|
||||
// LeveDB 23898µs/22367µs
|
||||
|
||||
// hack to fake a true fifo_mutex
|
||||
#define fifo_mutex sc_mutex
|
||||
|
||||
const unsigned ram_size = 256;
|
||||
|
||||
class rw_task_if : virtual public sc_interface {
|
||||
public:
|
||||
using addr_t = sc_uint<8>;
|
||||
using data_t = sc_uint<8>;
|
||||
struct write_t {
|
||||
addr_t addr;
|
||||
data_t data;
|
||||
};
|
||||
|
||||
virtual data_t read(const addr_t *) = 0;
|
||||
virtual void write(const write_t *) = 0;
|
||||
};
|
||||
|
||||
SCV_EXTENSIONS(rw_task_if::write_t) {
|
||||
public:
|
||||
scv_extensions<rw_task_if::addr_t> addr;
|
||||
scv_extensions<rw_task_if::data_t> data;
|
||||
SCV_EXTENSIONS_CTOR(rw_task_if::write_t) {
|
||||
SCV_FIELD(addr);
|
||||
SCV_FIELD(data);
|
||||
}
|
||||
};
|
||||
|
||||
class pipelined_bus_ports : public sc_module {
|
||||
public:
|
||||
sc_in<bool> clk;
|
||||
sc_inout<bool> rw;
|
||||
sc_inout<bool> addr_req;
|
||||
sc_inout<bool> addr_ack;
|
||||
sc_inout<sc_uint<8>> bus_addr;
|
||||
sc_inout<bool> data_rdy;
|
||||
sc_inout<sc_uint<8>> bus_data;
|
||||
|
||||
SC_CTOR(pipelined_bus_ports)
|
||||
: clk("clk")
|
||||
, rw("rw")
|
||||
, addr_req("addr_req")
|
||||
, addr_ack("addr_ack")
|
||||
, bus_addr("bus_addr")
|
||||
, data_rdy("data_rdy")
|
||||
, bus_data("bus_data") {}
|
||||
void trace(sc_trace_file *tf) const override;
|
||||
};
|
||||
|
||||
void pipelined_bus_ports::trace(sc_trace_file *tf) const {
|
||||
sc_trace(tf, clk, clk.name());
|
||||
sc_trace(tf, rw, rw.name());
|
||||
sc_trace(tf, addr_req, addr_req.name());
|
||||
sc_trace(tf, addr_ack, addr_ack.name());
|
||||
sc_trace(tf, bus_addr, bus_addr.name());
|
||||
sc_trace(tf, data_rdy, data_rdy.name());
|
||||
sc_trace(tf, bus_data, bus_data.name());
|
||||
}
|
||||
|
||||
class rw_pipelined_transactor : public rw_task_if, public pipelined_bus_ports {
|
||||
|
||||
fifo_mutex addr_phase;
|
||||
fifo_mutex data_phase;
|
||||
|
||||
scv_tr_stream pipelined_stream;
|
||||
scv_tr_stream addr_stream;
|
||||
scv_tr_stream data_stream;
|
||||
scv_tr_generator<sc_uint<8>, sc_uint<8>> read_gen;
|
||||
scv_tr_generator<sc_uint<8>, sc_uint<8>> write_gen;
|
||||
scv_tr_generator<sc_uint<8>> addr_gen;
|
||||
scv_tr_generator<_scv_tr_generator_default_data, sc_uint<8>> rdata_gen;
|
||||
scv_tr_generator<sc_uint<8>> wdata_gen;
|
||||
|
||||
public:
|
||||
rw_pipelined_transactor(sc_module_name nm)
|
||||
: pipelined_bus_ports(nm)
|
||||
, addr_phase("addr_phase")
|
||||
, data_phase("data_phase")
|
||||
, pipelined_stream((std::string(name()) + ".pipelined_stream").c_str(), "transactor")
|
||||
, addr_stream((std::string(name()) + ".addr_stream").c_str(), "transactor")
|
||||
, data_stream((std::string(name()) + ".data_stream").c_str(), "transactor")
|
||||
, read_gen("read", pipelined_stream, "addr", "data")
|
||||
, write_gen("write", pipelined_stream, "addr", "data")
|
||||
, addr_gen("addr", addr_stream, "addr")
|
||||
, rdata_gen("rdata", data_stream, nullptr, "data")
|
||||
, wdata_gen("wdata", data_stream, "data") {}
|
||||
data_t read(const addr_t *p_addr) override;
|
||||
void write(const write_t *req) override;
|
||||
};
|
||||
|
||||
rw_task_if::data_t rw_pipelined_transactor::read(const addr_t *addr) {
|
||||
addr_phase.lock();
|
||||
scv_tr_handle h = read_gen.begin_transaction(*addr);
|
||||
h.record_attribute("data_size", sizeof(data_t));
|
||||
scv_tr_handle h1 = addr_gen.begin_transaction(*addr, "addr_phase", h);
|
||||
wait(clk->posedge_event());
|
||||
bus_addr = *addr;
|
||||
rw = false;
|
||||
addr_req = true;
|
||||
wait(addr_ack->posedge_event());
|
||||
wait(clk->negedge_event());
|
||||
addr_req = false;
|
||||
wait(addr_ack->negedge_event());
|
||||
addr_gen.end_transaction(h1);
|
||||
addr_phase.unlock();
|
||||
|
||||
data_phase.lock();
|
||||
scv_tr_handle h2 = rdata_gen.begin_transaction("data_phase", h);
|
||||
wait(data_rdy->posedge_event());
|
||||
data_t data = bus_data.read();
|
||||
wait(data_rdy->negedge_event());
|
||||
rdata_gen.end_transaction(h2, data);
|
||||
read_gen.end_transaction(h, data);
|
||||
data_phase.unlock();
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
void rw_pipelined_transactor::write(const write_t *req) {
|
||||
addr_phase.lock();
|
||||
scv_tr_handle h = write_gen.begin_transaction(req->addr);
|
||||
h.record_attribute("data_size", sizeof(data_t));
|
||||
scv_tr_handle h1 = addr_gen.begin_transaction(req->addr, "addr_phase", h);
|
||||
wait(clk->posedge_event());
|
||||
bus_addr = req->addr;
|
||||
rw = true;
|
||||
addr_req = true;
|
||||
wait(addr_ack->posedge_event());
|
||||
wait(clk->negedge_event());
|
||||
addr_req = false;
|
||||
wait(addr_ack->negedge_event());
|
||||
addr_gen.end_transaction(h1);
|
||||
addr_phase.unlock();
|
||||
|
||||
data_phase.lock();
|
||||
scv_tr_handle h2 = wdata_gen.begin_transaction(req->data, "data_phase", h);
|
||||
bus_data = req->data;
|
||||
wait(data_rdy->posedge_event());
|
||||
wait(data_rdy->negedge_event());
|
||||
wdata_gen.end_transaction(h2);
|
||||
write_gen.end_transaction(h, req->data);
|
||||
data_phase.unlock();
|
||||
}
|
||||
|
||||
class test : public sc_module {
|
||||
public:
|
||||
sc_port<rw_task_if> transactor;
|
||||
SC_HAS_PROCESS(test);
|
||||
test(::sc_core::sc_module_name) {
|
||||
SC_THREAD(main1);
|
||||
SC_THREAD(main2);
|
||||
}
|
||||
void main1();
|
||||
void main2();
|
||||
};
|
||||
|
||||
class write_constraint : virtual public scv_constraint_base {
|
||||
public:
|
||||
scv_smart_ptr<rw_task_if::write_t> write;
|
||||
SCV_CONSTRAINT_CTOR(write_constraint) { // NOLINT
|
||||
SCV_CONSTRAINT(write->addr() <= ram_size); // NOLINT
|
||||
SCV_CONSTRAINT(write->addr() != write->data()); // NOLINT
|
||||
}
|
||||
};
|
||||
|
||||
inline void process(scv_smart_ptr<int> data) {}
|
||||
|
||||
inline void test::main1() {
|
||||
// simple sequential tests
|
||||
for (int i = 0; i < 3; i++) {
|
||||
rw_task_if::addr_t addr = i;
|
||||
rw_task_if::data_t data = transactor->read(&addr);
|
||||
SCCINFO(sc_get_current_object()->name()) << "received data : " << data;
|
||||
}
|
||||
|
||||
scv_smart_ptr<rw_task_if::addr_t> addr;
|
||||
for (int i = 0; i < 3; i++) {
|
||||
|
||||
addr->next();
|
||||
rw_task_if::data_t data = transactor->read(addr->get_instance());
|
||||
SCCINFO(sc_get_current_object()->name()) << "data for address " << *addr << " is " << data;
|
||||
}
|
||||
|
||||
scv_smart_ptr<rw_task_if::write_t> write;
|
||||
for (int i = 0; i < 3; i++) {
|
||||
write->next();
|
||||
transactor->write(write->get_instance());
|
||||
SCCINFO(sc_get_current_object()->name()) << "send data : " << write->data;
|
||||
}
|
||||
|
||||
scv_smart_ptr<int> data;
|
||||
scv_bag<int> distribution;
|
||||
distribution.push(1, 40);
|
||||
distribution.push(2, 60);
|
||||
data->set_mode(distribution);
|
||||
for (int i = 0; i < 3; i++) {
|
||||
data->next();
|
||||
process(data);
|
||||
}
|
||||
}
|
||||
|
||||
inline void test::main2() {
|
||||
// simple sequential tests
|
||||
for (int i = 0; i < 3; i++) {
|
||||
rw_task_if::addr_t addr = i;
|
||||
rw_task_if::data_t data = transactor->read(&addr);
|
||||
SCCINFO(sc_get_current_object()->name()) << "received data : " << data;
|
||||
}
|
||||
|
||||
scv_smart_ptr<rw_task_if::addr_t> addr;
|
||||
for (int i = 0; i < 3; i++) {
|
||||
|
||||
addr->next();
|
||||
rw_task_if::data_t data = transactor->read(addr->get_instance());
|
||||
SCCINFO(sc_get_current_object()->name()) << "data for address " << *addr << " is " << data;
|
||||
}
|
||||
|
||||
scv_smart_ptr<rw_task_if::write_t> write;
|
||||
for (int i = 0; i < 3; i++) {
|
||||
write->next();
|
||||
transactor->write(write->get_instance());
|
||||
SCCINFO(sc_get_current_object()->name()) << "send data : " << write->data;
|
||||
}
|
||||
|
||||
scv_smart_ptr<int> data;
|
||||
scv_bag<int> distribution;
|
||||
distribution.push(1, 140);
|
||||
distribution.push(2, 160);
|
||||
data->set_mode(distribution);
|
||||
for (int i = 0; i < 3; i++) {
|
||||
data->next();
|
||||
process(data);
|
||||
}
|
||||
}
|
||||
class design : public pipelined_bus_ports {
|
||||
std::list<sc_uint<8>> outstandingAddresses;
|
||||
std::list<bool> outstandingType;
|
||||
sc_uint<8> memory[ram_size];
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(design);
|
||||
design(sc_module_name nm)
|
||||
: pipelined_bus_ports(nm) {
|
||||
for (unsigned i = 0; i < ram_size; ++i) {
|
||||
memory[i] = i;
|
||||
}
|
||||
SC_THREAD(addr_phase);
|
||||
SC_THREAD(data_phase);
|
||||
}
|
||||
void addr_phase();
|
||||
void data_phase();
|
||||
};
|
||||
|
||||
inline void design::addr_phase() {
|
||||
while (true) {
|
||||
while (addr_req.read() != 1) {
|
||||
wait(addr_req->value_changed_event());
|
||||
}
|
||||
sc_uint<8> _addr = bus_addr.read();
|
||||
bool _rw = rw.read();
|
||||
|
||||
int cycle = rand() % 10 + 1;
|
||||
while (cycle-- > 0) {
|
||||
wait(clk->posedge_event());
|
||||
}
|
||||
|
||||
addr_ack = true;
|
||||
wait(clk->posedge_event());
|
||||
addr_ack = false;
|
||||
|
||||
outstandingAddresses.push_back(_addr);
|
||||
outstandingType.push_back(_rw);
|
||||
SCCINFO(sc_get_current_object()->name()) << "received request for memory address " << _addr;
|
||||
}
|
||||
}
|
||||
|
||||
inline void design::data_phase() {
|
||||
while (true) {
|
||||
while (outstandingAddresses.empty()) {
|
||||
wait(clk->posedge_event());
|
||||
}
|
||||
int cycle = rand() % 10 + 1;
|
||||
while (cycle-- > 0) {
|
||||
wait(clk->posedge_event());
|
||||
}
|
||||
if (outstandingType.front() == false) {
|
||||
SCCINFO(sc_get_current_object()->name()) << "reading memory address " << outstandingAddresses.front() << " with value "
|
||||
<< memory[outstandingAddresses.front().to_ulong()];
|
||||
bus_data = memory[outstandingAddresses.front().to_ulong()];
|
||||
data_rdy = true;
|
||||
wait(clk->posedge_event());
|
||||
data_rdy = false;
|
||||
|
||||
} else {
|
||||
SCCINFO(sc_get_current_object()->name()) << "writing memory address " << outstandingAddresses.front() << " with value " << bus_data;
|
||||
memory[outstandingAddresses.front().to_ulong()] = bus_data;
|
||||
data_rdy = true;
|
||||
wait(clk->posedge_event());
|
||||
data_rdy = false;
|
||||
}
|
||||
outstandingAddresses.pop_front();
|
||||
outstandingType.pop_front();
|
||||
}
|
||||
}
|
||||
|
||||
inline const char* init_db(char type){
|
||||
switch(type){
|
||||
case '2':
|
||||
scv_tr_compressed_init();
|
||||
return "my_db.txlog";
|
||||
break;
|
||||
case '3':
|
||||
scv_tr_sqlite_init();
|
||||
return "my_db.txdb";
|
||||
break;
|
||||
default:
|
||||
scv_tr_text_init();
|
||||
return "my_db.txlog";
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
int sc_main(int argc, char *argv[]) {
|
||||
auto start = std::chrono::system_clock::now();
|
||||
scv_startup();
|
||||
scc::init_logging(scc::LogConfig().logLevel(scc::log::DEBUG));
|
||||
const char *fileName = argc==2? init_db(argv[1][0]): "my_db.txlog";
|
||||
if(argc<2) scv_tr_text_init();
|
||||
scv_tr_db db(fileName);
|
||||
scv_tr_db::set_default_db(&db);
|
||||
sc_trace_file *tf = sc_create_vcd_trace_file("my_db");
|
||||
// create signals
|
||||
sc_clock clk("clk", 20.0, SC_NS, 0.5, 0.0, SC_NS, true);
|
||||
sc_signal<bool> rw;
|
||||
sc_signal<bool> addr_req;
|
||||
sc_signal<bool> addr_ack;
|
||||
sc_signal<sc_uint<8>> bus_addr;
|
||||
sc_signal<bool> data_rdy;
|
||||
sc_signal<sc_uint<8>> bus_data;
|
||||
|
||||
scc::value_registry registry;
|
||||
// create modules/channels
|
||||
test t("t");
|
||||
rw_pipelined_transactor tr("tr");
|
||||
design duv("duv");
|
||||
|
||||
// connect them up
|
||||
t.transactor(tr);
|
||||
|
||||
tr.clk(clk);
|
||||
tr.rw(rw);
|
||||
tr.addr_req(addr_req);
|
||||
tr.addr_ack(addr_ack);
|
||||
tr.bus_addr(bus_addr);
|
||||
tr.data_rdy(data_rdy);
|
||||
tr.bus_data(bus_data);
|
||||
tr.trace(tf);
|
||||
|
||||
duv.clk(clk);
|
||||
duv.rw(rw);
|
||||
duv.addr_req(addr_req);
|
||||
duv.addr_ack(addr_ack);
|
||||
duv.bus_addr(bus_addr);
|
||||
duv.data_rdy(data_rdy);
|
||||
duv.bus_data(bus_data);
|
||||
duv.trace(tf);
|
||||
|
||||
// Accellera SystemC >=2.2 got picky about multiple drivers.
|
||||
// Disable check for bus simulation.
|
||||
sc_report_handler::set_actions(SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, SC_DO_NOTHING);
|
||||
// run the simulation
|
||||
sc_start(10.0, SC_US);
|
||||
sc_close_vcd_trace_file(tf);
|
||||
auto int_us = std::chrono::duration_cast<std::chrono::microseconds>(std::chrono::system_clock::now()-start);
|
||||
SCCINFO() << "simulation duration "<<int_us.count()<<"µs";
|
||||
return 0;
|
||||
}
|
@ -1 +0,0 @@
|
||||
conan<2.0
|
2
scc
2
scc
@ -1 +1 @@
|
||||
Subproject commit 4f27c76e0631da96cfdf421e91c2cd983c3f4253
|
||||
Subproject commit 2a11251ae63f3470245e13f4f576e4c93d2f243c
|
@ -1,5 +0,0 @@
|
||||
project (test_util)
|
||||
|
||||
add_library(${PROJECT_NAME} factory.cpp)
|
||||
target_include_directories(${PROJECT_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR})
|
||||
target_link_libraries (${PROJECT_NAME} PUBLIC scc Catch2::Catch2)
|
@ -1,40 +0,0 @@
|
||||
#include "factory.h"
|
||||
|
||||
#include <stdexcept>
|
||||
|
||||
auto factory::get_instance() -> factory& {
|
||||
static factory instance{};
|
||||
return instance;
|
||||
}
|
||||
|
||||
factory::factory()
|
||||
: m_constructors{}
|
||||
, m_objects{} {}
|
||||
|
||||
void factory::create() {
|
||||
for(const auto& item : m_constructors) {
|
||||
m_objects[item.first] = item.second();
|
||||
}
|
||||
}
|
||||
|
||||
void factory::destroy() { m_objects.clear(); }
|
||||
|
||||
void factory::add_object(const std::string& name, constructor create) {
|
||||
auto it = m_constructors.find(name);
|
||||
|
||||
if(it == m_constructors.cend()) {
|
||||
m_constructors[name] = create;
|
||||
} else {
|
||||
throw std::runtime_error("factory::add(): " + name + " object already exist in factory");
|
||||
}
|
||||
}
|
||||
|
||||
auto factory::get_object(const std::string& name) -> void* {
|
||||
auto it = m_objects.find(name);
|
||||
|
||||
if(it == m_objects.cend()) {
|
||||
throw std::runtime_error("factory::get(): " + name + " object doesn't exist in factory");
|
||||
}
|
||||
|
||||
return it->second.get();
|
||||
}
|
@ -1,65 +0,0 @@
|
||||
/*
|
||||
* according to https://forums.accellera.org/topic/5754-unit-testing-with-gtest/
|
||||
* factory.h
|
||||
*
|
||||
* Created on: Oct 1, 2022
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#ifndef SRC_FACTORY_H_
|
||||
#define SRC_FACTORY_H_
|
||||
|
||||
#include <functional>
|
||||
#include <map>
|
||||
#include <memory>
|
||||
#include <string>
|
||||
|
||||
class factory {
|
||||
public:
|
||||
static factory& get_instance();
|
||||
|
||||
template <typename T, typename... Args> class add {
|
||||
public:
|
||||
add(Args&&... args);
|
||||
|
||||
add(const std::string& name, Args&&... args);
|
||||
};
|
||||
|
||||
template <typename T> static T& get(const std::string& name = "");
|
||||
|
||||
void create();
|
||||
|
||||
void destroy();
|
||||
|
||||
private:
|
||||
using destructor = std::function<void(void*)>;
|
||||
using object = std::unique_ptr<void, destructor>;
|
||||
using constructor = std::function<object(void)>;
|
||||
|
||||
factory();
|
||||
|
||||
factory(const factory& other) = delete;
|
||||
|
||||
factory& operator=(const factory& other) = delete;
|
||||
|
||||
void add_object(const std::string& name, constructor create);
|
||||
|
||||
void* get_object(const std::string& name);
|
||||
|
||||
std::map<std::string, constructor> m_constructors;
|
||||
std::map<std::string, object> m_objects;
|
||||
};
|
||||
|
||||
template <typename T, typename... Args> factory::add<T, Args...>::add(Args&&... args) { add("", args...); }
|
||||
|
||||
template <typename T, typename... Args> factory::add<T, Args...>::add(const std::string& name, Args&&... args) {
|
||||
factory::get_instance().add_object(name, [args...]() -> object {
|
||||
return object{new T(std::forward<Args>(args)...), [](void* obj) { delete static_cast<T*>(obj); }};
|
||||
});
|
||||
}
|
||||
|
||||
template <typename T> auto factory::get(const std::string& name) -> T& {
|
||||
return *static_cast<T*>(factory::get_instance().get_object(name));
|
||||
}
|
||||
|
||||
#endif /* SRC_FACTORY_H_ */
|
@ -1,43 +0,0 @@
|
||||
/*
|
||||
* sc_main.cpp
|
||||
*
|
||||
* Created on:
|
||||
* Author:
|
||||
*/
|
||||
|
||||
#include "factory.h"
|
||||
#include <catch2/catch_session.hpp>
|
||||
#include <csetjmp>
|
||||
#include <csignal>
|
||||
#include <cstdlib>
|
||||
#include <scc/report.h>
|
||||
#include <scc/trace.h>
|
||||
#include <scc/tracer.h>
|
||||
#include <util/ities.h>
|
||||
|
||||
using namespace scc;
|
||||
using namespace sc_core;
|
||||
|
||||
jmp_buf abrt;
|
||||
void ABRThandler(int sig) { longjmp(abrt, 1); }
|
||||
|
||||
int sc_main(int argc, char* argv[]) {
|
||||
signal(SIGABRT, ABRThandler);
|
||||
auto my_name = util::split(argv[0], '/').back();
|
||||
scc::init_logging(LogConfig().logLevel(getenv("SCC_TEST_VERBOSE") ? log::TRACE : log::FATAL).logAsync(false).msgTypeFieldWidth(35));
|
||||
// create tracer if environment variable SCC_TEST_TRACE is defined
|
||||
std::unique_ptr<scc::tracer> tracer;
|
||||
if(getenv("SCC_TEST_TRACE"))
|
||||
tracer = std::make_unique<scc::tracer>(my_name, scc::tracer::NONE, scc::tracer::ENABLE);
|
||||
int result = -1;
|
||||
if(setjmp(abrt) == 0) {
|
||||
// instantiate design(s)
|
||||
factory::get_instance().create();
|
||||
// run tests
|
||||
result = Catch::Session().run(argc, argv);
|
||||
// destroy design(s)
|
||||
sc_stop();
|
||||
factory::get_instance().destroy();
|
||||
}
|
||||
return result;
|
||||
}
|
@ -1,11 +1,3 @@
|
||||
add_subdirectory(io-redirector)
|
||||
add_subdirectory(sim_performance)
|
||||
add_subdirectory(ordered_semaphore)
|
||||
add_subdirectory(cci_param_restricted)
|
||||
add_subdirectory(ahb_pin_level)
|
||||
add_subdirectory(axi4_pin_level)
|
||||
add_subdirectory(ace_pin_level)
|
||||
add_subdirectory(configuration)
|
||||
add_subdirectory(configurer)
|
||||
if(FULL_TEST_SUITE)
|
||||
add_subdirectory(sim_performance)
|
||||
endif()
|
||||
|
@ -1,9 +0,0 @@
|
||||
project (ace_pin_level)
|
||||
|
||||
add_executable(${PROJECT_NAME}
|
||||
ace_narrow_burst_test.cpp
|
||||
${test_util_SOURCE_DIR}/sc_main.cpp
|
||||
)
|
||||
target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
|
||||
|
||||
catch_discover_tests(${PROJECT_NAME})
|
@ -1,275 +0,0 @@
|
||||
|
||||
#include "testbench.h"
|
||||
#include <factory.h>
|
||||
#include <tlm/scc/tlm_gp_shared.h>
|
||||
#undef CHECK
|
||||
#include <catch2/catch_all.hpp>
|
||||
#include <unordered_map>
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
factory::add<testbench> tb;
|
||||
|
||||
int snoop_id = 0;
|
||||
|
||||
bool is_equal(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b) {
|
||||
auto ret = true;
|
||||
ret &= a.get_command() == b.get_command();
|
||||
ret &= a.get_address() == b.get_address();
|
||||
ret &= a.get_data_length() == b.get_data_length();
|
||||
for(auto i = 0u; i < a.get_data_length(); ++i)
|
||||
ret &= a.get_data_ptr()[i] == b.get_data_ptr()[i];
|
||||
// if(a.get_byte_enable_ptr() && b.get_byte_enable_ptr()) {
|
||||
// ret &= a.get_byte_enable_length() == b.get_byte_enable_length();
|
||||
// for(auto i=0u; i<a.get_byte_enable_length(); ++i)
|
||||
// ret &= a.get_byte_enable_ptr()[i] == b.get_byte_enable_ptr()[i];
|
||||
// }
|
||||
ret &= a.get_command() == b.get_command();
|
||||
// if(!ret) SCCWARN()<<"Comparison failed: "<<a<<" and "<<b;
|
||||
return ret;
|
||||
}
|
||||
|
||||
template <typename bus_cfg>
|
||||
tlm::tlm_generic_payload* prepare_trans_ace(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
|
||||
auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::ace_extension>(len);
|
||||
trans->set_address(start_address);
|
||||
tlm::scc::setId(*trans, id);
|
||||
auto ext = trans->get_extension<axi::ace_extension>();
|
||||
trans->set_data_length(len);
|
||||
trans->set_streaming_width(len);
|
||||
ext->set_size(scc::ilog2(width));
|
||||
sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
|
||||
auto length = (len * 8 - 1) / (8 * width);
|
||||
if(width == (bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
|
||||
length++;
|
||||
ext->set_length(length);
|
||||
// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
|
||||
// here len is CachelineSizeBytes
|
||||
// here burtst for read/write_trans and snoop_trans are different
|
||||
ext->set_burst(axi::burst_e::INCR); // TBD???
|
||||
// ext->set_burst(len*8 > bus_cfg::BUSWIDTH ? axi::burst_e::WRAP : axi::burst_e::INCR);
|
||||
ext->set_id(id);
|
||||
ext->set_snoop(axi::snoop_e::READ_SHARED); // set it so that is_data_less return true???
|
||||
return trans;
|
||||
}
|
||||
|
||||
inline void randomize(tlm::tlm_generic_payload& gp) {
|
||||
static uint8_t req_cnt{0};
|
||||
for(size_t i = 0; i < gp.get_data_length(); ++i) {
|
||||
*(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
|
||||
}
|
||||
req_cnt++;
|
||||
}
|
||||
|
||||
template <typename STATE> unsigned run_scenario(STATE& state) {
|
||||
auto& dut = factory::get<testbench>();
|
||||
|
||||
dut.axi_tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned {
|
||||
auto id = axi::get_axi_id(trans);
|
||||
if(trans.is_read()) {
|
||||
for(size_t i = 0; i < trans.get_data_length(); ++i) {
|
||||
*(trans.get_data_ptr() + i) = i % 2 ? 123 : (state.resp_cnt + 128);
|
||||
}
|
||||
state.read_tx[id].second.emplace_back(&trans);
|
||||
}
|
||||
if(trans.is_write())
|
||||
state.write_tx[id].second.emplace_back(&trans);
|
||||
SCCDEBUG(__FUNCTION__) << "RX: " << trans;
|
||||
state.resp_cnt++;
|
||||
return 0;
|
||||
});
|
||||
dut.transport_cb = [&state](tlm::tlm_generic_payload& trans) -> unsigned {
|
||||
SCCDEBUG(__FUNCTION__) << " update snoop trans, with snoop_id = " << snoop_id;
|
||||
// extracting address and snoop_e from ac_trans and pack them into cache data trans
|
||||
auto ac_address = trans.get_address();
|
||||
auto ext = trans.get_extension<ace_extension>();
|
||||
auto ac_snoop = ext->get_snoop();
|
||||
for(size_t i = 0; i < trans.get_data_length(); ++i) {
|
||||
*(trans.get_data_ptr() + i) = i % 2 ? i : 128;
|
||||
}
|
||||
state.snoop_tx[snoop_id].second.emplace_back(&trans);
|
||||
return 1;
|
||||
};
|
||||
|
||||
dut.rst.write(false);
|
||||
sc_start(state.ResetCycles * dut.clk.period());
|
||||
dut.rst.write(true);
|
||||
sc_start(dut.clk.period());
|
||||
|
||||
auto run1 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x0};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
// tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::bus_cfg>(StartAddr, 4,
|
||||
// state.BurstLengthByte, state.BurstSizeBytes, 1);
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
SCCDEBUG(__FUNCTION__) << "run1, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
|
||||
auto run2 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x2000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
SCCDEBUG(__FUNCTION__) << "run2, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
auto run3 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x1000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
SCCDEBUG(__FUNCTION__) << "run3, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
auto run4 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x3000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
SCCDEBUG(__FUNCTION__) << "run4, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
|
||||
auto run5 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x0};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans_ace<testbench::bus_cfg>(StartAddr, 4, state.CachelineSizeBytes, state.BurstSizeBytes, 5);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
SCCDEBUG(__FUNCTION__) << "run1, iteration " << i << "snoop_id = " << snoop_id << " TX: " << *trans;
|
||||
dut.ace_tgt_pe.snoop(*trans);
|
||||
SCCDEBUG(__FUNCTION__) << "run1, after iteration " << i;
|
||||
state.snoop_tx[snoop_id].first.emplace_back(trans);
|
||||
snoop_id++;
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
|
||||
unsigned cycles{0};
|
||||
while(cycles < 1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())) {
|
||||
// while(cycles<1000 && !(run5.terminated())){
|
||||
sc_start(10 * dut.clk.period());
|
||||
cycles += 10;
|
||||
}
|
||||
return cycles;
|
||||
}
|
||||
|
||||
TEST_CASE("ace_burst_alignment", "[AXI][pin-level]") {
|
||||
struct {
|
||||
unsigned int ResetCycles{4};
|
||||
unsigned int BurstLengthByte{16};
|
||||
unsigned int BurstSizeBytes{8};
|
||||
unsigned int NumberOfIterations{2};
|
||||
unsigned int CachelineSizeBytes = {64}; //
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
|
||||
write_tx;
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
|
||||
snoop_tx;
|
||||
unsigned resp_cnt{0};
|
||||
} state;
|
||||
|
||||
state.resp_cnt = 0;
|
||||
auto cycles = run_scenario(state);
|
||||
|
||||
REQUIRE(cycles < 1000);
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
|
||||
REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
|
||||
// REQUIRE(state.resp_cnt==1*state.NumberOfIterations);
|
||||
for(auto& e : state.write_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
|
||||
for(auto& e : state.read_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
SCCDEBUG(__FUNCTION__) << " index = " << i;
|
||||
// SCCDEBUG(__FUNCTION__) <<" send value = "<<*send_tx[i];
|
||||
// SCCDEBUG(__FUNCTION__) <<" received value = "<<*recv_tx[i];
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
|
||||
for(auto& e : state.snoop_tx) {
|
||||
auto const& snoop_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(snoop_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < snoop_tx.size(); ++i) {
|
||||
REQUIRE(snoop_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
SCCDEBUG(__FUNCTION__) << " index = " << i;
|
||||
SCCDEBUG(__FUNCTION__) << " send snoop value = " << *snoop_tx[i];
|
||||
SCCDEBUG(__FUNCTION__) << " received value = " << *recv_tx[i];
|
||||
// CHECK(*snoop_tx[i] == *recv_tx[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ace_narrow_burst", "[AXI][pin-level]") {
|
||||
struct {
|
||||
unsigned int ResetCycles{4};
|
||||
unsigned int BurstLengthByte{16};
|
||||
unsigned int BurstSizeBytes{8};
|
||||
unsigned int NumberOfIterations{2};
|
||||
unsigned int CachelineSizeBytes = {64}; //
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
|
||||
write_tx;
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
|
||||
snoop_tx;
|
||||
unsigned resp_cnt{0};
|
||||
} state;
|
||||
|
||||
state.resp_cnt = 0;
|
||||
auto cycles = run_scenario(state);
|
||||
|
||||
REQUIRE(cycles < 1000);
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
|
||||
REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
|
||||
for(auto& e : state.write_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i)
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
for(auto& e : state.read_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i)
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
@ -1,104 +0,0 @@
|
||||
#ifndef _TESTBENCH_H_
|
||||
#define _TESTBENCH_H_
|
||||
|
||||
#include <axi/pe/axi_initiator.h>
|
||||
#include <axi/pe/simple_ace_target.h>
|
||||
#include <axi/pe/simple_target.h>
|
||||
#include <axi/pin/ace_initiator.h>
|
||||
#include <axi/pin/ace_target.h>
|
||||
#include <axi/scv/recorder_modules.h>
|
||||
#include <scc.h>
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace axi;
|
||||
using namespace axi::pe;
|
||||
|
||||
class testbench : public sc_core::sc_module, public tlm::scc::pe::intor_bw_b {
|
||||
public:
|
||||
using bus_cfg = axi::ace_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1, /*CACHELINE*/ 64>;
|
||||
|
||||
sc_core::sc_time clk_period{10, sc_core::SC_NS};
|
||||
sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};
|
||||
sc_core::sc_signal<bool> rst{"rst"};
|
||||
// test interface, which is bound to initiator bw_o
|
||||
sc_core::sc_export<tlm::scc::pe::intor_bw_b> bw_i{"bw_i"};
|
||||
// initiator side
|
||||
axi::ace_initiator_socket<bus_cfg::BUSWIDTH> intor{"ace_intor"};
|
||||
axi::pin::ace_initiator<bus_cfg> intor_bfm{"ace_intor_bfm"};
|
||||
// signal accurate bus
|
||||
axi::aw_ace<bus_cfg, axi::signal_types> aw;
|
||||
axi::wdata_ace<bus_cfg, axi::signal_types> wdata;
|
||||
axi::b_ace<bus_cfg, axi::signal_types> b;
|
||||
axi::ar_ace<bus_cfg, axi::signal_types> ar;
|
||||
axi::rresp_ace<bus_cfg, axi::signal_types> rresp;
|
||||
axi::ac_ace<bus_cfg, axi::signal_types> ac;
|
||||
axi::cr_ace<bus_cfg, axi::signal_types> cr;
|
||||
axi::cd_ace<bus_cfg, axi::signal_types> cd;
|
||||
|
||||
axi::pin::ace_target<bus_cfg> tgt_bfm{"ace_tgt_bfm"};
|
||||
// target side
|
||||
axi::ace_target_socket<bus_cfg::BUSWIDTH> tgt_ace{"tgt_ace"};
|
||||
axi::axi_target_socket<bus_cfg::BUSWIDTH> tgt_axi{"tgt_axi"};
|
||||
// engines
|
||||
axi::pe::ace_initiator<bus_cfg::BUSWIDTH> intor_pe;
|
||||
axi::pe::simple_target<bus_cfg::BUSWIDTH> axi_tgt_pe;
|
||||
axi::pe::simple_ace_target<bus_cfg::BUSWIDTH> ace_tgt_pe;
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(testbench);
|
||||
testbench()
|
||||
: testbench("testbench") {}
|
||||
testbench(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, intor_pe("ace_intor_pe", intor)
|
||||
, ace_tgt_pe("ace_tgt_pe", tgt_ace)
|
||||
, axi_tgt_pe("axi_tgt_pe", tgt_axi) {
|
||||
|
||||
bw_i.bind(*this);
|
||||
intor_pe.clk_i(clk);
|
||||
intor_bfm.clk_i(clk);
|
||||
tgt_bfm.clk_i(clk);
|
||||
axi_tgt_pe.clk_i(clk);
|
||||
ace_tgt_pe.clk_i(clk);
|
||||
// pe socket to recorder
|
||||
intor(intor_bfm.tsckt);
|
||||
|
||||
// bfm to signals
|
||||
intor_bfm.bind_aw(aw);
|
||||
intor_bfm.bind_w(wdata);
|
||||
intor_bfm.bind_b(b);
|
||||
intor_bfm.bind_ar(ar);
|
||||
intor_bfm.bind_r(rresp);
|
||||
|
||||
intor_bfm.bind_ac(ac);
|
||||
intor_bfm.bind_cr(cr);
|
||||
intor_bfm.bind_cd(cd);
|
||||
|
||||
// signals to bfm
|
||||
tgt_bfm.bind_aw(aw);
|
||||
tgt_bfm.bind_w(wdata);
|
||||
tgt_bfm.bind_b(b);
|
||||
tgt_bfm.bind_ar(ar);
|
||||
tgt_bfm.bind_r(rresp);
|
||||
|
||||
tgt_bfm.bind_ac(ac);
|
||||
tgt_bfm.bind_cr(cr);
|
||||
tgt_bfm.bind_cd(cd);
|
||||
|
||||
// bfm to ace target
|
||||
tgt_bfm.isckt(tgt_ace);
|
||||
ace_tgt_pe.isckt_axi(tgt_axi);
|
||||
// for updating snooop transaction
|
||||
intor_pe.bw_o(bw_i);
|
||||
}
|
||||
|
||||
unsigned transport(tlm::tlm_generic_payload& trans) override {
|
||||
if(transport_cb)
|
||||
return transport_cb(trans);
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
std::function<unsigned(tlm::tlm_generic_payload&)> transport_cb;
|
||||
};
|
||||
|
||||
#endif // _TESTBENCH_H_
|
@ -1,9 +0,0 @@
|
||||
project (ahb_pin_level)
|
||||
|
||||
add_executable(${PROJECT_NAME}
|
||||
bus_test.cpp
|
||||
${test_util_SOURCE_DIR}/sc_main.cpp
|
||||
)
|
||||
target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
|
||||
|
||||
catch_discover_tests(${PROJECT_NAME})
|
@ -1,251 +0,0 @@
|
||||
|
||||
#include "testbench.h"
|
||||
#include <factory.h>
|
||||
#include <tlm/scc/tlm_gp_shared.h>
|
||||
#undef CHECK
|
||||
#include <catch2/catch_all.hpp>
|
||||
#include <unordered_map>
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace ahb;
|
||||
|
||||
factory::add<testbench> tb;
|
||||
bool is_equal(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b) {
|
||||
auto ret = true;
|
||||
ret &= a.get_command() == b.get_command();
|
||||
ret &= a.get_address() == b.get_address();
|
||||
ret &= a.get_data_length() == b.get_data_length();
|
||||
for(auto i = 0u; i < a.get_data_length(); ++i)
|
||||
ret &= a.get_data_ptr()[i] == b.get_data_ptr()[i];
|
||||
// if(a.get_byte_enable_ptr() && b.get_byte_enable_ptr()) {
|
||||
// ret &= a.get_byte_enable_length() == b.get_byte_enable_length();
|
||||
// for(auto i=0u; i<a.get_byte_enable_length(); ++i)
|
||||
// ret &= a.get_byte_enable_ptr()[i] == b.get_byte_enable_ptr()[i];
|
||||
// }
|
||||
ret &= a.get_command() == b.get_command();
|
||||
// if(!ret) SCCWARN()<<"Comparison failed: "<<a<<" and "<<b;
|
||||
return ret;
|
||||
}
|
||||
template <unsigned BUSWIDTH> tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned len, unsigned width) {
|
||||
static unsigned id{0};
|
||||
auto trans = tlm::scc::tlm_mm<>::get().allocate<ahb::ahb_extension>(len);
|
||||
trans->set_address(start_address);
|
||||
tlm::scc::setId(*trans, ++id);
|
||||
auto ext = trans->get_extension<ahb::ahb_extension>();
|
||||
trans->set_data_length(len);
|
||||
trans->set_streaming_width(len);
|
||||
ext->set_burst(ahb::burst_e::INCR);
|
||||
return trans;
|
||||
}
|
||||
|
||||
inline void randomize(tlm::tlm_generic_payload& gp) {
|
||||
static uint8_t req_cnt{0};
|
||||
for(size_t i = 0; i < gp.get_data_length(); ++i) {
|
||||
*(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
|
||||
}
|
||||
req_cnt++;
|
||||
}
|
||||
|
||||
template <typename STATE> unsigned run_scenario(STATE& state, unsigned wait_states = 0) {
|
||||
auto& dut = factory::get<testbench>();
|
||||
dut.tsck.register_b_transport([&state, wait_states](tlm::tlm_base_protocol_types::tlm_payload_type& trans, sc_core::sc_time& d) {
|
||||
if(trans.is_read()) {
|
||||
for(size_t i = 0; i < trans.get_data_length(); ++i) {
|
||||
*(trans.get_data_ptr() + i) = i % 2 ? i : (state.resp_cnt + 128);
|
||||
}
|
||||
state.read_tx.second.emplace_back(&trans);
|
||||
}
|
||||
if(trans.is_write())
|
||||
state.write_tx.second.emplace_back(&trans);
|
||||
SCCDEBUG(__FUNCTION__) << "RX: " << trans;
|
||||
for(unsigned i = 0; i < wait_states; ++i)
|
||||
sc_core::wait(factory::get<testbench>().clk.posedge_event());
|
||||
state.resp_cnt++;
|
||||
return 0;
|
||||
});
|
||||
|
||||
dut.rst_n.write(false);
|
||||
sc_start(state.ResetCycles * dut.clk.period());
|
||||
dut.rst_n.write(true);
|
||||
sc_start(dut.clk.period());
|
||||
dut.HSEL.write(true);
|
||||
sc_start(dut.clk.period());
|
||||
|
||||
auto run1 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x0};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
SCCDEBUG(__FUNCTION__) << "task run1, iteration " << i << " TX: " << *trans;
|
||||
sc_core::sc_time d;
|
||||
dut.isck->b_transport(*trans, d);
|
||||
state.read_tx.first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
SCCDEBUG(__FUNCTION__) << "task run1 finished";
|
||||
});
|
||||
auto run2 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x2000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
SCCDEBUG(__FUNCTION__) << "task run2, iteration " << i << " TX: " << *trans;
|
||||
sc_core::sc_time d;
|
||||
dut.isck->b_transport(*trans, d);
|
||||
state.write_tx.first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
SCCDEBUG(__FUNCTION__) << "task run2 finished";
|
||||
});
|
||||
auto run3 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x1000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
SCCDEBUG(__FUNCTION__) << "task run3, iteration " << i << " TX: " << *trans;
|
||||
sc_core::sc_time d;
|
||||
dut.isck->b_transport(*trans, d);
|
||||
state.read_tx.first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
SCCDEBUG(__FUNCTION__) << "task run3 finished";
|
||||
});
|
||||
auto run4 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x3000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans = prepare_trans<testbench::DWIDTH>(StartAddr, state.BurstLengthByte, state.BurstSizeBytes);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
SCCDEBUG(__FUNCTION__) << "task run4, iteration " << i << " TX: " << *trans;
|
||||
sc_core::sc_time d;
|
||||
dut.isck->b_transport(*trans, d);
|
||||
state.write_tx.first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
SCCDEBUG(__FUNCTION__) << "task run4 finished";
|
||||
});
|
||||
|
||||
unsigned cycles{0};
|
||||
while(cycles < 1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())) {
|
||||
sc_start(10 * dut.clk.period());
|
||||
cycles += 10;
|
||||
}
|
||||
return cycles;
|
||||
}
|
||||
|
||||
TEST_CASE("ahb_read_write", "[AHB][pin-level]") {
|
||||
struct {
|
||||
unsigned int ResetCycles{4};
|
||||
unsigned int BurstLengthByte{4};
|
||||
unsigned int BurstSizeBytes{4};
|
||||
unsigned int NumberOfIterations{1};
|
||||
std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> read_tx;
|
||||
std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> write_tx;
|
||||
unsigned resp_cnt{0};
|
||||
} state;
|
||||
|
||||
auto cycles = run_scenario(state);
|
||||
|
||||
REQUIRE(cycles < 1000);
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
|
||||
REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
|
||||
{
|
||||
auto& e = state.write_tx;
|
||||
auto const& send_tx = e.first;
|
||||
auto const& recv_tx = e.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
{
|
||||
auto& e = state.read_tx;
|
||||
auto const& send_tx = e.first;
|
||||
auto const& recv_tx = e.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ahb_narrow_read_write", "[AHB][pin-level]") {
|
||||
struct {
|
||||
unsigned int ResetCycles{4};
|
||||
unsigned int BurstLengthByte{1};
|
||||
unsigned int BurstSizeBytes{1};
|
||||
unsigned int NumberOfIterations{8};
|
||||
std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> read_tx;
|
||||
std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> write_tx;
|
||||
unsigned resp_cnt{0};
|
||||
} state;
|
||||
|
||||
auto cycles = run_scenario(state);
|
||||
|
||||
REQUIRE(cycles < 1000);
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
|
||||
REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
|
||||
{
|
||||
auto& e = state.write_tx;
|
||||
auto const& send_tx = e.first;
|
||||
auto const& recv_tx = e.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i)
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
{
|
||||
auto& e = state.read_tx;
|
||||
auto const& send_tx = e.first;
|
||||
auto const& recv_tx = e.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i)
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("ahb_delayed_read_write", "[AHB][pin-level]") {
|
||||
struct {
|
||||
unsigned int ResetCycles{4};
|
||||
unsigned int BurstLengthByte{4};
|
||||
unsigned int BurstSizeBytes{4};
|
||||
unsigned int NumberOfIterations{2};
|
||||
std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> read_tx;
|
||||
std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>> write_tx;
|
||||
unsigned resp_cnt{0};
|
||||
} state;
|
||||
|
||||
auto cycles = run_scenario(state, 1);
|
||||
|
||||
REQUIRE(cycles < 1000);
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
|
||||
REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
|
||||
{
|
||||
auto& e = state.write_tx;
|
||||
auto const& send_tx = e.first;
|
||||
auto const& recv_tx = e.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
{
|
||||
auto& e = state.read_tx;
|
||||
auto const& send_tx = e.first;
|
||||
auto const& recv_tx = e.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
}
|
@ -1,78 +0,0 @@
|
||||
#ifndef _TESTBENCH_H_
|
||||
#define _TESTBENCH_H_
|
||||
|
||||
#include <ahb/pin/initiator.h>
|
||||
#include <ahb/pin/target.h>
|
||||
#include <scc.h>
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
class testbench : public sc_core::sc_module {
|
||||
public:
|
||||
enum { DWIDTH = 32 };
|
||||
sc_core::sc_time clk_period{10, sc_core::SC_NS};
|
||||
sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};
|
||||
sc_core::sc_signal<bool> rst_n{"rst_n"};
|
||||
// initiator side
|
||||
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<DWIDTH>> isck{"isck"};
|
||||
ahb::pin::initiator<DWIDTH> intor_bfm{"intor_bfm"};
|
||||
// signal accurate bus
|
||||
sc_core::sc_signal<sc_dt::sc_uint<32>> HADDR{"HADDR"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<3>> HBURST{"HBURST"};
|
||||
sc_core::sc_signal<bool> HMASTLOCK{"HMASTLOCK"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<4>> HPROT{"HPROT"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<3>> HSIZE{"HSIZE"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<2>> HTRANS{"HTRANS"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<DWIDTH>> HWDATA{"HWDATA"};
|
||||
sc_core::sc_signal<bool> HWRITE{"HWRITE"};
|
||||
sc_core::sc_signal<sc_dt::sc_uint<DWIDTH>> HRDATA{"HRDATA"};
|
||||
sc_core::sc_signal<bool> HREADY{"HREADY"};
|
||||
sc_core::sc_signal<bool> HRESP{"HRESP"};
|
||||
sc_core::sc_signal<bool> HSEL{"HSEL"};
|
||||
// target side
|
||||
ahb::pin::target<DWIDTH, 32> tgt_bfm{"tgt_bfm"};
|
||||
tlm::scc::target_mixin<tlm::tlm_target_socket<scc::LT>> tsck{"tsck"};
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(testbench);
|
||||
testbench()
|
||||
: testbench("testbench") {}
|
||||
testbench(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm) {
|
||||
intor_bfm.HCLK_i(clk);
|
||||
tgt_bfm.HCLK_i(clk);
|
||||
// bfm to signals
|
||||
isck(intor_bfm.tsckt);
|
||||
intor_bfm.HRESETn_i(rst_n);
|
||||
intor_bfm.HADDR_o(HADDR);
|
||||
intor_bfm.HBURST_o(HBURST);
|
||||
intor_bfm.HMASTLOCK_o(HMASTLOCK);
|
||||
intor_bfm.HPROT_o(HPROT);
|
||||
intor_bfm.HSIZE_o(HSIZE);
|
||||
intor_bfm.HTRANS_o(HTRANS);
|
||||
intor_bfm.HWDATA_o(HWDATA);
|
||||
intor_bfm.HWRITE_o(HWRITE);
|
||||
intor_bfm.HRDATA_i(HRDATA);
|
||||
intor_bfm.HREADY_i(HREADY);
|
||||
intor_bfm.HRESP_i(HRESP);
|
||||
// signals to bfm
|
||||
tgt_bfm.HRESETn_i(rst_n);
|
||||
tgt_bfm.HADDR_i(HADDR);
|
||||
tgt_bfm.HBURST_i(HBURST);
|
||||
tgt_bfm.HMASTLOCK_i(HMASTLOCK);
|
||||
tgt_bfm.HPROT_i(HPROT);
|
||||
tgt_bfm.HSIZE_i(HSIZE);
|
||||
tgt_bfm.HTRANS_i(HTRANS);
|
||||
tgt_bfm.HWDATA_i(HWDATA);
|
||||
tgt_bfm.HWRITE_i(HWRITE);
|
||||
tgt_bfm.HSEL_i(HSEL);
|
||||
tgt_bfm.HRDATA_o(HRDATA);
|
||||
tgt_bfm.HREADY_o(HREADY);
|
||||
tgt_bfm.HRESP_o(HRESP);
|
||||
tgt_bfm.isckt(tsck);
|
||||
}
|
||||
|
||||
void run1() {}
|
||||
};
|
||||
|
||||
#endif // _TESTBENCH_H_
|
@ -1,9 +0,0 @@
|
||||
project (axi4_pin_level)
|
||||
|
||||
add_executable(${PROJECT_NAME}
|
||||
narrow_burst_test.cpp
|
||||
${test_util_SOURCE_DIR}/sc_main.cpp
|
||||
)
|
||||
target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
|
||||
|
||||
catch_discover_tests(${PROJECT_NAME})
|
@ -1,233 +0,0 @@
|
||||
|
||||
#include "testbench.h"
|
||||
#include <factory.h>
|
||||
#include <tlm/scc/tlm_gp_shared.h>
|
||||
#undef CHECK
|
||||
#include <catch2/catch_all.hpp>
|
||||
#include <unordered_map>
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
factory::add<testbench> tb;
|
||||
|
||||
bool is_equal(tlm::tlm_generic_payload const& a, tlm::tlm_generic_payload const& b) {
|
||||
auto ret = true;
|
||||
ret &= a.get_command() == b.get_command();
|
||||
ret &= a.get_address() == b.get_address();
|
||||
ret &= a.get_data_length() == b.get_data_length();
|
||||
for(auto i = 0u; i < a.get_data_length(); ++i)
|
||||
ret &= a.get_data_ptr()[i] == b.get_data_ptr()[i];
|
||||
// if(a.get_byte_enable_ptr() && b.get_byte_enable_ptr()) {
|
||||
// ret &= a.get_byte_enable_length() == b.get_byte_enable_length();
|
||||
// for(auto i=0u; i<a.get_byte_enable_length(); ++i)
|
||||
// ret &= a.get_byte_enable_ptr()[i] == b.get_byte_enable_ptr()[i];
|
||||
// }
|
||||
ret &= a.get_command() == b.get_command();
|
||||
// if(!ret) SCCWARN()<<"Comparison failed: "<<a<<" and "<<b;
|
||||
return ret;
|
||||
}
|
||||
|
||||
template <typename bus_cfg>
|
||||
tlm::tlm_generic_payload* prepare_trans(uint64_t start_address, unsigned addr_incr, unsigned len, unsigned width, unsigned id) {
|
||||
auto trans = tlm::scc::tlm_mm<>::get().allocate<axi::axi4_extension>(len);
|
||||
trans->set_address(start_address);
|
||||
tlm::scc::setId(*trans, id);
|
||||
auto ext = trans->get_extension<axi::axi4_extension>();
|
||||
trans->set_data_length(len);
|
||||
trans->set_streaming_width(len);
|
||||
ext->set_size(scc::ilog2(width));
|
||||
sc_assert(len < (bus_cfg::BUSWIDTH / 8) || len % (bus_cfg::BUSWIDTH / 8) == 0);
|
||||
auto length = (len * 8 - 1) / (8 * width);
|
||||
if(width == (bus_cfg::BUSWIDTH / 8) && start_address % (bus_cfg::BUSWIDTH / 8))
|
||||
length++;
|
||||
ext->set_length(length);
|
||||
// ext->set_burst(len * 8 > bus_cfg::buswidth ? axi::burst_e::INCR : axi::burst_e::FIXED);
|
||||
ext->set_burst(axi::burst_e::INCR);
|
||||
ext->set_id(id);
|
||||
return trans;
|
||||
}
|
||||
|
||||
inline void randomize(tlm::tlm_generic_payload& gp) {
|
||||
static uint8_t req_cnt{0};
|
||||
for(size_t i = 0; i < gp.get_data_length(); ++i) {
|
||||
*(gp.get_data_ptr() + i) = i % 2 ? i : req_cnt;
|
||||
}
|
||||
req_cnt++;
|
||||
}
|
||||
|
||||
template <typename STATE> unsigned run_scenario(STATE& state) {
|
||||
auto& dut = factory::get<testbench>();
|
||||
dut.tgt_pe.set_operation_cb([&state](axi::axi_protocol_types::tlm_payload_type& trans) -> unsigned {
|
||||
auto id = axi::get_axi_id(trans);
|
||||
if(trans.is_read()) {
|
||||
for(size_t i = 0; i < trans.get_data_length(); ++i) {
|
||||
*(trans.get_data_ptr() + i) = i % 2 ? i : (state.resp_cnt + 128);
|
||||
}
|
||||
state.read_tx[id].second.emplace_back(&trans);
|
||||
}
|
||||
if(trans.is_write())
|
||||
state.write_tx[id].second.emplace_back(&trans);
|
||||
SCCDEBUG(__FUNCTION__) << "RX: " << trans;
|
||||
state.resp_cnt++;
|
||||
return 0;
|
||||
});
|
||||
|
||||
dut.rst.write(false);
|
||||
sc_start(state.ResetCycles * dut.clk.period());
|
||||
dut.rst.write(true);
|
||||
sc_start(dut.clk.period());
|
||||
|
||||
auto run1 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x0};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 1);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
SCCDEBUG(__FUNCTION__) << "run1, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
auto run2 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x2000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 2);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
SCCDEBUG(__FUNCTION__) << "run2, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
auto run3 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x1000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 3);
|
||||
trans->set_command(tlm::TLM_READ_COMMAND);
|
||||
SCCDEBUG(__FUNCTION__) << "run3, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.read_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
auto run4 = sc_spawn([&dut, &state]() {
|
||||
unsigned int StartAddr{0x3000};
|
||||
for(int i = 0; i < state.NumberOfIterations; ++i) {
|
||||
tlm::scc::tlm_gp_shared_ptr trans =
|
||||
prepare_trans<testbench::bus_cfg>(StartAddr, 4, state.BurstLengthByte, state.BurstSizeBytes, 4);
|
||||
trans->set_command(tlm::TLM_WRITE_COMMAND);
|
||||
randomize(*trans);
|
||||
SCCDEBUG(__FUNCTION__) << "run4, iteration " << i << " TX: " << *trans;
|
||||
dut.intor_pe.transport(*trans, false);
|
||||
state.write_tx[axi::get_axi_id(*trans)].first.emplace_back(trans);
|
||||
StartAddr += state.BurstSizeBytes;
|
||||
}
|
||||
});
|
||||
|
||||
unsigned cycles{0};
|
||||
while(cycles < 1000 && !(run1.terminated() && run2.terminated() && run3.terminated() && run4.terminated())) {
|
||||
sc_start(10 * dut.clk.period());
|
||||
cycles += 10;
|
||||
}
|
||||
return cycles;
|
||||
}
|
||||
|
||||
void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
|
||||
struct {
|
||||
unsigned int ResetCycles{4};
|
||||
unsigned int BurstLengthByte{16};
|
||||
unsigned int BurstSizeBytes{8};
|
||||
unsigned int NumberOfIterations{8};
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
|
||||
write_tx;
|
||||
unsigned resp_cnt{0};
|
||||
} state;
|
||||
|
||||
auto& dut = factory::get<testbench>();
|
||||
dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
|
||||
dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
|
||||
auto cycles = run_scenario(state);
|
||||
|
||||
REQUIRE(cycles < 1000);
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
|
||||
REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
|
||||
for(auto& e : state.write_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
for(auto& e : state.read_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i) {
|
||||
REQUIRE(send_tx[i]->get_response_status() == tlm::TLM_OK_RESPONSE);
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
|
||||
struct {
|
||||
unsigned int ResetCycles{4};
|
||||
unsigned int BurstLengthByte{16};
|
||||
unsigned int BurstSizeBytes{4};
|
||||
unsigned int NumberOfIterations{8};
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>> read_tx;
|
||||
std::unordered_map<unsigned, std::pair<std::vector<tlm::scc::tlm_gp_shared_ptr>, std::vector<tlm::scc::tlm_gp_shared_ptr>>>
|
||||
write_tx;
|
||||
unsigned resp_cnt{0};
|
||||
} state;
|
||||
|
||||
auto& dut = factory::get<testbench>();
|
||||
dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
|
||||
dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
|
||||
auto cycles = run_scenario(state);
|
||||
|
||||
REQUIRE(cycles < 1000);
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
|
||||
REQUIRE(state.resp_cnt == 4 * state.NumberOfIterations);
|
||||
for(auto& e : state.write_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i)
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
for(auto& e : state.read_tx) {
|
||||
auto const& send_tx = e.second.first;
|
||||
auto const& recv_tx = e.second.second;
|
||||
REQUIRE(send_tx.size() == recv_tx.size());
|
||||
for(auto i = 0; i < send_tx.size(); ++i)
|
||||
CHECK(is_equal(*send_tx[i], *recv_tx[i]));
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("axi4_burst_alignment", "[AXI][pin-level]") { axi4_burst_alignment(false, false); }
|
||||
|
||||
TEST_CASE("axi4_narrow_burst", "[AXI][pin-level]") { axi4_narrow_burst(false, false); }
|
||||
|
||||
TEST_CASE("axi4_burst_alignment_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(false, true); }
|
||||
|
||||
TEST_CASE("axi4_narrow_burst_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(false, true); }
|
||||
|
||||
TEST_CASE("axi4_burst_alignment_pipelined_write", "[AXI][pin-level]") { axi4_burst_alignment(true, false); }
|
||||
|
||||
TEST_CASE("axi4_narrow_burst_pipelined_write", "[AXI][pin-level]") { axi4_narrow_burst(true, false); }
|
||||
|
||||
TEST_CASE("axi4_burst_alignment_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_burst_alignment(true, true); }
|
||||
|
||||
TEST_CASE("axi4_narrow_burst_pipelined_write_with_bp", "[AXI][pin-level]") { axi4_narrow_burst(true, true); }
|
@ -1,77 +0,0 @@
|
||||
#ifndef _TESTBENCH_H_
|
||||
#define _TESTBENCH_H_
|
||||
|
||||
#include <axi/pe/axi_initiator.h>
|
||||
#include <axi/pe/simple_target.h>
|
||||
#include <axi/pin/axi4_initiator.h>
|
||||
#include <axi/pin/axi4_target.h>
|
||||
#include <axi/scv/recorder_modules.h>
|
||||
#include <scc.h>
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace axi;
|
||||
using namespace axi::pe;
|
||||
|
||||
class testbench : public sc_core::sc_module {
|
||||
public:
|
||||
using bus_cfg = axi::axi4_cfg</*BUSWIDTH=*/64, /*ADDRWIDTH=*/32, /*IDWIDTH=*/4, /*USERWIDTH=*/1>;
|
||||
|
||||
sc_core::sc_time clk_period{10, sc_core::SC_NS};
|
||||
sc_core::sc_clock clk{"clk", clk_period, 0.5, sc_core::SC_ZERO_TIME, true};
|
||||
sc_core::sc_signal<bool> rst{"rst"};
|
||||
// initiator side
|
||||
axi::axi_initiator_socket<bus_cfg::BUSWIDTH> intor{"intor"};
|
||||
axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> intor_rec{"intor_rec"};
|
||||
axi::pin::axi4_initiator<bus_cfg> intor_bfm{"intor_bfm"};
|
||||
// signal accurate bus
|
||||
axi::aw_axi<bus_cfg, axi::signal_types> aw;
|
||||
axi::wdata_axi<bus_cfg, axi::signal_types> wdata;
|
||||
axi::b_axi<bus_cfg, axi::signal_types> b;
|
||||
axi::ar_axi<bus_cfg, axi::signal_types> ar;
|
||||
axi::rresp_axi<bus_cfg, axi::signal_types> rresp;
|
||||
axi::pin::axi4_target<bus_cfg> tgt_bfm{"tgt_bfm"};
|
||||
// target side
|
||||
axi::scv::axi_recorder_module<bus_cfg::BUSWIDTH> tgt_rec{"tgt_rec"};
|
||||
axi::axi_target_socket<bus_cfg::BUSWIDTH> tgt{"tgt"};
|
||||
// engines
|
||||
axi::pe::axi_initiator<bus_cfg::BUSWIDTH> intor_pe;
|
||||
axi::pe::simple_target<bus_cfg::BUSWIDTH> tgt_pe;
|
||||
|
||||
public:
|
||||
SC_HAS_PROCESS(testbench);
|
||||
testbench()
|
||||
: testbench("testbench") {}
|
||||
testbench(sc_core::sc_module_name nm)
|
||||
: sc_core::sc_module(nm)
|
||||
, intor_pe("intor_pe", intor)
|
||||
, tgt_pe("tgt_pe", tgt) {
|
||||
intor_pe.clk_i(clk);
|
||||
intor_bfm.clk_i(clk);
|
||||
tgt_bfm.clk_i(clk);
|
||||
tgt_pe.clk_i(clk);
|
||||
// pe socket to recorder
|
||||
intor(intor_rec.tsckt);
|
||||
// recorder to bfm
|
||||
intor_rec.isckt(intor_bfm.tsckt);
|
||||
// bfm to signals
|
||||
intor_bfm.bind_aw(aw);
|
||||
intor_bfm.bind_w(wdata);
|
||||
intor_bfm.bind_b(b);
|
||||
intor_bfm.bind_ar(ar);
|
||||
intor_bfm.bind_r(rresp);
|
||||
// signals to bfm
|
||||
tgt_bfm.bind_aw(aw);
|
||||
tgt_bfm.bind_w(wdata);
|
||||
tgt_bfm.bind_b(b);
|
||||
tgt_bfm.bind_ar(ar);
|
||||
tgt_bfm.bind_r(rresp);
|
||||
// bfm to recorder
|
||||
tgt_bfm.isckt(tgt_rec.tsckt);
|
||||
// recorder to target
|
||||
tgt_rec.isckt(tgt);
|
||||
}
|
||||
|
||||
void run1() {}
|
||||
};
|
||||
|
||||
#endif // _TESTBENCH_H_
|
@ -1,9 +0,0 @@
|
||||
project (cci_param_restricted)
|
||||
|
||||
add_executable(${PROJECT_NAME}
|
||||
test.cpp
|
||||
${test_util_SOURCE_DIR}/sc_main.cpp
|
||||
)
|
||||
target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
|
||||
|
||||
catch_discover_tests(${PROJECT_NAME})
|
@ -1,145 +0,0 @@
|
||||
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#include <sysc/kernel/sc_simcontext.h>
|
||||
#endif
|
||||
#include <catch2/catch_all.hpp>
|
||||
#include <factory.h>
|
||||
#include <scc/cci_param_restricted.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <systemc>
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
struct top : public sc_core::sc_module {
|
||||
top()
|
||||
: top("top") {}
|
||||
top(sc_module_name const& nm)
|
||||
: sc_core::sc_module(nm) {}
|
||||
|
||||
scc::cci_param_restricted<int> param1{"param1", 5, scc::min_max_restriction(0, 10), "This is parameter 1"};
|
||||
scc::cci_param_restricted<int> param2{"param2", 5, scc::min_max_excl_restriction(0, 10), "This is parameter 3"};
|
||||
scc::cci_param_restricted<int> param3{"param3", 10, scc::min_restriction(0), "This is parameter 2"};
|
||||
scc::cci_param_restricted<int> param4{"param4", 10, scc::min_excl_restriction(0), "This is parameter 4"};
|
||||
scc::cci_param_restricted<int> param5{"param5", 1, scc::max_restriction(10), "This is parameter 5"};
|
||||
scc::cci_param_restricted<int> param6{"param6", 1, scc::max_excl_restriction(10), "This is parameter 6"};
|
||||
scc::cci_param_restricted<int> param7{"param7", 4, scc::discrete_restriction({1, 2, 4, 8, 16}), "This is parameter 7"};
|
||||
std::array<int, 5> values_arr{1, 2, 4, 8, 16};
|
||||
scc::cci_param_restricted<int> param8{"param8", 4, scc::discrete_restriction(values_arr), "This is parameter 8"};
|
||||
std::vector<int> values_vec{1, 2, 4, 8, 16};
|
||||
scc::cci_param_restricted<int> param9{"param9", 4, scc::discrete_restriction(values_vec), "This is parameter 9"};
|
||||
};
|
||||
|
||||
factory::add<top> tb;
|
||||
|
||||
TEST_CASE("simple cci_param_restricted min_max test", "[SCC][cci_param_restricted]") {
|
||||
sc_report_handler::set_actions(SC_ERROR, SC_LOG | SC_CACHE_REPORT | SC_DISPLAY | SC_DO_NOTHING);
|
||||
auto& dut = factory::get<top>();
|
||||
auto run1 = sc_spawn([&dut]() {
|
||||
sc_core::wait(1_ns);
|
||||
for(auto i : {0, 5, 10, -1, 11}) {
|
||||
dut.param1.set_value(i);
|
||||
sc_core::wait(1_ns);
|
||||
}
|
||||
});
|
||||
|
||||
sc_start(10_ns);
|
||||
REQUIRE(run1.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 2);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
sc_report_handler::initialize();
|
||||
auto run2 = sc_spawn([&dut]() {
|
||||
sc_core::wait(1_ns);
|
||||
for(auto i : {0, 5, 10, -1, 11}) {
|
||||
dut.param2.set_value(i);
|
||||
sc_core::wait(1_ns);
|
||||
}
|
||||
});
|
||||
|
||||
sc_start(10_ns);
|
||||
REQUIRE(run2.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 4);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
sc_report_handler::initialize();
|
||||
}
|
||||
|
||||
TEST_CASE("simple cci_param_restricted min test", "[SCC][cci_param_restricted]") {
|
||||
sc_report_handler::set_actions(SC_ERROR, SC_LOG | SC_CACHE_REPORT | SC_DISPLAY | SC_DO_NOTHING);
|
||||
auto& dut = factory::get<top>();
|
||||
auto run1 = sc_spawn([&dut]() {
|
||||
sc_core::wait(1_ns);
|
||||
for(auto i : {0, 5, -1}) {
|
||||
dut.param3.set_value(i);
|
||||
sc_core::wait(1_ns);
|
||||
}
|
||||
});
|
||||
|
||||
sc_start(10_ns);
|
||||
REQUIRE(run1.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 1);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
sc_report_handler::initialize();
|
||||
auto run2 = sc_spawn([&dut]() {
|
||||
sc_core::wait(1_ns);
|
||||
for(auto i : {0, 5, -1}) {
|
||||
dut.param4.set_value(i);
|
||||
sc_core::wait(1_ns);
|
||||
}
|
||||
});
|
||||
|
||||
sc_start(10_ns);
|
||||
REQUIRE(run2.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 2);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
sc_report_handler::initialize();
|
||||
}
|
||||
|
||||
TEST_CASE("simple cci_param_restricted max test", "[SCC][cci_param_restricted]") {
|
||||
sc_report_handler::set_actions(SC_ERROR, SC_LOG | SC_CACHE_REPORT | SC_DISPLAY | SC_DO_NOTHING);
|
||||
auto& dut = factory::get<top>();
|
||||
auto run1 = sc_spawn([&dut]() {
|
||||
sc_core::wait(1_ns);
|
||||
for(auto i : {0, 10, 11}) {
|
||||
dut.param5.set_value(i);
|
||||
sc_core::wait(1_ns);
|
||||
}
|
||||
});
|
||||
|
||||
sc_start(10_ns);
|
||||
REQUIRE(run1.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 1);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
sc_report_handler::initialize();
|
||||
auto run2 = sc_spawn([&dut]() {
|
||||
sc_core::wait(1_ns);
|
||||
for(auto i : {0, 10, 11}) {
|
||||
dut.param6.set_value(i);
|
||||
sc_core::wait(1_ns);
|
||||
}
|
||||
});
|
||||
|
||||
sc_start(10_ns);
|
||||
REQUIRE(run2.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 2);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
sc_report_handler::initialize();
|
||||
}
|
||||
|
||||
TEST_CASE("simple cci_param_restricted discrete test", "[SCC][cci_param_restricted]") {
|
||||
sc_report_handler::set_actions(SC_ERROR, SC_LOG | SC_CACHE_REPORT | SC_DISPLAY | SC_DO_NOTHING);
|
||||
auto& dut = factory::get<top>();
|
||||
auto run1 = sc_spawn([&dut]() {
|
||||
sc_core::wait(1_ns);
|
||||
for(auto i : {4, 10}) {
|
||||
dut.param7.set_value(i);
|
||||
dut.param8.set_value(i);
|
||||
dut.param9.set_value(i);
|
||||
sc_core::wait(1_ns);
|
||||
}
|
||||
});
|
||||
|
||||
sc_start(10_ns);
|
||||
REQUIRE(run1.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 3);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 0);
|
||||
sc_report_handler::initialize();
|
||||
}
|
@ -1,5 +0,0 @@
|
||||
add_executable (cci-example
|
||||
sc_main.cpp
|
||||
)
|
||||
target_link_libraries (cci-example LINK_PUBLIC scc-sysc)
|
||||
add_test(NAME cci-example_test COMMAND cci-example)
|
@ -1,139 +0,0 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
|
||||
more contributor license agreements. See the NOTICE file distributed
|
||||
with this work for additional information regarding copyright ownership.
|
||||
Accellera licenses this file to you under the Apache License, Version 2.0
|
||||
(the "License"); you may not use this file except in compliance with the
|
||||
License. You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied. See the License for the specific language governing
|
||||
permissions and limitations under the License.
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file initiator.h
|
||||
* @brief initiator module implementation.
|
||||
* This file declares and implements the functionality of the initiator.
|
||||
* Few of the parameters of the initiator sc_module are configured by the
|
||||
* router sc_module
|
||||
* @author P V S Phaneendra, CircuitSutra Technologies <pvs@circuitsutra.com>
|
||||
* Parvinder Pal Singh, CircuitSutra Technologies <parvinder@circuitsutra.com>
|
||||
* @date 29th April, 2011 (Friday)
|
||||
*/
|
||||
|
||||
#ifndef EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_INITIATOR_H_
|
||||
#define EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_INITIATOR_H_
|
||||
|
||||
#include <cci_configuration>
|
||||
#include <scc/report.h>
|
||||
#include <string>
|
||||
#include <tlm>
|
||||
#include <tlm_utils/simple_initiator_socket.h>
|
||||
|
||||
/**
|
||||
* @class initiator
|
||||
* @brief The implementation of the initiator module with tlm2 socket for communication
|
||||
* @return void
|
||||
*/
|
||||
SC_MODULE(initiator) {
|
||||
public:
|
||||
int data;
|
||||
|
||||
tlm_utils::simple_initiator_socket<initiator, 32> initiator_socket; ///< Instance of TLM2 simple initiator socket
|
||||
|
||||
/**
|
||||
* @fn initiator
|
||||
* @brief The class constructor
|
||||
* @return void
|
||||
*/
|
||||
SC_CTOR(initiator)
|
||||
: data(0)
|
||||
, initiator_socket("initiator_socket")
|
||||
, initiator_ID("initiator_ID", "initiator_default") {
|
||||
SCCINFO(SCMOD) << "[" << initiator_ID.get_value() << " C_TOR] ------- [INITIATOR CONSTRUCTOR BEGINS HERE] --------";
|
||||
|
||||
// initiator's SC_THREAD declaration
|
||||
SC_THREAD(run_initiator);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn void run_initiator(void)
|
||||
* @brief Main function to send transactions
|
||||
* @return void
|
||||
*/
|
||||
void run_initiator(void) {
|
||||
tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
|
||||
|
||||
int i = 0;
|
||||
|
||||
static tlm::tlm_command cmds[8] = {tlm::TLM_WRITE_COMMAND, tlm::TLM_READ_COMMAND, tlm::TLM_WRITE_COMMAND, tlm::TLM_READ_COMMAND,
|
||||
tlm::TLM_READ_COMMAND, tlm::TLM_READ_COMMAND, tlm::TLM_WRITE_COMMAND, tlm::TLM_WRITE_COMMAND};
|
||||
while(1) {
|
||||
tlm::tlm_command cmd = cmds[(i >> 2) % 8];
|
||||
// static_cast<tlm::tlm_command>(cmd_dist(rng));
|
||||
|
||||
if(cmd == tlm::TLM_WRITE_COMMAND)
|
||||
data = 0xFF000000 | i;
|
||||
|
||||
trans->set_command(cmd);
|
||||
trans->set_address(i);
|
||||
trans->set_data_ptr(reinterpret_cast<unsigned char*>(&data));
|
||||
trans->set_data_length(4);
|
||||
trans->set_streaming_width(4);
|
||||
trans->set_byte_enable_ptr(0);
|
||||
trans->set_dmi_allowed(false);
|
||||
trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
|
||||
sc_core::sc_time delay = sc_core::sc_time(0, sc_core::SC_NS);
|
||||
|
||||
if(cmd == tlm::TLM_WRITE_COMMAND) {
|
||||
SCCINFO(SCMOD) << "[Initiators Message]=>At address " << std::hex << i << " sending transaction with command = Write"
|
||||
<< ", data=" << std::hex << data << " at time " << sc_core::sc_time_stamp();
|
||||
} else {
|
||||
SCCINFO(SCMOD) << "[Initiators Message]=>At address " << std::hex << i << " sending transaction with command= Read "
|
||||
<< " at time " << sc_core::sc_time_stamp();
|
||||
}
|
||||
|
||||
initiator_socket->b_transport(*trans, delay);
|
||||
|
||||
if(trans->is_response_error())
|
||||
SCCERR(SCMOD) << "TLM_2" << trans->get_response_string().c_str();
|
||||
|
||||
if(delay.to_double() != 0)
|
||||
wait(delay);
|
||||
|
||||
if(cmd == tlm::TLM_WRITE_COMMAND) {
|
||||
SCCINFO(SCMOD) << "[Initiators Message]=>At address " << std::hex << i << " received response of Write transaction "
|
||||
<< " at time " << sc_core::sc_time_stamp();
|
||||
} else {
|
||||
SCCINFO(SCMOD) << "[Initiators Message]=>At address " << std::hex << i << " received response of Read transaction "
|
||||
<< " data " << data << " at time " << sc_core::sc_time_stamp();
|
||||
}
|
||||
|
||||
SCCINFO(SCMOD) << "--------------------------------------------------------";
|
||||
|
||||
wait(5.0, sc_core::SC_NS);
|
||||
|
||||
i = i + 4;
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
cci::cci_param<std::string, cci::CCI_MUTABLE_PARAM>
|
||||
initiator_ID; ///< Elab Time Param for assigning initiator ID (initialized by top_module)
|
||||
/**
|
||||
* @fn void end_of_elaboration()
|
||||
* @brief end of elaboration function to lock structural param
|
||||
* @return void
|
||||
*/
|
||||
void end_of_elaboration() { initiator_ID.lock(); }
|
||||
};
|
||||
// initiator
|
||||
|
||||
#endif // EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_INITIATOR_H_
|
@ -1,179 +0,0 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
|
||||
more contributor license agreements. See the NOTICE file distributed
|
||||
with this work for additional information regarding copyright ownership.
|
||||
Accellera licenses this file to you under the Apache License, Version 2.0
|
||||
(the "License"); you may not use this file except in compliance with the
|
||||
License. You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied. See the License for the specific language governing
|
||||
permissions and limitations under the License.
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file router.h
|
||||
* @brief Definition of the router module.
|
||||
* This file declares and implements the functionality of the router.
|
||||
* Few of the parameters of the target and initiator sc_module(s) are
|
||||
* configured by the router sc_module
|
||||
* @authors P V S Phaneendra, CircuitSutra Technologies <pvs@circuitsutra.com>
|
||||
* @date 29th April, 2011 (Friday)
|
||||
*/
|
||||
|
||||
#ifndef EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_ROUTER_H_
|
||||
#define EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_ROUTER_H_
|
||||
|
||||
#ifdef _MSC_VER
|
||||
#define snprintf _snprintf
|
||||
#endif
|
||||
|
||||
#include <cci_configuration>
|
||||
#include <iomanip>
|
||||
#include <sstream>
|
||||
#include <tlm>
|
||||
#include <vector>
|
||||
|
||||
#include <tlm_utils/multi_passthrough_initiator_socket.h>
|
||||
#include <tlm_utils/multi_passthrough_target_socket.h>
|
||||
|
||||
/**
|
||||
* @class router
|
||||
* @brief Thes module implements a router functionality
|
||||
*/
|
||||
SC_MODULE(router) {
|
||||
public:
|
||||
// Declare tlm multi-passthrough sockets for target and initiator modules
|
||||
tlm_utils::multi_passthrough_target_socket<router, 32> Router_target;
|
||||
tlm_utils::multi_passthrough_initiator_socket<router, 32> Router_initiator;
|
||||
|
||||
/**
|
||||
* @fn router
|
||||
* @brief The class constructor
|
||||
* @return void
|
||||
*/
|
||||
SC_CTOR(router)
|
||||
: Router_target("Router_target")
|
||||
, Router_initiator("Router_initiator")
|
||||
, r_initiators("r_initiators", 0)
|
||||
, r_targets("r_targets", 0)
|
||||
, addr_limit("addr_max", 64)
|
||||
, m_broker(cci::cci_get_broker())
|
||||
, addrSize(0) {
|
||||
SCCINFO(SCMOD) << "[ROUTER C_TOR] ----- [ROUTER CONSTRUCTOR BEGINS HERE] ------";
|
||||
|
||||
// Register b_transport
|
||||
Router_target.register_b_transport(this, &router::b_transport);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn void before_end_of_elaboration(void)
|
||||
* @brief The router table information is filled in during this function
|
||||
* @return void
|
||||
*/
|
||||
void before_end_of_elaboration(void) {
|
||||
SCCINFO(SCMOD) << "[ROUTER in beoe] : Number of initiator(s) : " << r_initiators.get_cci_value().to_json();
|
||||
SCCINFO(SCMOD) << "[ROUTER in beoe] : Number of target(s) : " << r_targets.get_value();
|
||||
SCCINFO(SCMOD) << "[ROUTER in beoe] : Maximum Addressable Limit of the router : " << addr_limit.get_value();
|
||||
|
||||
char targetName[10]; ///< Holds router table's fields' names
|
||||
addrSize = (unsigned int)(addr_limit.get_value() / r_targets);
|
||||
|
||||
// Printing the Router Table contents
|
||||
SCCINFO(SCMOD) << "============= ROUTER TABLE INFORMATION ==============";
|
||||
SCCINFO(SCMOD) << "-----------------------------------------------------";
|
||||
SCCINFO(SCMOD) << "| Target ID | Start Addr | End Addr | Base Addr |";
|
||||
SCCINFO(SCMOD) << "-----------------------------------------------------";
|
||||
|
||||
// Sets the contents of the routing table with (default) values
|
||||
// calculated within 'beoe' phase
|
||||
for(int i = 0; i < r_targets; i++) {
|
||||
snprintf(targetName, sizeof(targetName), "r_index_%d", i);
|
||||
r_target_index.push_back(new cci::cci_param<unsigned int, cci::CCI_IMMUTABLE_PARAM>(targetName, i));
|
||||
|
||||
snprintf(targetName, sizeof(targetName), "r_sa_%d", i);
|
||||
r_addr_start.push_back(new cci::cci_param<unsigned int, cci::CCI_IMMUTABLE_PARAM>(targetName, (i * addrSize)));
|
||||
|
||||
snprintf(targetName, sizeof(targetName), "r_ea_%d", i);
|
||||
r_addr_end.push_back(new cci::cci_param<unsigned int, cci::CCI_IMMUTABLE_PARAM>(targetName, ((i + 1) * addrSize - 1)));
|
||||
}
|
||||
|
||||
for(int i = 0; i < r_targets; i++) {
|
||||
snprintf(stringName, sizeof(stringName), "top_module_inst.target_%d.s_base_addr", i);
|
||||
|
||||
base_handle = m_broker.get_param_handle(stringName);
|
||||
if(!base_handle.is_valid()) {
|
||||
sc_assert(!"target Base Address Handle returned is NULL");
|
||||
}
|
||||
std::stringstream row_ss;
|
||||
row_ss << "| " << std::setw(10) << r_target_index[i]->get_value() << " | " << std::setw(10) << std::hex << std::showbase
|
||||
<< r_addr_start[i]->get_value() << " | " << std::setw(10) << r_addr_end[i]->get_value() << " | " << std::setw(10)
|
||||
<< base_handle.get_cci_value().to_json() << " |";
|
||||
SCCINFO(SCMOD) << row_ss.str().c_str();
|
||||
SCCINFO(SCMOD) << "-----------------------------------------------------";
|
||||
}
|
||||
}
|
||||
|
||||
// Blocking transport implementation of the router
|
||||
void b_transport(int i_, tlm::tlm_generic_payload& trans, sc_core::sc_time& delay) {
|
||||
wait(delay);
|
||||
|
||||
delay = sc_core::SC_ZERO_TIME;
|
||||
|
||||
sc_dt::uint64 addr = trans.get_address();
|
||||
|
||||
if(addr >= static_cast<sc_dt::uint64>(addr_limit.get_value())) {
|
||||
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
|
||||
return;
|
||||
}
|
||||
|
||||
for(unsigned int i = 0; i < r_target_index.size(); i++) {
|
||||
if((addr >= (r_addr_start[i]->get_value())) && (addr <= (r_addr_end[i]->get_value()))) {
|
||||
SCCINFO(SCMOD) << "[Router in 'b_transport' layer]";
|
||||
SCCINFO(SCMOD) << "Address = " << std::hex << addr;
|
||||
SCCINFO(SCMOD) << "Index = " << (r_target_index[i])->get_value();
|
||||
SCCINFO(SCMOD) << "Start addres = " << std::hex << (r_addr_start[i]->get_value());
|
||||
SCCINFO(SCMOD) << "End Address = " << std::hex << (r_addr_end[i]->get_value());
|
||||
Router_initiator[(r_target_index[i])->get_value()]->b_transport(trans, delay);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
/// Demonstrates Model-to-Model Configuration (UC12)
|
||||
/// Elaboration Time Parameters for setting up the model hierarcy;
|
||||
cci::cci_param<int, cci::CCI_MUTABLE_PARAM> r_initiators; ///< initiator ID assigned by the top_module upon instantiation
|
||||
cci::cci_param<int, cci::CCI_MUTABLE_PARAM> r_targets; ///< target ID assigned by the top_module upon instantiation
|
||||
cci::cci_param<unsigned int, cci::CCI_MUTABLE_PARAM> addr_limit; ///< Router Addressing Range
|
||||
cci::cci_broker_handle m_broker; ///< CCI configuration broker handle
|
||||
|
||||
/// Router Table contents holding targets related information
|
||||
std::vector<cci::cci_param<unsigned int, cci::CCI_IMMUTABLE_PARAM>*> r_target_index; ///< Router table target index
|
||||
std::vector<cci::cci_param<unsigned int, cci::CCI_IMMUTABLE_PARAM>*> r_addr_start; ///< Router table start address
|
||||
std::vector<cci::cci_param<unsigned int, cci::CCI_IMMUTABLE_PARAM>*> r_addr_end; ///< Router table end address
|
||||
|
||||
cci::cci_param_handle base_handle; ///< CCI base parameter handle for target base address
|
||||
|
||||
/**
|
||||
* @fn void end_of_elaboration()
|
||||
* @brief end of elaboration function to lock structural param
|
||||
* @return void
|
||||
*/
|
||||
void end_of_elaboration() {
|
||||
r_initiators.lock();
|
||||
r_targets.lock();
|
||||
}
|
||||
|
||||
int addrSize;
|
||||
char stringName[50];
|
||||
};
|
||||
// router
|
||||
|
||||
#endif // EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_ROUTER_H_
|
@ -1,86 +0,0 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
|
||||
more contributor license agreements. See the NOTICE file distributed
|
||||
with this work for additional information regarding copyright ownership.
|
||||
Accellera licenses this file to you under the Apache License, Version 2.0
|
||||
(the "License"); you may not use this file except in compliance with the
|
||||
License. You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied. See the License for the specific language governing
|
||||
permissions and limitations under the License.
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @file main.cpp
|
||||
* @brief Testbench file
|
||||
* This file declares and implements the functionality of the target.
|
||||
* Few of the parameters of the target sc_module are configured by the
|
||||
* router sc_module.
|
||||
* @author P V S Phaneendra, CircuitSutra Technologies <pvs@circuitsutra.com>
|
||||
* @date 29th April, 2011 (Friday)
|
||||
*/
|
||||
|
||||
#include "top_module.h"
|
||||
#include <cci_configuration>
|
||||
#include <cci_utils/broker.h>
|
||||
#include <string>
|
||||
|
||||
/**
|
||||
* @fn int sc_main(int argc, char* argv[])
|
||||
* @brief The testbench for the hierarchical override of parameter values example
|
||||
* @param argc The number of input arguments
|
||||
* @param argv The list of input arguments
|
||||
* @return An integer for the execution status
|
||||
*/
|
||||
int sc_main(int sc_argc, char* sc_argv[]) {
|
||||
scc::init_logging(scc::log::INFO);
|
||||
cci::cci_originator me = cci::cci_originator("sc_main");
|
||||
// Get handle to the default broker
|
||||
cci::cci_broker_handle myGlobalBroker = cci::cci_get_global_broker(me);
|
||||
myGlobalBroker.set_preset_cci_value("top_module_inst.**.log_level", cci::cci_value(3));
|
||||
SCCINFO("sc_main") << "[MAIN] : Setting preset value of the number of initiators to 2";
|
||||
// Set preset value to the number of initiator(s) (within top_module)
|
||||
std::string initiatorHierarchicalName = "top_module_inst.number_of_initiators";
|
||||
myGlobalBroker.set_preset_cci_value(initiatorHierarchicalName, cci::cci_value(2));
|
||||
SCCINFO("sc_main") << "[MAIN] : Setting preset value of the number of initiators to 1";
|
||||
// The program considers only the last set preset value
|
||||
myGlobalBroker.set_preset_cci_value(initiatorHierarchicalName, cci::cci_value(1));
|
||||
SCCINFO("sc_main") << "[MAIN] : Setting preset value of the number of targets to 4";
|
||||
// Set preset value to the number of target(s) (within top_module)
|
||||
std::string targetHierarchicalName = "top_module_inst.number_of_targets";
|
||||
myGlobalBroker.set_preset_cci_value(targetHierarchicalName, cci::cci_value(4));
|
||||
// Set the maximum addressing limit for the router
|
||||
myGlobalBroker.set_preset_cci_value("top_module_inst.RouterInstance.addr_max", cci::cci_value(1024));
|
||||
// Set and lock the Router Table presets values for target_1
|
||||
// These values have again been tried to set within the Top_MODULE
|
||||
// @see top_module.h
|
||||
SCCINFO("sc_main") << "[MAIN] : Set and lock Router Table target_1 contents";
|
||||
myGlobalBroker.set_preset_cci_value("top_module_inst.RouterInstance.r_index_1", cci::cci_value(1));
|
||||
myGlobalBroker.lock_preset_value("top_module_inst.RouterInstance.r_index_1");
|
||||
SCCINFO("sc_main") << "[MAIN] : Set and lock Router Table Start Address for target_1 to 128";
|
||||
myGlobalBroker.set_preset_cci_value("top_module_inst.RouterInstance.r_sa_1", cci::cci_value(128));
|
||||
myGlobalBroker.lock_preset_value("top_module_inst.RouterInstance.r_sa_1");
|
||||
SCCINFO("sc_main") << "[MAIN] : Set and lock Router Table End Address for target_1 to 255";
|
||||
myGlobalBroker.set_preset_cci_value("top_module_inst.RouterInstance.r_ea_1", cci::cci_value(255));
|
||||
myGlobalBroker.lock_preset_value("top_module_inst.RouterInstance.r_ea_1");
|
||||
SCCINFO("sc_main") << "[MAIN] : Instantiate top module after setting preset values to top_module, router and target parameters";
|
||||
// Instantiate TOP_MODULE responsible for creating the model hierarchy
|
||||
top_module top_mod("top_module_inst");
|
||||
// Start the simulation
|
||||
SCCINFO("sc_main") << "Begin Simulation.";
|
||||
sc_core::sc_start(1140, sc_core::SC_NS);
|
||||
SCCINFO("sc_main") << "End Simulation.";
|
||||
|
||||
return EXIT_SUCCESS;
|
||||
} // End of 'sc_main'
|
@ -1,148 +0,0 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
|
||||
more contributor license agreements. See the NOTICE file distributed
|
||||
with this work for additional information regarding copyright ownership.
|
||||
Accellera licenses this file to you under the Apache License, Version 2.0
|
||||
(the "License"); you may not use this file except in compliance with the
|
||||
License. You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied. See the License for the specific language governing
|
||||
permissions and limitations under the License.
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file target.h
|
||||
* @brief target module implementation.
|
||||
* This file declares and implements the functionality of the target.
|
||||
* Few of the parameters of the target sc_module are configured by the
|
||||
* router sc_module
|
||||
* @author P V S Phaneendra, CircuitSutra Technologies <pvs@circuitsutra.com>
|
||||
* Parvinder Pal Singh, CircuitSutra Technologies <parvinder@circuitsutra.com>
|
||||
* @date 5th May, 2011 (Thursday)
|
||||
*/
|
||||
|
||||
#ifndef EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_TARGET_H_
|
||||
#define EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_TARGET_H_
|
||||
|
||||
#include <cci_configuration>
|
||||
#include <scc/report.h>
|
||||
#include <string>
|
||||
#include <tlm>
|
||||
#include <tlm_utils/simple_target_socket.h>
|
||||
|
||||
/**
|
||||
* @class target
|
||||
* @brief This module implementas the functionality of a target IP
|
||||
*/
|
||||
SC_MODULE(target) {
|
||||
public:
|
||||
tlm_utils::simple_target_socket<target, 32> target_socket;
|
||||
sc_core::sc_time read_latency, write_latency;
|
||||
|
||||
SC_CTOR(target)
|
||||
: target_socket("target_socket")
|
||||
, target_ID("target_ID", "target_default")
|
||||
, s_base_addr("s_base_addr", 0)
|
||||
, s_size("s_size", 256) {
|
||||
SCCINFO(SCMOD) << "[" << target_ID.get_value() << " C_TOR] ------- [TARGET CONSTRUCTOR BEGINS HERE] --------";
|
||||
SCCINFO(SCMOD) << "[" << target_ID.get_value() << " C_TOR] : Base Address : " << s_base_addr.get_value();
|
||||
|
||||
// Register b_transport
|
||||
target_socket.register_b_transport(this, &target::b_transport);
|
||||
|
||||
write_latency = sc_core::sc_time(3, sc_core::SC_NS);
|
||||
read_latency = sc_core::sc_time(5, sc_core::SC_NS);
|
||||
|
||||
mem = new int[s_size.get_value()];
|
||||
|
||||
for(unsigned int i = 0; i < s_size.get_value(); i++)
|
||||
mem[i] = 0xAABBCCDD | i;
|
||||
|
||||
// target's SC_THREAD declaration
|
||||
SC_THREAD(run_target);
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn void run_target(void)
|
||||
* @brief The run thread of the modeul (does nothing)
|
||||
* @return void
|
||||
*/
|
||||
void run_target(void) {}
|
||||
|
||||
/**
|
||||
* @fn void b_transport(tlm::tlm_generic_payload& trans, sc_core::sc_time& delay)
|
||||
* @brief Implementation of the blocking transport in the target
|
||||
* @param trans The transaction being sent
|
||||
* @param delay The annotated delay associated with the transaction
|
||||
* @return void
|
||||
*/
|
||||
void b_transport(tlm::tlm_generic_payload & trans, sc_core::sc_time & delay) {
|
||||
tlm::tlm_command cmd = trans.get_command();
|
||||
sc_dt::uint64 adr = trans.get_address() - s_base_addr.get_value();
|
||||
unsigned char* ptr = trans.get_data_ptr();
|
||||
unsigned int len = trans.get_data_length();
|
||||
unsigned char* byt = trans.get_byte_enable_ptr();
|
||||
unsigned int wid = trans.get_streaming_width();
|
||||
|
||||
SCCINFO(SCMOD) << "[TARGET] : adr ---- " << std::hex << adr;
|
||||
SCCINFO(SCMOD) << "[TARGET] : base addr ---- " << std::hex << s_base_addr.get_value();
|
||||
|
||||
// Check for storage address overflow
|
||||
if(adr > s_size.get_value()) {
|
||||
trans.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
|
||||
return;
|
||||
}
|
||||
|
||||
// Target unable to support byte enable attribute
|
||||
if(byt) {
|
||||
trans.set_response_status(tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE);
|
||||
return;
|
||||
}
|
||||
|
||||
// Target unable to support streaming width attribute
|
||||
if(wid < len) {
|
||||
trans.set_response_status(tlm::TLM_BURST_ERROR_RESPONSE);
|
||||
return;
|
||||
}
|
||||
|
||||
if(cmd == tlm::TLM_READ_COMMAND) {
|
||||
memcpy(ptr, &mem[adr], len);
|
||||
delay = delay + read_latency;
|
||||
} else if(cmd == tlm::TLM_WRITE_COMMAND) {
|
||||
memcpy(&mem[adr], ptr, len);
|
||||
delay = delay + write_latency;
|
||||
}
|
||||
|
||||
trans.set_response_status(tlm::TLM_OK_RESPONSE);
|
||||
}
|
||||
|
||||
private:
|
||||
cci::cci_param<std::string, cci::CCI_MUTABLE_PARAM>
|
||||
target_ID; ///< Elaboration Time Param for assigning target ID (initialized by top_module)
|
||||
|
||||
cci::cci_param<int, cci::CCI_MUTABLE_PARAM> s_base_addr; ///< Mutable time param for setting target's base addr (initialized by router)
|
||||
|
||||
cci::cci_param<unsigned int> s_size; ///< Mutable time parameter for setting target's size (initialized by router);
|
||||
|
||||
/**
|
||||
* @fn void end_of_elaboration()
|
||||
* @brief end of elaboration function to lock structural param
|
||||
* @return void
|
||||
*/
|
||||
void end_of_elaboration() {
|
||||
target_ID.lock();
|
||||
s_base_addr.lock();
|
||||
}
|
||||
|
||||
int* mem;
|
||||
};
|
||||
// target
|
||||
|
||||
#endif // EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_TARGET_H_
|
@ -1,224 +0,0 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
|
||||
more contributor license agreements. See the NOTICE file distributed
|
||||
with this work for additional information regarding copyright ownership.
|
||||
Accellera licenses this file to you under the Apache License, Version 2.0
|
||||
(the "License"); you may not use this file except in compliance with the
|
||||
License. You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied. See the License for the specific language governing
|
||||
permissions and limitations under the License.
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
/**
|
||||
* @file top_module.h
|
||||
* @brief Implementation the TOP_MODULE.
|
||||
* This header contains code related to the top module which decides
|
||||
* the model hierarchy for example#9.
|
||||
* @author P V S Phaneendra, CircuitSutra Technologies <pvs@circuitsutra.com>
|
||||
* Girish Verma, CircuitSutra Technologies <girish@circuitsutra.com>
|
||||
* Parvinder Pal Singh, CircuitSutra Technologies <parvinder@circuitsutra.com>
|
||||
* @date 29th April, 2011 (Friday)
|
||||
*/
|
||||
|
||||
#ifndef EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_TOP_MODULE_H_
|
||||
#define EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_TOP_MODULE_H_
|
||||
|
||||
#include <cci_configuration>
|
||||
#include <scc/report.h>
|
||||
#include <sstream>
|
||||
#include <tlm>
|
||||
#include <vector>
|
||||
|
||||
#include "initiator.h"
|
||||
#include "router.h"
|
||||
#include "target.h"
|
||||
|
||||
/**
|
||||
* @class top_module
|
||||
* @brief This module instantiated a initiator, target, and router and binds them correctly for communication.
|
||||
*/
|
||||
SC_MODULE(top_module) {
|
||||
public:
|
||||
/**
|
||||
* @fn top_module
|
||||
* @brief The class constructor
|
||||
*/
|
||||
SC_CTOR(top_module)
|
||||
: n_initiators("number_of_initiators", 0)
|
||||
, n_targets("number_of_targets", 0)
|
||||
, m_broker(cci::cci_get_broker()) {
|
||||
std::stringstream ss;
|
||||
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] -- [TOP MODULE CONSTRUCTOR BEGINS HERE]";
|
||||
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Number of initiators : " << n_initiators.get_value();
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Number of targets : " << n_targets.get_value();
|
||||
|
||||
// Set and lock the number of initiators in Router Table
|
||||
// to value passed from 'sc_main'
|
||||
m_broker.set_preset_cci_value("top_module_inst.RouterInstance.r_initiators", n_initiators.get_cci_value());
|
||||
m_broker.lock_preset_value("top_module_inst.RouterInstance.r_initiators");
|
||||
|
||||
// Set and lock the number of targets in Router Table
|
||||
// to value passed from 'sc_main'
|
||||
m_broker.set_preset_cci_value("top_module_inst.RouterInstance.r_targets", n_targets.get_cci_value());
|
||||
m_broker.lock_preset_value("top_module_inst.RouterInstance.r_targets");
|
||||
|
||||
// Declaring and defining router module
|
||||
char routerName[15] = "RouterInstance";
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Creating Router : " << routerName;
|
||||
routerInstance = new router(routerName);
|
||||
|
||||
// Top_Module begins construction of the model hierarchy from here
|
||||
// ----------------------------------------------------------------
|
||||
|
||||
cci::cci_param_handle r_addr_limit_handle = m_broker.get_param_handle("top_module_inst.RouterInstance.addr_limit");
|
||||
if(r_addr_limit_handle.is_valid()) {
|
||||
r_addr_max = atoi((r_addr_limit_handle.get_cci_value().to_json()).c_str());
|
||||
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Router's maximum addressable limit : " << r_addr_max;
|
||||
}
|
||||
|
||||
/// Creating instances of initiator(s)
|
||||
for(int i = 0; i < n_initiators; i++) {
|
||||
snprintf(initiatorName, sizeof(initiatorName), "initiator_%d", i);
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Creating initiator : " << initiatorName;
|
||||
|
||||
snprintf(stringMisc, sizeof(stringMisc), "%s.%s.initiator_ID", name(), initiatorName);
|
||||
|
||||
snprintf(initiatorName, sizeof(initiatorName), "\"initiator_%d\"", i);
|
||||
m_broker.set_preset_cci_value(stringMisc, cci::cci_value::from_json(initiatorName));
|
||||
snprintf(initiatorName, sizeof(initiatorName), "initiator_%d", i);
|
||||
initiatorList.push_back(new initiator(initiatorName));
|
||||
|
||||
// Binding of initiator to Router
|
||||
SCCINFO(SCMOD) << "[TOP MODULE C_TOR] : Binding Router_Initiator to " << initiatorName;
|
||||
initiatorList[i]->initiator_socket.bind(routerInstance->Router_target);
|
||||
}
|
||||
|
||||
// Defining target size
|
||||
targetSize = 128;
|
||||
|
||||
// Creating instances of target(s)
|
||||
for(int i = 0; i < n_targets; i++) {
|
||||
snprintf(targetName, sizeof(targetName), "target_%d", i);
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Creating target : " << targetName;
|
||||
|
||||
snprintf(stringMisc, sizeof(stringMisc), "%s.%s.target_ID", name(), targetName);
|
||||
snprintf(targetName, sizeof(targetName), "\"target_%d\"", i);
|
||||
m_broker.set_preset_cci_value(stringMisc, cci::cci_value::from_json(targetName));
|
||||
snprintf(targetName, sizeof(targetName), "target_%d", i);
|
||||
|
||||
// Set preset value for maximum target size(memory)
|
||||
snprintf(stringMisc, sizeof(stringMisc), "%s.%s.s_size", name(), targetName);
|
||||
ss.clear();
|
||||
ss.str("");
|
||||
ss << targetSize;
|
||||
|
||||
m_broker.set_preset_cci_value(stringMisc, cci::cci_value::from_json(ss.str()));
|
||||
targetList.push_back(new target(targetName));
|
||||
|
||||
// Binding Router to target
|
||||
SCCINFO(SCMOD) << "[TOP MODULE C_TOR] : Binding Router_Initiator to " << targetName;
|
||||
routerInstance->Router_initiator.bind(targetList[i]->target_socket);
|
||||
}
|
||||
|
||||
// Try re-setting locked values for Router Table contents
|
||||
for(int i = 0; i < n_targets; i++) {
|
||||
snprintf(targetName, sizeof(targetName), "%s.RouterInstance.r_index_%d", name(), i);
|
||||
ss.clear();
|
||||
ss.str("");
|
||||
ss << i;
|
||||
|
||||
try {
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Re-setting fields of target_" << i;
|
||||
m_broker.set_preset_cci_value(targetName, cci::cci_value::from_json(ss.str()));
|
||||
} catch(sc_core::sc_report const& exception) {
|
||||
SCCINFO(SCMOD) << "[ROUTER : Caught] : " << exception.what();
|
||||
}
|
||||
|
||||
snprintf(targetName, sizeof(targetName), "%s.RouterInstance.r_sa_%d", name(), i);
|
||||
ss.clear();
|
||||
ss.str("");
|
||||
ss << (i * targetSize);
|
||||
|
||||
snprintf(targetBaseAddr, sizeof(targetBaseAddr), "%s.target_%d.s_base_addr", name(), i);
|
||||
|
||||
cci::cci_param_untyped_handle h = m_broker.get_param_handle(targetBaseAddr);
|
||||
h.set_cci_value(cci::cci_value::from_json(ss.str()));
|
||||
|
||||
try {
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Re-setting start addr of target_" << i;
|
||||
m_broker.set_preset_cci_value(targetName, cci::cci_value::from_json(ss.str()));
|
||||
} catch(sc_core::sc_report const& exception) {
|
||||
SCCINFO(SCMOD) << "[ROUTER : Caught] : " << exception.what();
|
||||
}
|
||||
|
||||
snprintf(targetName, sizeof(targetName), "%s.RouterInstance.r_ea_%d", name(), i);
|
||||
ss.clear();
|
||||
ss.str("");
|
||||
ss << ((i + 1) * targetSize - 1);
|
||||
|
||||
try {
|
||||
SCCINFO(SCMOD) << "[TOP_MODULE C_TOR] : Re-setting end addr of target_" << i;
|
||||
m_broker.set_preset_cci_value(targetName, cci::cci_value::from_json(ss.str()));
|
||||
} catch(sc_core::sc_report const& exception) {
|
||||
SCCINFO(SCMOD) << "[ROUTER : Caught] : " << exception.what();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @fn ~top_module()
|
||||
* @brief The class destructor
|
||||
* @return void
|
||||
*/
|
||||
~top_module() {
|
||||
if(!initiatorList.empty()) {
|
||||
for(std::vector<initiator*>::iterator it = initiatorList.begin(); it != initiatorList.end(); ++it) {
|
||||
delete(*it);
|
||||
}
|
||||
initiatorList.clear();
|
||||
}
|
||||
|
||||
if(!targetList.empty()) {
|
||||
for(std::vector<target*>::iterator it = targetList.begin(); it != targetList.end(); ++it) {
|
||||
delete(*it);
|
||||
}
|
||||
targetList.clear();
|
||||
}
|
||||
}
|
||||
|
||||
private:
|
||||
// Immutable type cci-parameters
|
||||
cci::cci_param<int, cci::CCI_IMMUTABLE_PARAM> n_initiators; ///< Number of initiators to be instantiated
|
||||
cci::cci_param<int, cci::CCI_IMMUTABLE_PARAM> n_targets; ///< Number of targets to be instantiated
|
||||
|
||||
cci::cci_broker_handle m_broker; ///< Configuration broker handle
|
||||
|
||||
router* routerInstance; ///< Declaration of a router pointer
|
||||
|
||||
// STD::VECTORs for creating instances of initiator and target
|
||||
std::vector<initiator*> initiatorList; ///< STD::VECTOR for initiators
|
||||
std::vector<target*> targetList; ///< STD::VECTOR for targets
|
||||
|
||||
char initiatorName[50]; ///< initiator_ID
|
||||
char targetName[50]; ///< target_ID
|
||||
char stringMisc[50]; ///< String to be used for misc things
|
||||
char targetBaseAddr[50]; ///< The base address of the target
|
||||
|
||||
int addrValue{0}; ///< Address Value
|
||||
int targetSize; ///< Maximum target Size (preset value)
|
||||
int r_addr_max; ///< Maximum Router Table's memory range
|
||||
};
|
||||
// top_module
|
||||
|
||||
#endif // EXAMPLES_EX09_HIERARCHICAL_OVERRIDE_OF_PARAMETER_VALUES_TOP_MODULE_H_
|
@ -1,3 +0,0 @@
|
||||
add_executable (configurer sc_main.cpp)
|
||||
target_link_libraries (configurer LINK_PUBLIC scc-sysc)
|
||||
add_test(NAME configurer_test COMMAND configurer ${CMAKE_CURRENT_SOURCE_DIR}/test.yaml)
|
@ -1,74 +0,0 @@
|
||||
/*****************************************************************************
|
||||
|
||||
Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
|
||||
more contributor license agreements. See the NOTICE file distributed
|
||||
with this work for additional information regarding copyright ownership.
|
||||
Accellera licenses this file to you under the Apache License, Version 2.0
|
||||
(the "License"); you may not use this file except in compliance with the
|
||||
License. You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied. See the License for the specific language governing
|
||||
permissions and limitations under the License.
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @file main.cpp
|
||||
* @brief Testbench file
|
||||
* This file declares and implements the functionality of the target.
|
||||
* Few of the parameters of the target sc_module are configured by the
|
||||
* router sc_module.
|
||||
* @author P V S Phaneendra, CircuitSutra Technologies <pvs@circuitsutra.com>
|
||||
* @date 29th April, 2011 (Friday)
|
||||
*/
|
||||
|
||||
#include <scc/cci_util.h>
|
||||
#include <scc/configurer.h>
|
||||
#include <string>
|
||||
|
||||
DEFINE_ENUM4CCI(trace_lvl, (NONE)(LOW)(MEDIUM)(HIGH)(FULL))
|
||||
DEFINE_NS_ENUM4CCI(test, log_lvl, (NONE)(LOW)(MEDIUM)(HIGH)(FULL))
|
||||
|
||||
/**
|
||||
* @fn int sc_main(int argc, char* argv[])
|
||||
* @brief The testbench for the hierarchical override of parameter values example
|
||||
* @param argc The number of input arguments
|
||||
* @param argv The list of input arguments
|
||||
* @return An integer for the execution status
|
||||
*/
|
||||
int sc_main(int sc_argc, char* sc_argv[]) {
|
||||
scc::init_logging(scc::log::INFO);
|
||||
scc::configurer cfg(sc_argc == 2 ? sc_argv[1] : "test.yaml");
|
||||
cfg.dump_configuration("dump.yaml", true);
|
||||
cci::cci_originator sc_main_orig("SC_MAIN");
|
||||
cci::cci_param<int> int_param0{"int_param0", 0, "This is parameter 1", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<int> int_param1{"int_param1", 1, "This is parameter 3", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<int64_t> int64_param0{"int64_param0", 10, "This is parameter 2", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<int64_t> int64_param1{"int64_param1", 10, "This is parameter 4", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<unsigned> unsigned_param{"unsigned_param", 1, "This is parameter 5", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<uint64_t> uint64_param{"uint64_param", 1, "This is parameter 6", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<float> float_param{"float_param", 4, "This is parameter 7", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<double> double_param{"double_param", 4, "This is parameter 7", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<std::string> string_param{"string_param", "", "This is parameter 7", cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
cci::cci_param<sc_core::sc_time> sc_time_param{"sc_time_param", sc_core::SC_ZERO_TIME, "This is parameter 7", cci::CCI_ABSOLUTE_NAME,
|
||||
sc_main_orig};
|
||||
cci::cci_param<trace_lvl> trace_lvl_param{"trace_lvl_param", trace_lvl::NONE, "This is parameter 8", cci::CCI_ABSOLUTE_NAME,
|
||||
sc_main_orig};
|
||||
cci::cci_param<test::log_lvl> test_log_lvl_param{"test_log_lvl_param", test::log_lvl::NONE, "This is parameter 9",
|
||||
cci::CCI_ABSOLUTE_NAME, sc_main_orig};
|
||||
// Start the simulation
|
||||
SCCINFO("sc_main") << "Begin Simulation.";
|
||||
sc_core::sc_start(sc_core::SC_ZERO_TIME);
|
||||
SCCINFO("sc_main") << "End Simulation.";
|
||||
|
||||
return sc_core::sc_report_handler::get_count(sc_core::SC_ERROR) + sc_core::sc_report_handler::get_count(sc_core::SC_WARNING);
|
||||
} // End of 'sc_main'
|
@ -1,11 +0,0 @@
|
||||
int_param0: 1
|
||||
int_param1: -1
|
||||
int64_param0: 2
|
||||
int64_param1: -2
|
||||
unsigned_param: 3
|
||||
uint64_param: 4
|
||||
float_param: 5.0
|
||||
double_param: 6
|
||||
string_param: test entry
|
||||
sc_time_param: 10 ns
|
||||
trace_lvl_param: MEDIUM
|
@ -1,6 +1,7 @@
|
||||
project (io_redirector)
|
||||
add_executable (${PROJECT_NAME} test.cpp)
|
||||
target_link_libraries (io_redirector LINK_PUBLIC scc-util Catch2::Catch2WithMain)
|
||||
cmake_minimum_required(VERSION 3.12)
|
||||
add_executable (io_redirector
|
||||
main.cpp
|
||||
)
|
||||
target_link_libraries (io_redirector LINK_PUBLIC scc-util)
|
||||
|
||||
#add_test(NAME io_redirector_test COMMAND io_redirector)
|
||||
catch_discover_tests(${PROJECT_NAME})
|
||||
add_test(NAME io_redirector_test COMMAND io_redirector)
|
@ -5,20 +5,18 @@
|
||||
* Author: eyck
|
||||
*/
|
||||
|
||||
#include <cassert>
|
||||
#include <cstdio>
|
||||
#include <iostream>
|
||||
#include <util/io-redirector.h>
|
||||
#include <iostream>
|
||||
#include <cstdio>
|
||||
#include <cassert>
|
||||
|
||||
using namespace util;
|
||||
|
||||
int main(int arcg, char* argv[]) {
|
||||
int main(int arcg, char* argv[]){
|
||||
IoRedirector::get().start();
|
||||
auto result1 = IoRedirector::get().get_output();
|
||||
assert(result1 == "");
|
||||
assert(result1=="");
|
||||
printf("Some output");
|
||||
std::cout << "Some other output" << std::endl;
|
||||
std::cout<<"Some other output"<<std::endl;
|
||||
auto result2 = IoRedirector::get().get_output();
|
||||
assert(result2 == "Some outputSome other output\n");
|
||||
assert(result2=="Some outputSome other output\n");
|
||||
IoRedirector::get().stop();
|
||||
}
|
||||
|
@ -1,17 +0,0 @@
|
||||
#define CATCH_CONFIG_MAIN
|
||||
#include <catch2/catch_all.hpp>
|
||||
#include <cstdio>
|
||||
#include <iostream>
|
||||
#include <util/io-redirector.h>
|
||||
|
||||
TEST_CASE("io-redirector", "[io-redirector]") {
|
||||
util::IoRedirector::get().start();
|
||||
auto result1 = util::IoRedirector::get().get_output();
|
||||
printf("Some output");
|
||||
std::cout << "Some other output" << std::endl;
|
||||
auto result2 = util::IoRedirector::get().get_output();
|
||||
util::IoRedirector::get().stop();
|
||||
|
||||
REQUIRE(result1 == "");
|
||||
REQUIRE(result2 == "Some outputSome other output\n");
|
||||
}
|
@ -1,9 +1,8 @@
|
||||
project (ordered_semaphore)
|
||||
|
||||
add_executable(${PROJECT_NAME}
|
||||
test.cpp
|
||||
${test_util_SOURCE_DIR}/sc_main.cpp
|
||||
cmake_minimum_required(VERSION 3.12)
|
||||
add_executable (ordered_sem
|
||||
sc_main.cpp
|
||||
)
|
||||
target_link_libraries (${PROJECT_NAME} PUBLIC test_util)
|
||||
target_link_libraries (ordered_sem LINK_PUBLIC scc)
|
||||
target_link_libraries (ordered_sem LINK_PUBLIC ${Boost_LIBRARIES} )
|
||||
|
||||
catch_discover_tests(${PROJECT_NAME})
|
||||
add_test(NAME ordered_sem_test COMMAND ordered_sem)
|
110
tests/ordered_semaphore/sc_main.cpp
Normal file
110
tests/ordered_semaphore/sc_main.cpp
Normal file
@ -0,0 +1,110 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright 2017 eyck@minres.com
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License"); you may not
|
||||
// use this file except in compliance with the License. You may obtain a copy
|
||||
// of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
// License for the specific language governing permissions and limitations under
|
||||
// the License.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
/*
|
||||
* sc_main.cpp
|
||||
*
|
||||
* Created on: 17.09.2017
|
||||
* Author: eyck@minres.com
|
||||
*/
|
||||
|
||||
#include <scc/report.h>
|
||||
#include <scc/tracer.h>
|
||||
#include <boost/program_options.hpp>
|
||||
#include <scc/ordered_semaphore.h>
|
||||
using namespace scc;
|
||||
namespace po = boost::program_options;
|
||||
|
||||
namespace {
|
||||
const size_t ERROR_IN_COMMAND_LINE = 1;
|
||||
const size_t SUCCESS = 0;
|
||||
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
|
||||
} // namespace
|
||||
|
||||
|
||||
class top: public sc_core::sc_module {
|
||||
public:
|
||||
top(sc_core::sc_module_name const&){
|
||||
SC_HAS_PROCESS(top);
|
||||
SC_THREAD(run);
|
||||
}
|
||||
~top() override= default;;
|
||||
private:
|
||||
void run(){
|
||||
sem.wait();
|
||||
sem_t.wait();
|
||||
sem.set_capacity(4);
|
||||
sem_t.set_capacity(4);
|
||||
sem_t.post();
|
||||
sem.post();
|
||||
sc_core::sc_stop();
|
||||
}
|
||||
scc::ordered_semaphore sem{"sem", 2};
|
||||
scc::ordered_semaphore_t<2> sem_t{"sem_t"};
|
||||
};
|
||||
|
||||
|
||||
int sc_main(int argc, char *argv[]) {
|
||||
sc_core::sc_report_handler::set_actions( "/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING );
|
||||
sc_core::sc_report_handler::set_actions(sc_core::SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, sc_core::SC_DO_NOTHING);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// CLI argument parsing
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
po::options_description desc("Options");
|
||||
// clang-format off
|
||||
desc.add_options()
|
||||
("help,h", "Print help message")
|
||||
("debug,d", "set debug level")
|
||||
("trace,t", "trace SystemC signals");
|
||||
// clang-format on
|
||||
po::variables_map vm;
|
||||
try {
|
||||
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
|
||||
// --help option
|
||||
if (vm.count("help")) {
|
||||
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
|
||||
return SUCCESS;
|
||||
}
|
||||
po::notify(vm); // throws on error, so do after help in case
|
||||
// there are any problems
|
||||
} catch (po::error &e) {
|
||||
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
|
||||
std::cerr << desc << std::endl;
|
||||
return ERROR_IN_COMMAND_LINE;
|
||||
}
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// configure logging
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
scc::init_logging(vm.count("debug")?scc::log::DEBUG:scc::log::INFO);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// instantiate top level
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
top tb("tb");
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// run simulation
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
sc_start(sc_core::sc_time(1, sc_core::SC_MS));
|
||||
// todo: provide end-of-simulation macros
|
||||
|
||||
if (!sc_core::sc_end_of_simulation_invoked()) {
|
||||
SCCERR() << "simulation timed out";
|
||||
sc_core::sc_stop();
|
||||
}
|
||||
auto errcnt = sc_core::sc_report_handler::get_count(sc_core::SC_ERROR);
|
||||
auto warncnt = sc_core::sc_report_handler::get_count(sc_core::SC_WARNING);
|
||||
SCCINFO() << "Finished, there were " << errcnt << " error" << (errcnt == 1 ? "" : "s") << " and " << warncnt << " warning"
|
||||
<< (warncnt == 1 ? "" : "s, 1 warning expected");
|
||||
return errcnt + (warncnt-1);
|
||||
}
|
@ -1,39 +0,0 @@
|
||||
#ifndef SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#define SC_INCLUDE_DYNAMIC_PROCESSES
|
||||
#endif
|
||||
#include <catch2/catch_all.hpp>
|
||||
#include <factory.h>
|
||||
#include <scc/ordered_semaphore.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <systemc>
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
struct top : public sc_core::sc_module {
|
||||
top()
|
||||
: top("top") {}
|
||||
top(sc_module_name const& nm)
|
||||
: sc_core::sc_module(nm) {}
|
||||
scc::ordered_semaphore sem{"sem", 2};
|
||||
scc::ordered_semaphore_t<2> sem_t{"sem_t"};
|
||||
};
|
||||
|
||||
factory::add<top> tb;
|
||||
|
||||
TEST_CASE("simple ordered_semaphore test", "[SCC][ordered_semaphore]") {
|
||||
|
||||
auto& dut = factory::get<top>();
|
||||
auto run1 = sc_spawn([&dut]() {
|
||||
dut.sem.wait();
|
||||
dut.sem_t.wait();
|
||||
dut.sem.set_capacity(4);
|
||||
dut.sem_t.set_capacity(4); // should fail
|
||||
dut.sem_t.post();
|
||||
dut.sem.post();
|
||||
});
|
||||
|
||||
sc_start(1_ns);
|
||||
REQUIRE(run1.terminated());
|
||||
REQUIRE(sc_report_handler::get_count(SC_ERROR) == 0);
|
||||
REQUIRE(sc_report_handler::get_count(SC_WARNING) == 1);
|
||||
}
|
@ -1,6 +1,4 @@
|
||||
cmake_minimum_required(VERSION 3.12)
|
||||
find_package(fmt)
|
||||
find_package(Boost COMPONENTS program_options REQUIRED)
|
||||
add_executable (sim_performance
|
||||
sc_main.cpp
|
||||
pkt_sender.cpp
|
||||
@ -8,16 +6,4 @@ add_executable (sim_performance
|
||||
top.cpp
|
||||
)
|
||||
target_link_libraries (sim_performance LINK_PUBLIC scc)
|
||||
target_link_libraries (sim_performance LINK_PUBLIC scc fmt::fmt)
|
||||
if(TARGET Boost::program_options)
|
||||
target_link_libraries(sim_performance PUBLIC Boost::program_options)
|
||||
else()
|
||||
target_link_libraries(sim_performance PUBLIC ${BOOST_program_options_LIBRARY})
|
||||
endif()
|
||||
|
||||
#Mateo Done erst count 16384
|
||||
foreach(x RANGE 1 10)
|
||||
add_test(NAME sim_performance_16x16_${x} COMMAND sim_performance)
|
||||
add_test(NAME sim_performance_32x32_${x} COMMAND sim_performance --dim 32 --count 50000)
|
||||
add_test(NAME sim_performance_64x64_${x} COMMAND sim_performance --dim 64 --count 100000)
|
||||
endforeach()
|
||||
target_link_libraries (sim_performance LINK_PUBLIC ${Boost_LIBRARIES} )
|
||||
|
@ -14,18 +14,20 @@ struct packet {
|
||||
std::vector<uint8_t> routing;
|
||||
};
|
||||
|
||||
struct packet_ext : public tlm::tlm_extension<packet_ext>, public packet {
|
||||
struct packet_ext: public tlm::tlm_extension<packet_ext>, public packet {
|
||||
|
||||
packet_ext() = default;
|
||||
|
||||
packet_ext& operator=(packet_ext const& o) = default;
|
||||
|
||||
tlm_extension_base* clone() const override { return new packet_ext(*this); }
|
||||
tlm_extension_base* clone() const override {
|
||||
return new packet_ext(*this);
|
||||
}
|
||||
|
||||
void copy_from(tlm_extension_base const& o) override {
|
||||
void copy_from(tlm_extension_base const & o) override {
|
||||
auto* ext = dynamic_cast<packet_ext const*>(&o);
|
||||
if(ext)
|
||||
this->routing = ext->routing;
|
||||
this->routing=ext->routing;
|
||||
}
|
||||
};
|
||||
|
||||
|
@ -12,85 +12,88 @@
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
pkt_sender::pkt_sender(const sc_core::sc_module_name& nm, unsigned dim, unsigned pos_x, unsigned pos_y, unsigned count)
|
||||
pkt_sender::pkt_sender(const sc_core::sc_module_name &nm, unsigned dim, unsigned pos_x, unsigned pos_y, unsigned count)
|
||||
: sc_module(nm)
|
||||
, bw_peq("bw_peq")
|
||||
, fw_peq("fw_peq")
|
||||
, my_pos{pos_x, pos_y}
|
||||
, my_pos{pos_x,pos_y}
|
||||
, dim{dim}
|
||||
, count{count} {
|
||||
SCCDEBUG(SCMOD) << "instantiating sender " << pos_x << "/" << pos_y;
|
||||
, count{count}
|
||||
{
|
||||
SCCDEBUG(SCMOD)<<"instantiating sender "<<pos_x<<"/"<<pos_y;
|
||||
SC_HAS_PROCESS(pkt_sender);
|
||||
isck.register_nb_transport_bw([this](tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase,
|
||||
sc_core::sc_time& delay) -> tlm::tlm_sync_enum { return this->nb_bw(gp, phase, delay); });
|
||||
tsck.register_nb_transport_fw([this](tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase,
|
||||
sc_core::sc_time& delay) -> tlm::tlm_sync_enum { return this->nb_fw(gp, phase, delay); });
|
||||
isck.register_nb_transport_bw([this](tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay)->tlm::tlm_sync_enum{
|
||||
return this->nb_bw(gp, phase, delay);
|
||||
});
|
||||
tsck.register_nb_transport_fw([this](tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay)->tlm::tlm_sync_enum{
|
||||
return this->nb_fw(gp, phase, delay);
|
||||
});
|
||||
SC_METHOD(received);
|
||||
sensitive << fw_peq.get_event();
|
||||
sensitive<<fw_peq.get_event();
|
||||
dont_initialize();
|
||||
SC_THREAD(run);
|
||||
}
|
||||
|
||||
void pkt_sender::gen_routing(std::vector<uint8_t>& route_vec) {
|
||||
if(std::get<0>(my_pos) == 0) {
|
||||
for(auto i = 0; i < dim; ++i)
|
||||
void pkt_sender::gen_routing(std::vector<uint8_t> &route_vec) {
|
||||
if(std::get<0>(my_pos)==0){
|
||||
for(auto i=0; i<dim; ++i)
|
||||
route_vec.push_back(RIGHT);
|
||||
} else if(std::get<0>(my_pos) == dim + 1) {
|
||||
for(auto i = 0; i < dim; ++i)
|
||||
} else if(std::get<0>(my_pos)==dim+1){
|
||||
for(auto i=0; i<dim; ++i)
|
||||
route_vec.push_back(LEFT);
|
||||
} else if(std::get<1>(my_pos) == 0) {
|
||||
for(auto i = 0; i < dim; ++i)
|
||||
} else if(std::get<1>(my_pos)==0){
|
||||
for(auto i=0; i<dim; ++i)
|
||||
route_vec.push_back(BOTTOM);
|
||||
} else if(std::get<1>(my_pos) == dim + 1) {
|
||||
for(auto i = 0; i < dim; ++i)
|
||||
} else if(std::get<1>(my_pos)==dim+1){
|
||||
for(auto i=0; i<dim; ++i)
|
||||
route_vec.push_back(TOP);
|
||||
} else
|
||||
SCCERR(SCMOD) << "WTF!?!";
|
||||
SCCERR(SCMOD)<<"WTF!?!";
|
||||
}
|
||||
|
||||
void pkt_sender::run() {
|
||||
wait(clk_i.posedge_event());
|
||||
for(auto i = 0U; i < count; i++) {
|
||||
for(auto i=0U; i<count; i++){
|
||||
tlm::tlm_generic_payload* gp = tlm::scc::tlm_mm<>::get().allocate<packet_ext>();
|
||||
gen_routing(gp->get_extension<packet_ext>()->routing);
|
||||
tlm::tlm_phase phase{tlm::BEGIN_REQ};
|
||||
sc_time delay;
|
||||
gp->acquire();
|
||||
auto sync = isck->nb_transport_fw(*gp, phase, delay);
|
||||
sc_assert(sync == tlm::TLM_UPDATED && phase == tlm::END_REQ);
|
||||
sc_assert(sync==tlm::TLM_UPDATED && phase==tlm::END_REQ);
|
||||
tlm::tlm_generic_payload* ret{nullptr};
|
||||
while(!(ret = bw_peq.get_next_transaction())) {
|
||||
while(!(ret=bw_peq.get_next_transaction())){
|
||||
wait(bw_peq.get_event());
|
||||
}
|
||||
sc_assert(gp == ret);
|
||||
sc_assert(gp==ret);
|
||||
ret->release();
|
||||
}
|
||||
finish_evt.notify(SC_ZERO_TIME);
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum pkt_sender::nb_bw(tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay) {
|
||||
sc_assert(phase == tlm::BEGIN_RESP);
|
||||
tlm::tlm_sync_enum pkt_sender::nb_bw(tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) {
|
||||
sc_assert(phase==tlm::BEGIN_RESP);
|
||||
bw_peq.notify(gp, delay);
|
||||
phase = tlm::END_RESP;
|
||||
phase=tlm::END_RESP;
|
||||
return tlm::TLM_COMPLETED;
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum pkt_sender::nb_fw(tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay) {
|
||||
sc_assert(phase == tlm::BEGIN_REQ);
|
||||
tlm::tlm_sync_enum pkt_sender::nb_fw(tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) {
|
||||
sc_assert(phase==tlm::BEGIN_REQ);
|
||||
auto ext = gp.get_extension<packet_ext>();
|
||||
sc_assert(ext->routing.size() == 0);
|
||||
sc_assert(ext->routing.size()==0);
|
||||
gp.acquire();
|
||||
fw_peq.notify(gp, delay);
|
||||
phase = tlm::END_REQ;
|
||||
phase=tlm::END_REQ;
|
||||
return tlm::TLM_UPDATED;
|
||||
}
|
||||
|
||||
void pkt_sender::received() {
|
||||
if(auto gp = fw_peq.get_next_transaction()) {
|
||||
if(auto gp = fw_peq.get_next_transaction()){
|
||||
tlm::tlm_phase phase{tlm::BEGIN_RESP};
|
||||
sc_time delay;
|
||||
auto sync = tsck->nb_transport_bw(*gp, phase, delay);
|
||||
sc_assert(sync == tlm::TLM_COMPLETED && phase == tlm::END_RESP);
|
||||
sc_assert(sync==tlm::TLM_COMPLETED && phase==tlm::END_RESP);
|
||||
gp->release();
|
||||
}
|
||||
}
|
||||
|
@ -8,11 +8,12 @@
|
||||
#ifndef _SIM_PERFORMANCE_PKT_SENDER_H_
|
||||
#define _SIM_PERFORMANCE_PKT_SENDER_H_
|
||||
|
||||
#include "packet.h"
|
||||
#include <systemc>
|
||||
#include "packet.h"
|
||||
#include <tlm/scc/initiator_mixin.h>
|
||||
#include <tlm/scc/target_mixin.h>
|
||||
|
||||
|
||||
class pkt_sender : sc_core::sc_module {
|
||||
public:
|
||||
sc_core::sc_in<bool> clk_i{"clk_i"};
|
||||
@ -20,8 +21,7 @@ public:
|
||||
tlm::scc::target_mixin<tlm::tlm_target_socket<32>> tsck;
|
||||
pkt_sender(sc_core::sc_module_name const&, unsigned dim, unsigned pos_x, unsigned pos_y, unsigned count);
|
||||
virtual ~pkt_sender() = default;
|
||||
sc_core::sc_event const& get_finish_event() { return finish_evt; }
|
||||
|
||||
sc_core::sc_event const& get_finish_event(){return finish_evt;}
|
||||
private:
|
||||
void run();
|
||||
void gen_routing(std::vector<uint8_t>& route_vec);
|
||||
|
@ -14,67 +14,63 @@
|
||||
|
||||
using namespace sc_core;
|
||||
|
||||
pkt_switch::pkt_switch(const sc_core::sc_module_name& nm)
|
||||
: sc_module(nm) {
|
||||
pkt_switch::pkt_switch(const sc_core::sc_module_name &nm):sc_module(nm) {
|
||||
SC_HAS_PROCESS(pkt_switch);
|
||||
auto index = 0U;
|
||||
for(auto& s : isck) {
|
||||
s.register_nb_transport_bw([this](unsigned id, tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase,
|
||||
sc_core::sc_time& delay) -> tlm::tlm_sync_enum { return this->nb_bw(id, gp, phase, delay); },
|
||||
index++);
|
||||
for(auto& s:isck){
|
||||
s.register_nb_transport_bw([this](unsigned id, tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay)->tlm::tlm_sync_enum{
|
||||
return this->nb_bw(id, gp, phase, delay);
|
||||
}, index++);
|
||||
}
|
||||
index = 0U;
|
||||
for(auto& s : tsck) {
|
||||
s.register_nb_transport_fw([this](unsigned id, tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase,
|
||||
sc_core::sc_time& delay) -> tlm::tlm_sync_enum { return this->nb_fw(id, gp, phase, delay); },
|
||||
index++);
|
||||
for(auto& s:tsck){
|
||||
s.register_nb_transport_fw([this](unsigned id, tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay)->tlm::tlm_sync_enum{
|
||||
return this->nb_fw(id, gp, phase, delay);
|
||||
}, index++);
|
||||
}
|
||||
SC_METHOD(clock_cb);
|
||||
sensitive << clk_i.pos();
|
||||
sensitive<<clk_i.pos();
|
||||
dont_initialize();
|
||||
for(auto i = 0U; i < SIDES; ++i) {
|
||||
for(auto i=0U; i<SIDES; ++i){
|
||||
sc_core::sc_spawn_options opts;
|
||||
opts.spawn_method();
|
||||
opts.set_sensitivity(&out_fifo[i].data_written_event());
|
||||
sc_core::sc_spawn([this, i]() -> void { this->output_cb(i); }, sc_core::sc_gen_unique_name("out_peq"), &opts);
|
||||
sc_core::sc_spawn([this, i]()->void {this->output_cb(i);}, sc_core::sc_gen_unique_name("out_peq"), &opts);
|
||||
}
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum pkt_switch::nb_fw(unsigned id, tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay) {
|
||||
tlm::tlm_sync_enum pkt_switch::nb_fw(unsigned id, tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) {
|
||||
in_tx[id].write(&gp);
|
||||
if(phase == tlm::BEGIN_REQ)
|
||||
phase = tlm::END_REQ;
|
||||
else
|
||||
SCCERR(SCMOD) << "WTF!?!";
|
||||
if(phase==tlm::BEGIN_REQ) phase=tlm::END_REQ;
|
||||
else SCCERR(SCMOD)<<"WTF!?!";
|
||||
return tlm::TLM_UPDATED;
|
||||
}
|
||||
|
||||
void pkt_switch::clock_cb() {
|
||||
std::array<std::vector<unsigned>, SIDES> routing{};
|
||||
bool nothing_todo = true;
|
||||
for(auto i = 0U; i < SIDES; ++i) {
|
||||
if(auto gp = in_tx[i].read()) {
|
||||
bool nothing_todo=true;
|
||||
for(auto i=0U; i<SIDES; ++i){
|
||||
if(auto gp = in_tx[i].read()){
|
||||
auto ext = gp->get_extension<packet_ext>();
|
||||
sc_assert(ext);
|
||||
routing[ext->routing.back()].push_back(i);
|
||||
nothing_todo = false;
|
||||
}
|
||||
}
|
||||
if(nothing_todo)
|
||||
return;
|
||||
for(auto i = 0U; i < SIDES; ++i) {
|
||||
if(routing[i].size()) {
|
||||
auto selected_input = routing[i].front();
|
||||
if(nothing_todo) return;
|
||||
for(auto i=0U; i<SIDES; ++i){
|
||||
if(routing[i].size()){
|
||||
auto selected_input=routing[i].front();
|
||||
auto* gp = in_tx[selected_input].read();
|
||||
if(out_fifo[i].nb_write(gp)) {
|
||||
if(out_fifo[i].nb_write(gp)){
|
||||
auto ext = gp->get_extension<packet_ext>();
|
||||
ext->routing.pop_back();
|
||||
gp->acquire();
|
||||
tlm::tlm_phase phase{tlm::BEGIN_RESP};
|
||||
sc_core::sc_time delay;
|
||||
auto res = tsck[selected_input]->nb_transport_bw(*gp, phase, delay);
|
||||
if(res != tlm::TLM_COMPLETED && !(res == tlm::TLM_UPDATED && phase == tlm::END_RESP))
|
||||
SCCERR(SCMOD) << "WTF!?!";
|
||||
if(res!=tlm::TLM_COMPLETED && !(res==tlm::TLM_UPDATED && phase==tlm::END_RESP))
|
||||
SCCERR(SCMOD)<<"WTF!?!";
|
||||
in_tx[selected_input].clear();
|
||||
}
|
||||
}
|
||||
@ -83,18 +79,18 @@ void pkt_switch::clock_cb() {
|
||||
|
||||
void pkt_switch::output_cb(unsigned id) {
|
||||
|
||||
if(out_fifo[id].num_available()) {
|
||||
if(out_fifo[id].num_available()){
|
||||
auto* gp = out_fifo[id].read();
|
||||
tlm::tlm_phase phase{tlm::BEGIN_REQ};
|
||||
sc_time delay;
|
||||
auto sync = isck[id]->nb_transport_fw(*gp, phase, delay);
|
||||
sc_assert(sync == tlm::TLM_UPDATED && phase == tlm::END_REQ);
|
||||
sc_assert(sync==tlm::TLM_UPDATED && phase==tlm::END_REQ);
|
||||
}
|
||||
}
|
||||
|
||||
tlm::tlm_sync_enum pkt_switch::nb_bw(unsigned id, tlm::tlm_generic_payload& gp, tlm::tlm_phase& phase, sc_core::sc_time& delay) {
|
||||
tlm::tlm_sync_enum pkt_switch::nb_bw(unsigned id, tlm::tlm_generic_payload &gp, tlm::tlm_phase &phase, sc_core::sc_time &delay) {
|
||||
gp.release();
|
||||
sc_assert(phase == tlm::BEGIN_RESP);
|
||||
phase = tlm::END_RESP;
|
||||
sc_assert(phase==tlm::BEGIN_RESP);
|
||||
phase=tlm::END_RESP;
|
||||
return tlm::TLM_COMPLETED;
|
||||
}
|
||||
|
@ -8,22 +8,22 @@
|
||||
#ifndef _SIM_PERFORMANCE_PKT_SWITCH_H_
|
||||
#define _SIM_PERFORMANCE_PKT_SWITCH_H_
|
||||
|
||||
#include "packet.h"
|
||||
#include <array>
|
||||
#include <scc/sc_owning_signal.h>
|
||||
#include <systemc>
|
||||
#include "packet.h"
|
||||
#include <tlm/scc/tagged_initiator_mixin.h>
|
||||
#include <tlm/scc/tagged_target_mixin.h>
|
||||
#include <scc/sc_owning_signal.h>
|
||||
#include <array>
|
||||
|
||||
|
||||
class pkt_switch : sc_core::sc_module {
|
||||
public:
|
||||
enum { NONE = std::numeric_limits<unsigned>::max() };
|
||||
enum {NONE=std::numeric_limits<unsigned>::max()};
|
||||
sc_core::sc_in<bool> clk_i{"clk_i"};
|
||||
sc_core::sc_vector<tlm::scc::tagged_target_mixin<tlm::tlm_target_socket<32>>> tsck{"tsck", 4};
|
||||
sc_core::sc_vector<tlm::scc::tagged_initiator_mixin<tlm::tlm_initiator_socket<32>>> isck{"isck", 4};
|
||||
sc_core::sc_vector<tlm::scc::tagged_target_mixin<tlm::tlm_target_socket<32>>> tsck{"tsck",4};
|
||||
sc_core::sc_vector<tlm::scc::tagged_initiator_mixin<tlm::tlm_initiator_socket<32>>> isck{"isck",4};
|
||||
pkt_switch(sc_core::sc_module_name const&);
|
||||
virtual ~pkt_switch() = default;
|
||||
|
||||
private:
|
||||
void clock_cb();
|
||||
void output_cb(unsigned);
|
||||
|
@ -21,10 +21,10 @@
|
||||
*/
|
||||
|
||||
#include "top.h"
|
||||
#include <boost/program_options.hpp>
|
||||
#include <scc/perf_estimator.h>
|
||||
#include <scc/report.h>
|
||||
#include <scc/tracer.h>
|
||||
#include <boost/program_options.hpp>
|
||||
|
||||
using namespace scc;
|
||||
namespace po = boost::program_options;
|
||||
@ -35,8 +35,8 @@ const size_t SUCCESS = 0;
|
||||
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
|
||||
} // namespace
|
||||
|
||||
int sc_main(int argc, char* argv[]) {
|
||||
sc_core::sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING);
|
||||
int sc_main(int argc, char *argv[]) {
|
||||
sc_core::sc_report_handler::set_actions( "/IEEE_Std_1666/deprecated", sc_core::SC_DO_NOTHING );
|
||||
sc_core::sc_report_handler::set_actions(sc_core::SC_ID_MORE_THAN_ONE_SIGNAL_DRIVER_, sc_core::SC_DO_NOTHING);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// CLI argument parsing
|
||||
@ -47,20 +47,20 @@ int sc_main(int argc, char* argv[]) {
|
||||
("help,h", "Print help message")
|
||||
("debug,d", "set debug level")
|
||||
("trace,t", "trace SystemC signals")
|
||||
("dim", po::value<unsigned>()->default_value(16))
|
||||
("dim", po::value<uint8_t>()->default_value(16))
|
||||
("count", po::value<unsigned>()->default_value(16384));
|
||||
// clang-format on
|
||||
po::variables_map vm;
|
||||
try {
|
||||
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
|
||||
// --help option
|
||||
if(vm.count("help")) {
|
||||
if (vm.count("help")) {
|
||||
std::cout << "JIT-ISS simulator for AVR" << std::endl << desc << std::endl;
|
||||
return SUCCESS;
|
||||
}
|
||||
po::notify(vm); // throws on error, so do after help in case
|
||||
// there are any problems
|
||||
} catch(po::error& e) {
|
||||
} catch (po::error &e) {
|
||||
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
|
||||
std::cerr << desc << std::endl;
|
||||
return ERROR_IN_COMMAND_LINE;
|
||||
@ -68,20 +68,20 @@ int sc_main(int argc, char* argv[]) {
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// configure logging
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
scc::init_logging(vm.count("debug") ? scc::log::DEBUG : scc::log::INFO);
|
||||
scc::init_logging(vm.count("debug")?scc::log::DEBUG:scc::log::INFO);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// set up tracing & transaction recording
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// tracer trace("simple_system", tracer::TEXT, vm.count("trace"));
|
||||
// todo: fix displayed clock period in VCD
|
||||
//tracer trace("simple_system", tracer::TEXT, vm.count("trace"));
|
||||
// todo: fix displayed clock period in VCD
|
||||
try {
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// instantiate top level
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
perf_estimator estimator;
|
||||
auto const count = vm["count"].as<unsigned>();
|
||||
auto const dim = vm["dim"].as<unsigned>();
|
||||
SCCINFO() << "Instantiating " << (unsigned)dim << "x" << (unsigned)dim << " matrix and executing " << count << " accesses";
|
||||
auto const count=vm["count"].as<unsigned>();
|
||||
auto const dim = vm["dim"].as<uint8_t>();
|
||||
SCCINFO()<<"Instantiating "<<(unsigned)dim<<"x"<<(unsigned)dim<<" matrix and executing "<<count<<" accesses";
|
||||
top i_top("i_top", dim, count);
|
||||
///////////////////////////////////////////////////////////////////////////
|
||||
// run simulation
|
||||
|
@ -6,35 +6,34 @@
|
||||
*/
|
||||
|
||||
#include "top.h"
|
||||
#include <fmt/format.h>
|
||||
#include <scc/report.h>
|
||||
#include <scc/utilities.h>
|
||||
#include <scc/report.h>
|
||||
#include <fmt/format.h>
|
||||
|
||||
using namespace sc_core;
|
||||
using namespace fmt;
|
||||
|
||||
top::top(sc_core::sc_module_name const& nm, uint8_t dimension, unsigned count)
|
||||
: sc_module(nm) {
|
||||
sc_assert(dimension > 0);
|
||||
top::top(sc_core::sc_module_name const& nm, uint8_t dimension,unsigned count) :sc_module(nm){
|
||||
sc_assert(dimension>0);
|
||||
SC_HAS_PROCESS(top);
|
||||
for(auto yidx = 0U; yidx < dimension; ++yidx) {
|
||||
for(auto xidx = 0U; xidx < dimension; ++xidx) {
|
||||
for(auto yidx=0U; yidx<dimension; ++yidx){
|
||||
for(auto xidx=0U; xidx<dimension; ++xidx){
|
||||
auto name = format("sw_{}_{}", xidx, yidx);
|
||||
SCCDEBUG(SCMOD) << "instantiating switch " << xidx << "/" << yidx;
|
||||
SCCDEBUG(SCMOD)<<"instantiating switch "<<xidx<<"/"<<yidx;
|
||||
switches.push_back(scc::make_unique<pkt_switch>(sc_module_name(name.c_str())));
|
||||
switches.back()->clk_i(clk);
|
||||
}
|
||||
}
|
||||
for(auto yidx = 0U; yidx < dimension; ++yidx) {
|
||||
for(auto xidx = 0U; xidx < dimension; ++xidx) {
|
||||
auto& sw = switches[yidx * dimension + xidx];
|
||||
if(xidx < dimension - 1) {
|
||||
auto& swr = switches[yidx * dimension + (xidx + 1)];
|
||||
for(auto yidx=0U; yidx<dimension; ++yidx){
|
||||
for(auto xidx=0U; xidx<dimension; ++xidx){
|
||||
auto& sw = switches[yidx*dimension+xidx];
|
||||
if(xidx<dimension-1) {
|
||||
auto& swr = switches[yidx*dimension+(xidx+1)];
|
||||
sw->isck[RIGHT](swr->tsck[LEFT]);
|
||||
swr->isck[LEFT](sw->tsck[RIGHT]);
|
||||
}
|
||||
if(yidx < dimension - 1) {
|
||||
auto& swb = switches[(yidx + 1) * dimension + xidx];
|
||||
if(yidx<dimension-1){
|
||||
auto& swb = switches[(yidx+1)*dimension+xidx];
|
||||
sw->isck[BOTTOM](swb->tsck[TOP]);
|
||||
swb->isck[TOP](sw->tsck[BOTTOM]);
|
||||
}
|
||||
@ -42,42 +41,42 @@ top::top(sc_core::sc_module_name const& nm, uint8_t dimension, unsigned count)
|
||||
}
|
||||
auto yidx = 0U;
|
||||
auto xidx = 0U;
|
||||
for(xidx = 0U; xidx < dimension; ++xidx) {
|
||||
auto name = format("snd_{}_{}", xidx + 1, 0);
|
||||
senders[TOP].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, xidx + 1, 0, count));
|
||||
for(xidx=0U; xidx<dimension; ++xidx){
|
||||
auto name = format("snd_{}_{}", xidx+1, 0);
|
||||
senders[TOP].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, xidx+1, 0, count));
|
||||
auto& snd = senders[TOP].back();
|
||||
snd->clk_i(clk);
|
||||
auto& sw = switches[yidx * dimension + xidx];
|
||||
auto& sw = switches[yidx*dimension+xidx];
|
||||
snd->isck(sw->tsck[TOP]);
|
||||
sw->isck[TOP](snd->tsck);
|
||||
}
|
||||
yidx = dimension - 1;
|
||||
for(xidx = 0U; xidx < dimension; ++xidx) {
|
||||
auto name = format("snd_{}_{}", xidx + 1, dimension + 1);
|
||||
senders[BOTTOM].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, xidx + 1, dimension + 1, count));
|
||||
yidx=dimension-1;
|
||||
for(xidx=0U; xidx<dimension; ++xidx){
|
||||
auto name = format("snd_{}_{}", xidx+1, dimension+1);
|
||||
senders[BOTTOM].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, xidx+1, dimension+1, count));
|
||||
auto& snd = senders[BOTTOM].back();
|
||||
snd->clk_i(clk);
|
||||
auto& sw = switches[yidx * dimension + xidx];
|
||||
auto& sw = switches[yidx*dimension+xidx];
|
||||
snd->isck(sw->tsck[BOTTOM]);
|
||||
sw->isck[BOTTOM](snd->tsck);
|
||||
}
|
||||
xidx = 0U;
|
||||
for(yidx = 0U; yidx < dimension; ++yidx) {
|
||||
auto name = format("snd_{}_{}", 0, yidx + 1);
|
||||
senders[LEFT].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, 0, yidx + 1, count));
|
||||
xidx=0U;
|
||||
for(yidx=0U; yidx<dimension; ++yidx){
|
||||
auto name = format("snd_{}_{}", 0, yidx+1);
|
||||
senders[LEFT].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, 0, yidx+1, count));
|
||||
auto& snd = senders[LEFT].back();
|
||||
snd->clk_i(clk);
|
||||
auto& sw = switches[yidx * dimension + xidx];
|
||||
auto& sw = switches[yidx*dimension+xidx];
|
||||
snd->isck(sw->tsck[LEFT]);
|
||||
sw->isck[LEFT](snd->tsck);
|
||||
}
|
||||
xidx = dimension - 1;
|
||||
for(yidx = 0U; yidx < dimension; ++yidx) {
|
||||
auto name = format("snd_{}_{}", dimension + 1, yidx + 1);
|
||||
senders[RIGHT].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, dimension + 1, yidx + 1, count));
|
||||
xidx=dimension-1;
|
||||
for(yidx=0U; yidx<dimension; ++yidx){
|
||||
auto name = format("snd_{}_{}", dimension+1, yidx+1);
|
||||
senders[RIGHT].push_back(scc::make_unique<pkt_sender>(sc_module_name(name.c_str()), dimension, dimension+1, yidx+1, count));
|
||||
auto& snd = senders[RIGHT].back();
|
||||
snd->clk_i(clk);
|
||||
auto& sw = switches[yidx * dimension + xidx];
|
||||
auto& sw = switches[yidx*dimension+xidx];
|
||||
snd->isck(sw->tsck[RIGHT]);
|
||||
sw->isck[RIGHT](snd->tsck);
|
||||
}
|
||||
@ -86,11 +85,12 @@ top::top(sc_core::sc_module_name const& nm, uint8_t dimension, unsigned count)
|
||||
|
||||
void top::run() {
|
||||
sc_event_and_list evt_list;
|
||||
for(auto& sides : senders) {
|
||||
for(auto& sender : sides) {
|
||||
evt_list &= sender->get_finish_event();
|
||||
for(auto& sides:senders) {
|
||||
for(auto& sender:sides){
|
||||
evt_list&=sender->get_finish_event();
|
||||
}
|
||||
}
|
||||
wait(evt_list);
|
||||
sc_stop();
|
||||
}
|
||||
|
||||
|
@ -8,18 +8,17 @@
|
||||
#ifndef _SIM_PERFORMANCE_TOP_H_
|
||||
#define _SIM_PERFORMANCE_TOP_H_
|
||||
|
||||
#include <systemc>
|
||||
#include <memory>
|
||||
#include <vector>
|
||||
#include "pkt_sender.h"
|
||||
#include "pkt_switch.h"
|
||||
#include "types.h"
|
||||
#include <memory>
|
||||
#include <systemc>
|
||||
#include <vector>
|
||||
|
||||
class top : public sc_core::sc_module {
|
||||
class top: public sc_core::sc_module {
|
||||
public:
|
||||
top(sc_core::sc_module_name const&, uint8_t, unsigned);
|
||||
virtual ~top() = default;
|
||||
|
||||
private:
|
||||
void run();
|
||||
sc_core::sc_clock clk;
|
||||
|
@ -8,6 +8,6 @@
|
||||
#ifndef TESTS_SIM_PERFORMANCE_TYPES_H_
|
||||
#define TESTS_SIM_PERFORMANCE_TYPES_H_
|
||||
|
||||
enum { TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3, SIDES = 4 };
|
||||
enum {TOP=0, RIGHT=1, BOTTOM=2, LEFT=3, SIDES=4};
|
||||
|
||||
#endif /* TESTS_SIM_PERFORMANCE_TYPES_H_ */
|
||||
|
Loading…
Reference in New Issue
Block a user