updates scc and adapts tests

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eyck committed 2024-12-11 11:03:49 +01:00
1 parent 6df06684bc
commit 82b219f267
2 files changed
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Submodule scc updated: f1d5dc5335...fa87148727.
+2 -2
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@@ -150,7 +150,7 @@ void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
auto& dut = factory::get<testbench>();
dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
auto cycles = run_scenario(state);
REQUIRE(cycles < 1000);
@@ -192,7 +192,7 @@ void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
auto& dut = factory::get<testbench>();
dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
auto cycles = run_scenario(state);
REQUIRE(cycles < 1000);