updates scc and adapts tests
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2
scc
2
scc
Submodule scc updated: f1d5dc5335...fa87148727
@ -150,7 +150,7 @@ void axi4_burst_alignment(bool pipelined_wrreq, bool write_bp) {
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auto& dut = factory::get<testbench>();
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dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
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dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
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dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
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auto cycles = run_scenario(state);
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REQUIRE(cycles < 1000);
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@ -192,7 +192,7 @@ void axi4_narrow_burst(bool pipelined_wrreq, bool write_bp) {
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auto& dut = factory::get<testbench>();
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dut.intor_bfm.pipelined_wrreq = pipelined_wrreq;
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dut.tgt_pe.wr_data_accept_delay.value = write_bp ? 1 : 0;
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dut.tgt_pe.wr_data_accept_delay.set_value(write_bp ? 1 : 0);
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auto cycles = run_scenario(state);
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REQUIRE(cycles < 1000);
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