updates scc and adds scc::memory tests
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2025-08-29 07:39:28 +02:00
parent 633a05c265
commit 22a8890f74
8 changed files with 145 additions and 7 deletions

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@@ -59,7 +59,7 @@ include(CTest)
include(Catch)
enable_testing()
set(WITH_SCP4SCC ON)
add_subdirectory(scc)
add_subdirectory(src)
add_subdirectory(tests)

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@@ -10,7 +10,7 @@ class Pkg(ConanFile):
"CMakeDeps"
)
default_options = {
"llvm-core/*:targets": "X86",
"systemc/*:shared": "True",
"boost/*:fPIC": "True",
"boost/*:header_only": "False",
"boost/*:without_contract": "True",
@@ -32,7 +32,6 @@ class Pkg(ConanFile):
"boost/*:without_timer": "True",
"boost/*:without_type_erasure": "True",
"boost/*:without_wave": "True",
"systemc/*:shared": "True"
}
def requirements(self):
@@ -46,8 +45,6 @@ class Pkg(ConanFile):
self.requires("jsoncpp/1.9.5")
self.requires("zlib/1.2.12")
self.requires("rapidjson/cci.20230929")
if "WITH_LLVM" in os.environ:
self.requires("llvm-core/19.1.7")
if os.path.isdir("tgc-iss/dbt-rise-plugins"):
self.requires("lua/5.4.3")

2
scc

Submodule scc updated: 2ab9bcda69...c8536918fe

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@@ -10,6 +10,7 @@ add_subdirectory(configurer)
add_subdirectory(sc_fixed_tracing)
add_subdirectory(cxs_tlm)
add_subdirectory(tlm_memory)
add_subdirectory(memory_subsys)
add_subdirectory(sim_speed)
if(FULL_TEST_SUITE)
add_subdirectory(sim_performance)

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@@ -29,7 +29,7 @@ template <unsigned PHIT_WIDTH> struct testbench : public sc_core::sc_module {
cxs_transmitter<PHIT_WIDTH> tx{"tx"};
cxs_channel<PHIT_WIDTH> cxs_chan{"cxs_chan"};
cxs_receiver<PHIT_WIDTH> rx{"rx"};
tlm::nw::target_mixin<cxs_pkt_target_socket<>, cxs_packet_types> tsck{"tsck"};
tlm::nw::target_mixin<cxs_pkt_target_socket<>, false, cxs_packet_types> tsck{"tsck"};
testbench()
: testbench(sc_core::sc_gen_unique_name("testbench", false)) {}

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@@ -0,0 +1,8 @@
project (memory_subsys)
add_executable(${PROJECT_NAME}
memory_test.cpp
${test_util_SOURCE_DIR}/sc_main.cpp
)
target_link_libraries (${PROJECT_NAME} PUBLIC scc::components test_util)
catch_discover_tests(${PROJECT_NAME})

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@@ -0,0 +1,72 @@
#include "testbench.h"
#include <factory.h>
#include <tlm/scc/tlm_gp_shared.h>
#undef CHECK
#include <array>
#include <catch2/catch_all.hpp>
#include <cstdint>
#include <deque>
#include <unordered_map>
using namespace sc_core;
namespace scc {
factory::add<testbench> tb;
template <typename T> void prepare_trans(tlm::tlm_generic_payload& trans, tlm::tlm_command cmd, uint64_t addr, T val) {
unsigned len = cmd == tlm::TLM_IGNORE_COMMAND ? 0 : sizeof(val);
unsigned char* data = len ? new unsigned char[len] : nullptr;
if(cmd == tlm::TLM_WRITE_COMMAND) {
memcpy(data, &val, len);
trans.set_command(cmd);
}
if(cmd == tlm::TLM_READ_COMMAND) {
memset(data, 0, len);
trans.set_command(tlm::TLM_READ_COMMAND);
}
trans.set_address(addr);
trans.set_data_ptr(data);
trans.set_data_length(len);
trans.set_streaming_width(len);
trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
}
template<typename T>
void do_dmi_access(T& isck, uint64_t address, uint64_t expected_size) {
tlm::tlm_generic_payload gp;
tlm::tlm_dmi dmi;
gp.set_address(address);
auto res = isck->get_direct_mem_ptr(gp, dmi);
REQUIRE(res == true);
REQUIRE(dmi.get_start_address() == address);
REQUIRE(dmi.get_end_address() == (address + expected_size-1));
REQUIRE(dmi.is_read_write_allowed());
}
TEST_CASE("simple_read_write_with host memory map", "[memory][tlm-level]") {
auto& dut = factory::get<testbench>();
std::array<unsigned char, 256> ref_data;
auto val = 256;
for(auto& e : ref_data)
e = --val;
dut.rst.write(true);
sc_start(10 * dut.clk.read());
dut.rst.write(false);
sc_start(dut.clk.read());
do_dmi_access(dut.isck0, 0, 1_kB);
do_dmi_access(dut.isck0, 1_kB, 1_kB);
do_dmi_access(dut.isck0, 16_MB, 16_MB);
do_dmi_access(dut.isck0, 32_MB, 16_MB);
do_dmi_access(dut.isck0, 48_MB, 4_MB);
do_dmi_access(dut.isck0, 64_MB, 16_MB);
do_dmi_access(dut.isck0, 80_MB, 4_MB);
do_dmi_access(dut.isck1, 0 - 1_MB, 1_kB);
do_dmi_access(dut.isck1, 1_kB - 1_MB, 1_kB);
do_dmi_access(dut.isck1, 16_MB - 1_MB, 16_MB);
do_dmi_access(dut.isck1, 32_MB - 1_MB, 16_MB);
do_dmi_access(dut.isck1, 48_MB - 1_MB, 4_MB);
sc_start(dut.clk.read());
}
} // namespace scc

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@@ -0,0 +1,60 @@
#ifndef _TESTBENCH_H_
#define _TESTBENCH_H_
#include <cxs/cxs_tlm.h>
#include <scc/cci_util.h>
#include <scc/configurer.h>
#include <scc/memory.h>
#include <scc/router.h>
#include <scc/observer.h>
#include <scc/sc_variable.h>
#include <scc/tracer.h>
#include <string>
#include <systemc>
#include <tlm/scc/initiator_mixin.h>
using namespace sc_core;
using namespace sc_dt;
using namespace std;
namespace scc {
const char* sc_gen_unique_name(const char*, bool preserve_first);
struct testbench : public sc_core::sc_module {
using transaction_type = tlm::tlm_base_protocol_types::tlm_payload_type;
using phase_type = tlm::tlm_base_protocol_types::tlm_phase_type;
sc_core::sc_signal<sc_core::sc_time> clk{"clk"};
sc_core::sc_signal<bool> rst{"rst"};
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<scc::LT>> isck0{"isck0"};
tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<scc::LT>> isck1{"isck1"};
scc::router<scc::LT> router{"router", 5, 2};
scc::memory_tl<1_kB, scc::LT> mem0{"mem0"};
scc::memory_tl<1_kB, scc::LT> mem1{"mem1"};
scc::memory_tl<18_MB, scc::LT> mem2{"mem2"};
scc::memory_tl<24_MB, scc::LT> mem3{"mem3"};
scc::memory_tl<88_MB, scc::LT> mem4{"mem4"};
testbench()
: testbench(sc_core::sc_gen_unique_name("testbench", false)) {}
testbench(sc_core::sc_module_name const& nm)
: sc_module(nm) {
isck0(router.target[0]);
isck1(router.target[1]);
router.set_initiator_base(1, 1_MB);
router.bind_target(mem0.target, 0, 0, 1_kB);
router.bind_target(mem1.target, 1, 1_kB, 1_kB);
router.bind_target(mem2.target, 2, 16_MB, 16_MB);
router.bind_target(mem3.target, 3, 32_MB, 20_MB);
router.bind_target(mem4.target, 4, 64_MB, 20_MB, false);
mem0.clk_i(clk);
mem1.clk_i(clk);
mem2.clk_i(clk);
mem3.clk_i(clk);
mem4.clk_i(clk);
}
void start_of_simulation() { clk = 10_ns; }
};
} // namespace scc
#endif // _TESTBENCH_H_