updates scc and adds scc::memory tests
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@@ -59,7 +59,7 @@ include(CTest)
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include(Catch)
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enable_testing()
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set(WITH_SCP4SCC ON)
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add_subdirectory(scc)
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add_subdirectory(src)
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add_subdirectory(tests)
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@@ -10,7 +10,7 @@ class Pkg(ConanFile):
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"CMakeDeps"
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)
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default_options = {
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"llvm-core/*:targets": "X86",
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"systemc/*:shared": "True",
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"boost/*:fPIC": "True",
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"boost/*:header_only": "False",
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"boost/*:without_contract": "True",
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@@ -32,7 +32,6 @@ class Pkg(ConanFile):
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"boost/*:without_timer": "True",
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"boost/*:without_type_erasure": "True",
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"boost/*:without_wave": "True",
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"systemc/*:shared": "True"
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}
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def requirements(self):
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@@ -46,8 +45,6 @@ class Pkg(ConanFile):
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self.requires("jsoncpp/1.9.5")
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self.requires("zlib/1.2.12")
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self.requires("rapidjson/cci.20230929")
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if "WITH_LLVM" in os.environ:
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self.requires("llvm-core/19.1.7")
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if os.path.isdir("tgc-iss/dbt-rise-plugins"):
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self.requires("lua/5.4.3")
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2
scc
2
scc
Submodule scc updated: 2ab9bcda69...c8536918fe
@@ -10,6 +10,7 @@ add_subdirectory(configurer)
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add_subdirectory(sc_fixed_tracing)
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add_subdirectory(cxs_tlm)
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add_subdirectory(tlm_memory)
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add_subdirectory(memory_subsys)
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add_subdirectory(sim_speed)
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if(FULL_TEST_SUITE)
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add_subdirectory(sim_performance)
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@@ -29,7 +29,7 @@ template <unsigned PHIT_WIDTH> struct testbench : public sc_core::sc_module {
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cxs_transmitter<PHIT_WIDTH> tx{"tx"};
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cxs_channel<PHIT_WIDTH> cxs_chan{"cxs_chan"};
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cxs_receiver<PHIT_WIDTH> rx{"rx"};
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tlm::nw::target_mixin<cxs_pkt_target_socket<>, cxs_packet_types> tsck{"tsck"};
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tlm::nw::target_mixin<cxs_pkt_target_socket<>, false, cxs_packet_types> tsck{"tsck"};
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testbench()
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: testbench(sc_core::sc_gen_unique_name("testbench", false)) {}
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8
tests/memory_subsys/CMakeLists.txt
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8
tests/memory_subsys/CMakeLists.txt
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@@ -0,0 +1,8 @@
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project (memory_subsys)
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add_executable(${PROJECT_NAME}
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memory_test.cpp
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${test_util_SOURCE_DIR}/sc_main.cpp
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)
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target_link_libraries (${PROJECT_NAME} PUBLIC scc::components test_util)
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catch_discover_tests(${PROJECT_NAME})
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72
tests/memory_subsys/memory_test.cpp
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72
tests/memory_subsys/memory_test.cpp
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@@ -0,0 +1,72 @@
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#include "testbench.h"
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#include <factory.h>
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#include <tlm/scc/tlm_gp_shared.h>
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#undef CHECK
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#include <array>
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#include <catch2/catch_all.hpp>
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#include <cstdint>
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#include <deque>
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#include <unordered_map>
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using namespace sc_core;
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namespace scc {
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factory::add<testbench> tb;
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template <typename T> void prepare_trans(tlm::tlm_generic_payload& trans, tlm::tlm_command cmd, uint64_t addr, T val) {
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unsigned len = cmd == tlm::TLM_IGNORE_COMMAND ? 0 : sizeof(val);
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unsigned char* data = len ? new unsigned char[len] : nullptr;
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if(cmd == tlm::TLM_WRITE_COMMAND) {
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memcpy(data, &val, len);
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trans.set_command(cmd);
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}
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if(cmd == tlm::TLM_READ_COMMAND) {
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memset(data, 0, len);
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trans.set_command(tlm::TLM_READ_COMMAND);
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}
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trans.set_address(addr);
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trans.set_data_ptr(data);
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trans.set_data_length(len);
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trans.set_streaming_width(len);
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trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE);
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}
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template<typename T>
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void do_dmi_access(T& isck, uint64_t address, uint64_t expected_size) {
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tlm::tlm_generic_payload gp;
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tlm::tlm_dmi dmi;
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gp.set_address(address);
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auto res = isck->get_direct_mem_ptr(gp, dmi);
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REQUIRE(res == true);
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REQUIRE(dmi.get_start_address() == address);
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REQUIRE(dmi.get_end_address() == (address + expected_size-1));
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REQUIRE(dmi.is_read_write_allowed());
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}
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TEST_CASE("simple_read_write_with host memory map", "[memory][tlm-level]") {
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auto& dut = factory::get<testbench>();
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std::array<unsigned char, 256> ref_data;
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auto val = 256;
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for(auto& e : ref_data)
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e = --val;
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dut.rst.write(true);
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sc_start(10 * dut.clk.read());
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dut.rst.write(false);
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sc_start(dut.clk.read());
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do_dmi_access(dut.isck0, 0, 1_kB);
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do_dmi_access(dut.isck0, 1_kB, 1_kB);
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do_dmi_access(dut.isck0, 16_MB, 16_MB);
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do_dmi_access(dut.isck0, 32_MB, 16_MB);
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do_dmi_access(dut.isck0, 48_MB, 4_MB);
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do_dmi_access(dut.isck0, 64_MB, 16_MB);
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do_dmi_access(dut.isck0, 80_MB, 4_MB);
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do_dmi_access(dut.isck1, 0 - 1_MB, 1_kB);
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do_dmi_access(dut.isck1, 1_kB - 1_MB, 1_kB);
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do_dmi_access(dut.isck1, 16_MB - 1_MB, 16_MB);
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do_dmi_access(dut.isck1, 32_MB - 1_MB, 16_MB);
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do_dmi_access(dut.isck1, 48_MB - 1_MB, 4_MB);
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sc_start(dut.clk.read());
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}
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} // namespace scc
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60
tests/memory_subsys/testbench.h
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60
tests/memory_subsys/testbench.h
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@@ -0,0 +1,60 @@
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#ifndef _TESTBENCH_H_
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#define _TESTBENCH_H_
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#include <cxs/cxs_tlm.h>
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#include <scc/cci_util.h>
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#include <scc/configurer.h>
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#include <scc/memory.h>
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#include <scc/router.h>
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#include <scc/observer.h>
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#include <scc/sc_variable.h>
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#include <scc/tracer.h>
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#include <string>
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#include <systemc>
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#include <tlm/scc/initiator_mixin.h>
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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namespace scc {
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const char* sc_gen_unique_name(const char*, bool preserve_first);
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struct testbench : public sc_core::sc_module {
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using transaction_type = tlm::tlm_base_protocol_types::tlm_payload_type;
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using phase_type = tlm::tlm_base_protocol_types::tlm_phase_type;
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sc_core::sc_signal<sc_core::sc_time> clk{"clk"};
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sc_core::sc_signal<bool> rst{"rst"};
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<scc::LT>> isck0{"isck0"};
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tlm::scc::initiator_mixin<tlm::tlm_initiator_socket<scc::LT>> isck1{"isck1"};
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scc::router<scc::LT> router{"router", 5, 2};
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scc::memory_tl<1_kB, scc::LT> mem0{"mem0"};
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scc::memory_tl<1_kB, scc::LT> mem1{"mem1"};
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scc::memory_tl<18_MB, scc::LT> mem2{"mem2"};
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scc::memory_tl<24_MB, scc::LT> mem3{"mem3"};
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scc::memory_tl<88_MB, scc::LT> mem4{"mem4"};
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testbench()
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: testbench(sc_core::sc_gen_unique_name("testbench", false)) {}
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testbench(sc_core::sc_module_name const& nm)
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: sc_module(nm) {
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isck0(router.target[0]);
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isck1(router.target[1]);
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router.set_initiator_base(1, 1_MB);
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router.bind_target(mem0.target, 0, 0, 1_kB);
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router.bind_target(mem1.target, 1, 1_kB, 1_kB);
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router.bind_target(mem2.target, 2, 16_MB, 16_MB);
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router.bind_target(mem3.target, 3, 32_MB, 20_MB);
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router.bind_target(mem4.target, 4, 64_MB, 20_MB, false);
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mem0.clk_i(clk);
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mem1.clk_i(clk);
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mem2.clk_i(clk);
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mem3.clk_i(clk);
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mem4.clk_i(clk);
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}
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void start_of_simulation() { clk = 10_ns; }
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};
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} // namespace scc
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#endif // _TESTBENCH_H_
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