From 22a8890f74a99a427e82f3202d4773e86bd71397 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Fri, 29 Aug 2025 07:39:28 +0200 Subject: [PATCH] updates scc and adds scc::memory tests --- CMakeLists.txt | 2 +- conanfile.py | 5 +- scc | 2 +- tests/CMakeLists.txt | 1 + tests/cxs_tlm/testbench.h | 2 +- tests/memory_subsys/CMakeLists.txt | 8 ++++ tests/memory_subsys/memory_test.cpp | 72 +++++++++++++++++++++++++++++ tests/memory_subsys/testbench.h | 60 ++++++++++++++++++++++++ 8 files changed, 145 insertions(+), 7 deletions(-) create mode 100644 tests/memory_subsys/CMakeLists.txt create mode 100644 tests/memory_subsys/memory_test.cpp create mode 100644 tests/memory_subsys/testbench.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 30fb7c7..8be6969 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -59,7 +59,7 @@ include(CTest) include(Catch) enable_testing() - +set(WITH_SCP4SCC ON) add_subdirectory(scc) add_subdirectory(src) add_subdirectory(tests) diff --git a/conanfile.py b/conanfile.py index d187926..9be5614 100644 --- a/conanfile.py +++ b/conanfile.py @@ -10,7 +10,7 @@ class Pkg(ConanFile): "CMakeDeps" ) default_options = { - "llvm-core/*:targets": "X86", + "systemc/*:shared": "True", "boost/*:fPIC": "True", "boost/*:header_only": "False", "boost/*:without_contract": "True", @@ -32,7 +32,6 @@ class Pkg(ConanFile): "boost/*:without_timer": "True", "boost/*:without_type_erasure": "True", "boost/*:without_wave": "True", - "systemc/*:shared": "True" } def requirements(self): @@ -46,8 +45,6 @@ class Pkg(ConanFile): self.requires("jsoncpp/1.9.5") self.requires("zlib/1.2.12") self.requires("rapidjson/cci.20230929") - if "WITH_LLVM" in os.environ: - self.requires("llvm-core/19.1.7") if os.path.isdir("tgc-iss/dbt-rise-plugins"): self.requires("lua/5.4.3") diff --git a/scc b/scc index 2ab9bcd..c853691 160000 --- a/scc +++ b/scc @@ -1 +1 @@ -Subproject commit 2ab9bcda6911387ce53b480072fb345c1f5531cf +Subproject commit c8536918fe9ee8d83d339702c441cea28bae6b61 diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 8976ad1..0982470 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -10,6 +10,7 @@ add_subdirectory(configurer) add_subdirectory(sc_fixed_tracing) add_subdirectory(cxs_tlm) add_subdirectory(tlm_memory) +add_subdirectory(memory_subsys) add_subdirectory(sim_speed) if(FULL_TEST_SUITE) add_subdirectory(sim_performance) diff --git a/tests/cxs_tlm/testbench.h b/tests/cxs_tlm/testbench.h index 00d99b9..5ef8617 100644 --- a/tests/cxs_tlm/testbench.h +++ b/tests/cxs_tlm/testbench.h @@ -29,7 +29,7 @@ template struct testbench : public sc_core::sc_module { cxs_transmitter tx{"tx"}; cxs_channel cxs_chan{"cxs_chan"}; cxs_receiver rx{"rx"}; - tlm::nw::target_mixin, cxs_packet_types> tsck{"tsck"}; + tlm::nw::target_mixin, false, cxs_packet_types> tsck{"tsck"}; testbench() : testbench(sc_core::sc_gen_unique_name("testbench", false)) {} diff --git a/tests/memory_subsys/CMakeLists.txt b/tests/memory_subsys/CMakeLists.txt new file mode 100644 index 0000000..dcb948a --- /dev/null +++ b/tests/memory_subsys/CMakeLists.txt @@ -0,0 +1,8 @@ +project (memory_subsys) +add_executable(${PROJECT_NAME} + memory_test.cpp + ${test_util_SOURCE_DIR}/sc_main.cpp +) +target_link_libraries (${PROJECT_NAME} PUBLIC scc::components test_util) + +catch_discover_tests(${PROJECT_NAME}) diff --git a/tests/memory_subsys/memory_test.cpp b/tests/memory_subsys/memory_test.cpp new file mode 100644 index 0000000..e5ac162 --- /dev/null +++ b/tests/memory_subsys/memory_test.cpp @@ -0,0 +1,72 @@ + +#include "testbench.h" +#include +#include +#undef CHECK +#include +#include +#include +#include +#include + +using namespace sc_core; +namespace scc { +factory::add tb; + +template void prepare_trans(tlm::tlm_generic_payload& trans, tlm::tlm_command cmd, uint64_t addr, T val) { + unsigned len = cmd == tlm::TLM_IGNORE_COMMAND ? 0 : sizeof(val); + unsigned char* data = len ? new unsigned char[len] : nullptr; + if(cmd == tlm::TLM_WRITE_COMMAND) { + memcpy(data, &val, len); + trans.set_command(cmd); + } + if(cmd == tlm::TLM_READ_COMMAND) { + memset(data, 0, len); + trans.set_command(tlm::TLM_READ_COMMAND); + } + trans.set_address(addr); + trans.set_data_ptr(data); + trans.set_data_length(len); + trans.set_streaming_width(len); + trans.set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); +} + +template +void do_dmi_access(T& isck, uint64_t address, uint64_t expected_size) { + tlm::tlm_generic_payload gp; + tlm::tlm_dmi dmi; + gp.set_address(address); + auto res = isck->get_direct_mem_ptr(gp, dmi); + REQUIRE(res == true); + REQUIRE(dmi.get_start_address() == address); + REQUIRE(dmi.get_end_address() == (address + expected_size-1)); + REQUIRE(dmi.is_read_write_allowed()); +} + +TEST_CASE("simple_read_write_with host memory map", "[memory][tlm-level]") { + auto& dut = factory::get(); + std::array ref_data; + auto val = 256; + for(auto& e : ref_data) + e = --val; + dut.rst.write(true); + sc_start(10 * dut.clk.read()); + dut.rst.write(false); + sc_start(dut.clk.read()); + + do_dmi_access(dut.isck0, 0, 1_kB); + do_dmi_access(dut.isck0, 1_kB, 1_kB); + do_dmi_access(dut.isck0, 16_MB, 16_MB); + do_dmi_access(dut.isck0, 32_MB, 16_MB); + do_dmi_access(dut.isck0, 48_MB, 4_MB); + do_dmi_access(dut.isck0, 64_MB, 16_MB); + do_dmi_access(dut.isck0, 80_MB, 4_MB); + do_dmi_access(dut.isck1, 0 - 1_MB, 1_kB); + do_dmi_access(dut.isck1, 1_kB - 1_MB, 1_kB); + do_dmi_access(dut.isck1, 16_MB - 1_MB, 16_MB); + do_dmi_access(dut.isck1, 32_MB - 1_MB, 16_MB); + do_dmi_access(dut.isck1, 48_MB - 1_MB, 4_MB); + sc_start(dut.clk.read()); +} + +} // namespace scc diff --git a/tests/memory_subsys/testbench.h b/tests/memory_subsys/testbench.h new file mode 100644 index 0000000..363e1df --- /dev/null +++ b/tests/memory_subsys/testbench.h @@ -0,0 +1,60 @@ +#ifndef _TESTBENCH_H_ +#define _TESTBENCH_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +using namespace sc_core; +using namespace sc_dt; +using namespace std; +namespace scc { + +const char* sc_gen_unique_name(const char*, bool preserve_first); +struct testbench : public sc_core::sc_module { + + using transaction_type = tlm::tlm_base_protocol_types::tlm_payload_type; + using phase_type = tlm::tlm_base_protocol_types::tlm_phase_type; + + sc_core::sc_signal clk{"clk"}; + sc_core::sc_signal rst{"rst"}; + tlm::scc::initiator_mixin> isck0{"isck0"}; + tlm::scc::initiator_mixin> isck1{"isck1"}; + scc::router router{"router", 5, 2}; + scc::memory_tl<1_kB, scc::LT> mem0{"mem0"}; + scc::memory_tl<1_kB, scc::LT> mem1{"mem1"}; + scc::memory_tl<18_MB, scc::LT> mem2{"mem2"}; + scc::memory_tl<24_MB, scc::LT> mem3{"mem3"}; + scc::memory_tl<88_MB, scc::LT> mem4{"mem4"}; + + testbench() + : testbench(sc_core::sc_gen_unique_name("testbench", false)) {} + + testbench(sc_core::sc_module_name const& nm) + : sc_module(nm) { + isck0(router.target[0]); + isck1(router.target[1]); + router.set_initiator_base(1, 1_MB); + router.bind_target(mem0.target, 0, 0, 1_kB); + router.bind_target(mem1.target, 1, 1_kB, 1_kB); + router.bind_target(mem2.target, 2, 16_MB, 16_MB); + router.bind_target(mem3.target, 3, 32_MB, 20_MB); + router.bind_target(mem4.target, 4, 64_MB, 20_MB, false); + mem0.clk_i(clk); + mem1.clk_i(clk); + mem2.clk_i(clk); + mem3.clk_i(clk); + mem4.clk_i(clk); + } + void start_of_simulation() { clk = 10_ns; } +}; +} // namespace scc +#endif // _TESTBENCH_H_