mirror of
https://github.com/Minres/RISCV-VP.git
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94 lines
3.2 KiB
C++
94 lines
3.2 KiB
C++
/*
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* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SRC_VP_SYSTEM_H_
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#define SRC_VP_SYSTEM_H_
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#include <cci_configuration>
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#include <minres/aclint.h>
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#include <minres/ethmac.h>
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#include <minres/gpio.h>
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#include <minres/irq.h>
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#include <minres/qspi.h>
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#include <minres/timer.h>
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#include <minres/uart.h>
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#include <scc/memory.h>
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#include <scc/router.h>
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#include <scc/utilities.h>
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#include <sysc/communication/sc_clock.h>
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#include <sysc/communication/sc_signal.h>
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#include <sysc/communication/sc_signal_ports.h>
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#include <sysc/core_complex.h>
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#include <sysc/kernel/sc_module.h>
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#include <sysc/kernel/sc_time.h>
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#include <sysc/utils/sc_vector.h>
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#include <tlm/scc/quantum_keeper.h>
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#include <tlm/scc/tlm_signal_sockets.h>
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namespace vp {
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class system : public sc_core::sc_module {
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public:
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enum { CLINT_IRQ_SIZE = 32, CLUSTER_ID = 0 };
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sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o", 32};
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sc_core::sc_vector<sc_core::sc_out<bool>> pins_oe_o{"pins_oe_o", 32};
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sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
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sc_core::sc_out<bool> uart0_tx_o{"uart0_tx_o"};
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sc_core::sc_in<bool> uart0_rx_i{"uart0_rx_i"};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
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sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
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spi::spi_pkt_initiator_socket<> mspi0{"mspi0"};
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eth::eth_pkt_initiator_socket<> eth0_tx{"eth0_tx"};
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eth::eth_pkt_target_socket<> eth0_rx{"eth0_rx"};
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eth::eth_pkt_initiator_socket<> eth1_tx{"eth1_tx"};
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eth::eth_pkt_target_socket<> eth1_rx{"eth1_rx"};
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cci::cci_param<std::string> trace_dump_file{"trace_dump_file", ""};
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sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
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sc_core::sc_in<bool> erst_n{"erst_n"};
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system(sc_core::sc_module_name nm);
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private:
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#include "../vp/gen/PipelinedMemoryBusToApbBridge.h" // IWYU pragma: keep
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sysc::riscv::core_complex<> core_complex{"core_complex"};
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scc::router<> main_bus, peripheral_bus;
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vpvper::minres::gpio_tl gpio0{"gpio0"};
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vpvper::minres::uart_tl uart0{"uart0"};
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vpvper::minres::timer_tl timer0{"timer0"};
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vpvper::minres::aclint_tl aclint{"aclint"};
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vpvper::minres::qspi_tl qspi{"qspi"};
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vpvper::minres::ethmac_tl eth0{"eth0"};
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vpvper::minres::ethmac_tl eth1{"eth1"};
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scc::memory<256_kB, scc::LT> mem_ram{"mem_ram"};
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scc::memory<1_GB, scc::LT> mem_dram{"mem_dram"};
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scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"};
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scc::memory<1_MiB, scc::LT> mem_trace{"mem_trace"};
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sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"};
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template <typename T> using vp_signal = sc_core::sc_signal<T, sc_core::SC_MANY_WRITERS>;
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vp_signal<bool> rst_s{"rst_s"};
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sc_core::sc_vector<vp_signal<bool>> clint_int_s{"clint_int_s", 0};
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sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"};
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sc_core::sc_event_or_list finish_evt_or_list;
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sc_core::sc_event_and_list finish_evt_and_list;
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std::vector<uint8_t> trace_buffer;
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void gen_reset();
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void start_of_simulation() override;
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void end_of_simulation() override;
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};
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} // namespace vp
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#endif /* SRC_VP_SYSTEM_H_ */
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