/*
 * Copyright (c) 2019 -2021 MINRES Technolgies GmbH
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef SRC_VP_SYSTEM_H_
#define SRC_VP_SYSTEM_H_

#include <cci_configuration>
#include <minres/aclint.h>
#include <minres/ethmac.h>
#include <minres/gpio.h>
#include <minres/irq.h>
#include <minres/qspi.h>
#include <minres/timer.h>
#include <minres/uart.h>
#include <scc/memory.h>
#include <scc/router.h>
#include <scc/utilities.h>
#include <sysc/communication/sc_clock.h>
#include <sysc/communication/sc_signal.h>
#include <sysc/communication/sc_signal_ports.h>
#include <sysc/core_complex.h>
#include <sysc/kernel/sc_module.h>
#include <sysc/kernel/sc_time.h>
#include <sysc/utils/sc_vector.h>
#include <tlm/scc/quantum_keeper.h>
#include <tlm/scc/tlm_signal_sockets.h>

namespace vp {

class system : public sc_core::sc_module {
public:
    enum { CLINT_IRQ_SIZE = 32, CLUSTER_ID = 0 };

    sc_core::sc_vector<sc_core::sc_out<bool>> pins_o{"pins_o", 32};
    sc_core::sc_vector<sc_core::sc_out<bool>> pins_oe_o{"pins_oe_o", 32};
    sc_core::sc_vector<sc_core::sc_in<bool>> pins_i{"pins_i", 32};
    sc_core::sc_out<bool> uart0_tx_o{"uart0_tx_o"};
    sc_core::sc_in<bool> uart0_rx_i{"uart0_rx_i"};
    sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
    sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
    spi::spi_pkt_initiator_socket<> mspi0{"mspi0"};
    eth::eth_pkt_initiator_socket<> eth0_tx{"eth0_tx"};
    eth::eth_pkt_target_socket<> eth0_rx{"eth0_rx"};
    eth::eth_pkt_initiator_socket<> eth1_tx{"eth1_tx"};
    eth::eth_pkt_target_socket<> eth1_rx{"eth1_rx"};

    cci::cci_param<std::string> trace_dump_file{"trace_dump_file", ""};

    sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};

    sc_core::sc_in<bool> erst_n{"erst_n"};

    system(sc_core::sc_module_name nm);

private:
#include "../vp/gen/PipelinedMemoryBusToApbBridge.h" // IWYU pragma: keep
    sysc::riscv::core_complex<> core_complex{"core_complex"};
    scc::router<> main_bus, peripheral_bus;
    vpvper::minres::gpio_tl gpio0{"gpio0"};
    vpvper::minres::uart_tl uart0{"uart0"};
    vpvper::minres::timer_tl timer0{"timer0"};
    vpvper::minres::aclint_tl aclint{"aclint"};
    vpvper::minres::qspi_tl qspi{"qspi"};
    vpvper::minres::ethmac_tl eth0{"eth0"};
    vpvper::minres::ethmac_tl eth1{"eth1"};

    scc::memory<256_kB, scc::LT> mem_ram{"mem_ram"};
    scc::memory<1_GB, scc::LT> mem_dram{"mem_dram"};
    scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"};
    scc::memory<1_MiB, scc::LT> mem_trace{"mem_trace"};

    sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"};
    template <typename T> using vp_signal = sc_core::sc_signal<T, sc_core::SC_MANY_WRITERS>;
    vp_signal<bool> rst_s{"rst_s"};

    sc_core::sc_vector<vp_signal<bool>> clint_int_s{"clint_int_s", 0};
    sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"};

    sc_core::sc_event_or_list finish_evt_or_list;
    sc_core::sc_event_and_list finish_evt_and_list;
    std::vector<uint8_t> trace_buffer;

    void gen_reset();
    void start_of_simulation() override;
    void end_of_simulation() override;
};

} // namespace vp

#endif /* SRC_VP_SYSTEM_H_ */