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61 lines
1.6 KiB
Markdown
61 lines
1.6 KiB
Markdown
# RISCV-VP
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A RISC-V VP using VP-VIBES peripherals.
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This VP is based in MINRES TGC series cores and uses CoreDSL to generate the concrete ISS
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of a particular ISA + extensions. The generator approach makes it very flexible and adaptable.
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Since the CoreDSL description is used to generate RTL as well as verification artifacts it
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provides a comprehensive and consistent solution to develop processor cores.
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## Ultra Quick start
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Using gitpod you can run the VP in the cloud. Just visit [Gitpod.io](https://www.gitpod.io/#https://github.com/Minres/RISCV-VP/tree/develop)
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and follow the instructions. After the build finished you can run
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```
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build/src/riscv-vp -f fw/hello-world/prebuilt/hello.elf
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```
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or use ctest:
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```
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cd build
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ctest
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```
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You will see on console the prints of the hello world firmware at fw/hello-world/hello.c
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[](https://gitpod.io/#https://github.com/Minres/RISCV-VP)
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## Build instructions for Linux
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You need to have a C++17 capable compiler, make or Ninja, Python 3, and CMake installed.
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To install conan.io version 2.0 and above (see also http://docs.conan.io/en/latest/installation.html) execute the following:
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```
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python3 -m venv .venv
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. .venv/bin/activate
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pip3 install conan
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conan profile detect
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```
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Building the VP is as simple as:
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```
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cmake -S . -B build/Release --preset Release && cmake --build build/Release -j24
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```
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Building a debug version is analogous:
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```
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cmake -S . -B build/Debug --preset Debug && cmake --build build/Debug -j24
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```
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To build some firmware you need to install a RISC-V toolchain like https://github.com/riscv/riscv-tools.
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