mirror of
https://github.com/Minres/RISCV-VP.git
synced 2025-12-17 08:51:35 +00:00
sets mt core complex
This commit is contained in:
9
.vscode/launch.json
vendored
9
.vscode/launch.json
vendored
@@ -30,6 +30,15 @@
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"arguments": "--isa 'rv32gc|msu_vp' -v INFO --disass -f fw/hello-world/hello.elf -g 10000",
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"openGdbConsole": true
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},
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{
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"type": "gdb",
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"request": "launch",
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"name": "32bit VP",
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"cwd": "${workspaceRoot}",
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"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
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"arguments": "--isa 'rv32gc_msu' -v INFO --disass -f fw/hello-world/hello.elf",
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"initCommands": ["info break"]
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},
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{
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"type": "gdb",
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"request": "launch",
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Submodule dbt-rise-core updated: b0fd6762be...83eb45bb3e
Submodule dbt-rise-riscv updated: 23b00add23...06fe403e69
2
scc
2
scc
Submodule scc updated: badc373aae...658e19539a
@@ -20,7 +20,7 @@
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#include <sysc/communication/sc_clock.h>
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#include <sysc/communication/sc_signal.h>
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#include <sysc/communication/sc_signal_ports.h>
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#include <sysc/core_complex.h>
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#include <sysc/core_complex_mt.h>
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#include <sysc/kernel/sc_module.h>
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#include <sysc/kernel/sc_time.h>
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#include <sysc/utils/sc_vector.h>
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@@ -48,7 +48,7 @@ public:
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system(sc_core::sc_module_name nm);
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private:
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sysc::riscv::core_complex<scc::LT, tlm::scc::quantumkeeper_mt> core_complex{"core_complex"};
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sysc::riscv::core_complex_mt<> core_complex{"core_complex"};
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scc::router<> ahb_router, apbBridge;
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vpvper::minres::gpio_tl gpio0{"gpio0"};
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vpvper::minres::uart_tl uart0{"uart0"};
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