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sets mt core complex

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This commit is contained in:
Eyck Jentzsch
2025-10-07 16:18:17 +02:00
parent 39ea27ee08
commit fc66bcbf48
5 changed files with 14 additions and 5 deletions
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9
.vscode/launch.json vendored
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@@ -30,6 +30,15 @@
"arguments": "--isa 'rv32gc|msu_vp' -v INFO --disass -f fw/hello-world/hello.elf -g 10000", "arguments": "--isa 'rv32gc|msu_vp' -v INFO --disass -f fw/hello-world/hello.elf -g 10000",
"openGdbConsole": true "openGdbConsole": true
}, },
{
"type": "gdb",
"request": "launch",
"name": "32bit VP",
"cwd": "${workspaceRoot}",
"program": "${workspaceFolder}/build/Debug/src/riscv-vp",
"arguments": "--isa 'rv32gc_msu' -v INFO --disass -f fw/hello-world/hello.elf",
"initCommands": ["info break"]
},
{ {
"type": "gdb", "type": "gdb",
"request": "launch", "request": "launch",

2
dbt-rise-core

Submodule dbt-rise-core updated: b0fd6762be...83eb45bb3e

2
dbt-rise-riscv

Submodule dbt-rise-riscv updated: 23b00add23...06fe403e69

2
scc

Submodule scc updated: badc373aae...658e19539a

4
src/vp/system.h
View File

@@ -20,7 +20,7 @@
#include <sysc/communication/sc_clock.h> #include <sysc/communication/sc_clock.h>
#include <sysc/communication/sc_signal.h> #include <sysc/communication/sc_signal.h>
#include <sysc/communication/sc_signal_ports.h> #include <sysc/communication/sc_signal_ports.h>
#include <sysc/core_complex.h> #include <sysc/core_complex_mt.h>
#include <sysc/kernel/sc_module.h> #include <sysc/kernel/sc_module.h>
#include <sysc/kernel/sc_time.h> #include <sysc/kernel/sc_time.h>
#include <sysc/utils/sc_vector.h> #include <sysc/utils/sc_vector.h>
@@ -48,7 +48,7 @@ public:
system(sc_core::sc_module_name nm); system(sc_core::sc_module_name nm);
private: private:
sysc::riscv::core_complex<scc::LT, tlm::scc::quantumkeeper_mt> core_complex{"core_complex"}; sysc::riscv::core_complex_mt<> core_complex{"core_complex"};
scc::router<> ahb_router, apbBridge; scc::router<> ahb_router, apbBridge;
vpvper::minres::gpio_tl gpio0{"gpio0"}; vpvper::minres::gpio_tl gpio0{"gpio0"};
vpvper::minres::uart_tl uart0{"uart0"}; vpvper::minres::uart_tl uart0{"uart0"};