adds ethernet peripherals

.gitignore

@@ -26,3 +26,4 @@ CMakeSettings.json
 /install
 .gdb_history
 /dbt-rise-custom
+*.pcap

.gitmodules

@@ -1,6 +1,6 @@
 [submodule "scc"]
 	path = scc
-	url = https://github.com/VP-Vibes/SystemC-Components.git
+	url = https://github.com/Minres/SystemC-Components.git
 [submodule "vpvper"]
 	path = vpvper
 	url = https://github.com/VP-Vibes/VPV-Peripherals.git

src/vp/gen/PipelinedMemoryBusToApbBridge.h

@@ -11,12 +11,11 @@
 
 // need double braces, see
 // https://stackoverflow.com/questions/6893700/how-to-construct-stdarray-object-with-initializer-list#6894191
-const std::array<scc::target_memory_map_entry<scc::LT>, 7> PipelinedMemoryBusToApbBridge_map = {{
+const std::array<scc::target_memory_map_entry<scc::LT>, 6> PipelinedMemoryBusToApbBridge_map = {{
     {gpio0.socket, 0x0, 0xc},
     {uart0.socket, 0x1000, 0x14},
     {timer0.socket, 0x20000, 0x1c},
     {aclint.socket, 0x30000, 0xc000},
-    {irq_ctrl.socket, 0x40000, 0x8},
     {qspi.socket, 0x50000, 0x5c},
     {boot_rom.target, 0x80000, 0x2000},
 }};

src/vp/system.cpp

@@ -14,6 +14,19 @@ namespace vp {
 using namespace sc_core;
 using namespace vpvper::minres;
 
+#define UART0_IRQ 16
+#define TIMER0_IRQ0 17
+#define TIMER0_IRQ1 18
+#define QSPI_IRQ 19
+#define I2S_IRQ 20
+#define CAM_IRQ 21
+#define DMA_IRQ 22
+#define GPIO_ORQ 23
+#define ETH0_IRQ 24
+#define ETH1_IRQ 25
+#define MDIO0_IRQ 26
+#define MDIO1_IRQ 27
+
 system::system(sc_core::sc_module_name nm)
 : sc_core::sc_module(nm)
 , NAMED(ahb_router, 5, 2)
@@ -39,7 +52,6 @@ system::system(sc_core::sc_module_name nm)
     uart0.clk_i(clk_i);
     timer0.clk_i(clk_i);
     aclint.clk_i(clk_i);
-    irq_ctrl.clk_i(clk_i);
     qspi.clk_i(clk_i);
     core_complex.clk_i(clk_i);
     // mem_ram.clk_i(clk_i);
@@ -50,7 +62,6 @@ system::system(sc_core::sc_module_name nm)
     uart0.rst_i(rst_s);
     timer0.rst_i(rst_s);
     aclint.rst_i(rst_s);
-    irq_ctrl.rst_i(rst_s);
     qspi.rst_i(rst_s);
     core_complex.rst_i(rst_s);
     eth0.rst_i(rst_s);
@@ -60,13 +71,19 @@ system::system(sc_core::sc_module_name nm)
     aclint.mtime_o(mtime_s);
     aclint.mtime_int_o[0](clint_int_s[sysc::riscv::TIMER_IRQ]);
     aclint.msip_int_o[0](clint_int_s[sysc::riscv::SW_IRQ]);
-    irq_ctrl.irq_o(clint_int_s[sysc::riscv::EXT_IRQ]);
-    irq_ctrl.pending_irq_i(irq_int_s);
 
-    uart0.irq_o(irq_int_s[0]);
+    uart0.irq_o(clint_int_s[UART0_IRQ]);
-    timer0.interrupt_o[0](irq_int_s[1]);
+    timer0.interrupt_o[0](clint_int_s[TIMER0_IRQ0]);
-    timer0.interrupt_o[1](irq_int_s[2]);
+    timer0.interrupt_o[1](clint_int_s[TIMER0_IRQ1]);
-    qspi.irq_o(irq_int_s[3]);
+    qspi.irq_o(clint_int_s[QSPI_IRQ]);
+    eth0.eth_tx(eth0_tx);
+    eth0_rx(eth0.eth_rx);
+    eth1.eth_tx(eth1_tx);
+    eth1_rx(eth1.eth_rx);
+    eth0.irq_o[0](clint_int_s[ETH0_IRQ]);
+    eth1.irq_o[0](clint_int_s[ETH1_IRQ]);
+    eth0.irq_o[1](clint_int_s[MDIO0_IRQ]);
+    eth1.irq_o[1](clint_int_s[MDIO1_IRQ]);
 
     core_complex.mtime_i(mtime_s);
     core_complex.clint_irq_i(clint_int_s);

src/vp/system.h

@@ -42,6 +42,10 @@ public:
     sc_core::sc_vector<sc_core::sc_in<bool>> t0_clear_i{"t0_clear_i", vpvper::minres::timer::CLEAR_CNT};
     sc_core::sc_vector<sc_core::sc_in<bool>> t0_tick_i{"t0_tick_i", vpvper::minres::timer::TICK_CNT - 1};
     spi::spi_pkt_initiator_socket<> mspi0{"mspi0"};
+    eth::eth_pkt_initiator_socket<> eth0_tx{"eth0_tx"};
+    eth::eth_pkt_target_socket<> eth0_rx{"eth0_rx"};
+    eth::eth_pkt_initiator_socket<> eth1_tx{"eth1_tx"};
+    eth::eth_pkt_target_socket<> eth1_rx{"eth1_rx"};
 
     sc_core::sc_in<sc_core::sc_time> clk_i{"clk_i"};
 
@@ -57,10 +61,9 @@ private:
     vpvper::minres::uart_tl uart0{"uart0"};
     vpvper::minres::timer_tl timer0{"timer0"};
     vpvper::minres::aclint_tl aclint{"aclint"};
-    vpvper::minres::irq_tl irq_ctrl{"irq_ctrl"};
     vpvper::minres::qspi_tl qspi{"qspi"};
-    vpvper::minres::ethmac eth0{"eth0"};
+    vpvper::minres::ethmac_tl eth0{"eth0"};
-    vpvper::minres::ethmac eth1{"eth1"};
+    vpvper::minres::ethmac_tl eth1{"eth1"};
 
     scc::memory<128_kB, scc::LT> mem_ram{"mem_ram"};
     scc::memory<8_kB, scc::LT> boot_rom{"boot_rom"};
@@ -68,7 +71,6 @@ private:
     sc_core::sc_signal<sc_core::sc_time> mtime_clk{"mtime_clk"};
     sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS> rst_s{"rst_s"};
 
-    sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> irq_int_s{"irq_int_s", 32};
     sc_core::sc_vector<sc_core::sc_signal<bool, sc_core::SC_MANY_WRITERS>> clint_int_s{"clint_int_s", 32};
     sc_core::sc_signal<uint64_t> mtime_s{"mtime_s"};
     void gen_reset();

src/vp/tb.cpp

@@ -22,6 +22,8 @@ tb::tb(const sc_core::sc_module_name& nm)
     top.t0_clear_i(t0_clear_i);
     top.t0_tick_i(t0_tick_i);
     top.mspi0(spi());
+    top.eth0_tx(top.eth1_rx);
+    top.eth1_tx(top.eth0_rx);
     spi(0)(qspi_mem.spi_t);
     top.clk_i(clk_i);
     clk_i = 10_ns;