mirror of
https://github.com/Minres/RISCV-VP.git
synced 2026-02-06 10:02:35 +00:00
114 lines
2.8 KiB
C++
114 lines
2.8 KiB
C++
/*
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* Copyright (c) 2019 -2021 MINRES Technolgies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "system.h"
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#include <minres/timer.h>
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#include <minres/uart.h>
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#include <scc/utilities.h>
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namespace vp {
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using namespace sc_core;
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using namespace vpvper::minres;
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#define UART0_IRQ 16
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#define TIMER0_IRQ0 17
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#define TIMER0_IRQ1 18
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#define QSPI_IRQ 19
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#define I2S_IRQ 20
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#define CAM_IRQ 21
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#define DMA_IRQ 22
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#define GPIO_ORQ 23
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#define ETH0_IRQ 24
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#define ETH1_IRQ 25
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#define MDIO0_IRQ 26
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#define MDIO1_IRQ 27
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system::system(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, NAMED(ahb_router, 5, 2)
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, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) {
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mtime_clk = (1.0 / 32768) * 1_sec;
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core_complex.ibus(ahb_router.target[0]);
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core_complex.dbus(ahb_router.target[1]);
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ahb_router.bind_target(mem_ram.target, 1, 0x00000000, 128_kB);
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ahb_router.bind_target(apbBridge.target[0], 2, 0x10000000, 128_MB);
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ahb_router.bind_target(eth0.socket, 3, 0x18000000, 4_KiB);
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ahb_router.bind_target(eth1.socket, 4, 0x18001000, 4_KiB);
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ahb_router.bind_target(qspi.xip_sck, 0, 0x20000000, 16_MB);
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size_t i = 0;
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for(const auto& e : PipelinedMemoryBusToApbBridge_map) {
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apbBridge.initiator.at(i)(e.target);
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apbBridge.set_target_range(i, e.start, e.size);
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i++;
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}
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gpio0.clk_i(clk_i);
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uart0.clk_i(clk_i);
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timer0.clk_i(clk_i);
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aclint.clk_i(clk_i);
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qspi.clk_i(clk_i);
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core_complex.clk_i(clk_i);
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// mem_ram.clk_i(clk_i);
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eth0.clk_i(clk_i);
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eth1.clk_i(clk_i);
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gpio0.rst_i(rst_s);
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uart0.rst_i(rst_s);
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timer0.rst_i(rst_s);
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aclint.rst_i(rst_s);
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qspi.rst_i(rst_s);
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core_complex.rst_i(rst_s);
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eth0.rst_i(rst_s);
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eth1.rst_i(rst_s);
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aclint.mtime_clk_i(mtime_clk);
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aclint.mtime_o(mtime_s);
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aclint.mtime_int_o[0](clint_int_s[sysc::riscv::TIMER_IRQ]);
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aclint.msip_int_o[0](clint_int_s[sysc::riscv::SW_IRQ]);
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uart0.irq_o(clint_int_s[UART0_IRQ]);
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timer0.interrupt_o[0](clint_int_s[TIMER0_IRQ0]);
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timer0.interrupt_o[1](clint_int_s[TIMER0_IRQ1]);
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qspi.irq_o(clint_int_s[QSPI_IRQ]);
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eth0.eth_tx(eth0_tx);
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eth0_rx(eth0.eth_rx);
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eth1.eth_tx(eth1_tx);
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eth1_rx(eth1.eth_rx);
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eth0.irq_o[0](clint_int_s[ETH0_IRQ]);
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eth1.irq_o[0](clint_int_s[ETH1_IRQ]);
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eth0.irq_o[1](clint_int_s[MDIO0_IRQ]);
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eth1.irq_o[1](clint_int_s[MDIO1_IRQ]);
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core_complex.mtime_i(mtime_s);
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core_complex.clint_irq_i(clint_int_s);
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gpio0.pins_i(pins_i);
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gpio0.pins_o(pins_o);
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gpio0.oe_o(pins_oe_o);
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uart0.tx_o(uart0_tx_o);
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uart0.rx_i(uart0_rx_i);
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timer0.clear_i(t0_clear_i);
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timer0.tick_i(t0_tick_i);
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qspi.spi_i(mspi0);
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SC_METHOD(gen_reset);
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sensitive << erst_n;
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}
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void system::gen_reset() {
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if(erst_n.read())
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rst_s = 0;
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else
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rst_s = 1;
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}
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} // namespace vp
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