mirror of
https://github.com/Minres/RISCV-VP.git
synced 2026-02-06 18:12:36 +00:00
adds ethernet peripherals
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@@ -14,6 +14,19 @@ namespace vp {
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using namespace sc_core;
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using namespace vpvper::minres;
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#define UART0_IRQ 16
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#define TIMER0_IRQ0 17
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#define TIMER0_IRQ1 18
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#define QSPI_IRQ 19
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#define I2S_IRQ 20
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#define CAM_IRQ 21
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#define DMA_IRQ 22
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#define GPIO_ORQ 23
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#define ETH0_IRQ 24
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#define ETH1_IRQ 25
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#define MDIO0_IRQ 26
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#define MDIO1_IRQ 27
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system::system(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, NAMED(ahb_router, 5, 2)
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@@ -39,7 +52,6 @@ system::system(sc_core::sc_module_name nm)
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uart0.clk_i(clk_i);
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timer0.clk_i(clk_i);
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aclint.clk_i(clk_i);
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irq_ctrl.clk_i(clk_i);
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qspi.clk_i(clk_i);
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core_complex.clk_i(clk_i);
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// mem_ram.clk_i(clk_i);
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@@ -50,7 +62,6 @@ system::system(sc_core::sc_module_name nm)
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uart0.rst_i(rst_s);
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timer0.rst_i(rst_s);
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aclint.rst_i(rst_s);
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irq_ctrl.rst_i(rst_s);
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qspi.rst_i(rst_s);
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core_complex.rst_i(rst_s);
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eth0.rst_i(rst_s);
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@@ -60,13 +71,19 @@ system::system(sc_core::sc_module_name nm)
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aclint.mtime_o(mtime_s);
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aclint.mtime_int_o[0](clint_int_s[sysc::riscv::TIMER_IRQ]);
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aclint.msip_int_o[0](clint_int_s[sysc::riscv::SW_IRQ]);
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irq_ctrl.irq_o(clint_int_s[sysc::riscv::EXT_IRQ]);
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irq_ctrl.pending_irq_i(irq_int_s);
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uart0.irq_o(irq_int_s[0]);
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timer0.interrupt_o[0](irq_int_s[1]);
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timer0.interrupt_o[1](irq_int_s[2]);
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qspi.irq_o(irq_int_s[3]);
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uart0.irq_o(clint_int_s[UART0_IRQ]);
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timer0.interrupt_o[0](clint_int_s[TIMER0_IRQ0]);
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timer0.interrupt_o[1](clint_int_s[TIMER0_IRQ1]);
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qspi.irq_o(clint_int_s[QSPI_IRQ]);
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eth0.eth_tx(eth0_tx);
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eth0_rx(eth0.eth_rx);
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eth1.eth_tx(eth1_tx);
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eth1_rx(eth1.eth_rx);
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eth0.irq_o[0](clint_int_s[ETH0_IRQ]);
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eth1.irq_o[0](clint_int_s[ETH1_IRQ]);
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eth0.irq_o[1](clint_int_s[MDIO0_IRQ]);
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eth1.irq_o[1](clint_int_s[MDIO1_IRQ]);
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core_complex.mtime_i(mtime_s);
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core_complex.clint_irq_i(clint_int_s);
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