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https://github.com/Minres/RISCV-VP.git
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adds separate clock for aclints mtime register
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@@ -19,6 +19,8 @@ system::system(sc_core::sc_module_name nm)
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: sc_core::sc_module(nm)
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, NAMED(ahb_router, 3, 2)
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, NAMED(apbBridge, PipelinedMemoryBusToApbBridge_map.size(), 1) {
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mtime_clk = (1.0 / 32768) * 1_sec;
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core_complex.ibus(ahb_router.target[0]);
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core_complex.dbus(ahb_router.target[1]);
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@@ -53,6 +55,7 @@ system::system(sc_core::sc_module_name nm)
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qspi.rst_i(rst_s);
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core_complex.rst_i(rst_s);
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aclint.mtime_clk_i(mtime_clk);
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aclint.mtime_o(mtime_s);
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aclint.mtime_int_o(mtime_int_s);
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aclint.msip_int_o(msip_int_s);
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