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138
Makefile
138
Makefile
@@ -29,16 +29,17 @@ endif
|
||||
ifeq ($(build_dir),$(CURDIR))
|
||||
$(error Build directory is same as source directory.)
|
||||
endif
|
||||
install_root_dir_default=$(CURDIR)/install
|
||||
ifdef I
|
||||
install_dir=$(shell $(READLINK) -f $(I))
|
||||
install_root_dir=$(shell $(READLINK) -f $(I))
|
||||
else
|
||||
install_dir=$(CURDIR)/install
|
||||
install_root_dir=$(install_root_dir_default)/usr
|
||||
endif
|
||||
ifeq ($(install_dir),$(CURDIR))
|
||||
$(error Install directory is same as source directory.)
|
||||
ifeq ($(install_root_dir),$(CURDIR))
|
||||
$(error Install root directory is same as source directory.)
|
||||
endif
|
||||
ifeq ($(install_dir),$(build_dir))
|
||||
$(error Install directory is same as build directory.)
|
||||
ifeq ($(install_root_dir),$(build_dir))
|
||||
$(error Install root directory is same as build directory.)
|
||||
endif
|
||||
ifdef PLATFORM_DIR
|
||||
platform_dir_path=$(shell $(READLINK) -f $(PLATFORM_DIR))
|
||||
@@ -93,6 +94,8 @@ DTC = dtc
|
||||
|
||||
# Guess the compillers xlen
|
||||
OPENSBI_CC_XLEN := $(shell TMP=`$(CC) -dumpmachine | sed 's/riscv\([0-9][0-9]\).*/\1/'`; echo $${TMP})
|
||||
OPENSBI_CC_ABI := $(shell TMP=`$(CC) -v 2>&1 | sed -n 's/.*\(with\-abi=\([a-zA-Z0-9]*\)\).*/\2/p'`; echo $${TMP})
|
||||
OPENSBI_CC_ISA := $(shell TMP=`$(CC) -v 2>&1 | sed -n 's/.*\(with\-arch=\([a-zA-Z0-9]*\)\).*/\2/p'`; echo $${TMP})
|
||||
|
||||
# Setup platform XLEN
|
||||
ifndef PLATFORM_RISCV_XLEN
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||||
@@ -129,7 +132,6 @@ libsbi-objs-path-y=$(foreach obj,$(libsbi-objs-y),$(build_dir)/lib/sbi/$(obj))
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||||
libsbiutils-objs-path-y=$(foreach obj,$(libsbiutils-objs-y),$(build_dir)/lib/utils/$(obj))
|
||||
ifdef PLATFORM
|
||||
platform-objs-path-y=$(foreach obj,$(platform-objs-y),$(platform_build_dir)/$(obj))
|
||||
platform-dtb-path-y=$(foreach obj,$(platform-dtb-y),$(platform_build_dir)/$(obj))
|
||||
firmware-bins-path-y=$(foreach bin,$(firmware-bins-y),$(platform_build_dir)/firmware/$(bin))
|
||||
endif
|
||||
firmware-elfs-path-y=$(firmware-bins-path-y:.bin=.elf)
|
||||
@@ -143,19 +145,54 @@ deps-y+=$(firmware-objs-path-y:.o=.dep)
|
||||
|
||||
# Setup platform ABI, ISA and Code Model
|
||||
ifndef PLATFORM_RISCV_ABI
|
||||
ifeq ($(PLATFORM_RISCV_XLEN), 32)
|
||||
PLATFORM_RISCV_ABI = ilp$(PLATFORM_RISCV_XLEN)
|
||||
ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
|
||||
ifeq ($(PLATFORM_RISCV_XLEN), 32)
|
||||
PLATFORM_RISCV_ABI = ilp$(PLATFORM_RISCV_XLEN)
|
||||
else
|
||||
PLATFORM_RISCV_ABI = lp$(PLATFORM_RISCV_XLEN)
|
||||
endif
|
||||
else
|
||||
PLATFORM_RISCV_ABI = lp$(PLATFORM_RISCV_XLEN)
|
||||
PLATFORM_RISCV_ABI = $(OPENSBI_CC_ABI)
|
||||
endif
|
||||
endif
|
||||
ifndef PLATFORM_RISCV_ISA
|
||||
PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
|
||||
ifneq ($(PLATFORM_RISCV_TOOLCHAIN_DEFAULT), 1)
|
||||
PLATFORM_RISCV_ISA = rv$(PLATFORM_RISCV_XLEN)imafdc
|
||||
else
|
||||
PLATFORM_RISCV_ISA = $(OPENSBI_CC_ISA)
|
||||
endif
|
||||
endif
|
||||
ifndef PLATFORM_RISCV_CODE_MODEL
|
||||
PLATFORM_RISCV_CODE_MODEL = medany
|
||||
endif
|
||||
|
||||
# Setup install directories
|
||||
ifdef INSTALL_INCLUDE_PATH
|
||||
install_include_path=$(INSTALL_INCLUDE_PATH)
|
||||
else
|
||||
install_include_path=include
|
||||
endif
|
||||
ifdef INSTALL_LIB_PATH
|
||||
install_lib_path=$(INSTALL_LIB_PATH)
|
||||
else
|
||||
ifneq ($(origin INSTALL_LIB_SUBDIR), undefined)
|
||||
install_lib_subdir=$(INSTALL_LIB_SUBDIR)
|
||||
else
|
||||
install_lib_subdir=$(PLATFORM_RISCV_ABI)
|
||||
endif
|
||||
install_lib_path=lib$(subst 32,,$(PLATFORM_RISCV_XLEN))/$(install_lib_subdir)
|
||||
endif
|
||||
ifdef INSTALL_FIRMWARE_PATH
|
||||
install_firmware_path=$(INSTALL_FIRMWARE_PATH)
|
||||
else
|
||||
install_firmware_path=share/opensbi/$(PLATFORM_RISCV_ABI)
|
||||
endif
|
||||
ifdef INSTALL_DOCS_PATH
|
||||
install_docs_path=$(INSTALL_DOCS_PATH)
|
||||
else
|
||||
install_docs_path=share/opensbi/docs
|
||||
endif
|
||||
|
||||
# Setup compilation commands flags
|
||||
GENFLAGS = -I$(platform_src_dir)/include
|
||||
GENFLAGS += -I$(include_dir)
|
||||
@@ -199,7 +236,7 @@ MERGEFLAGS += -r
|
||||
MERGEFLAGS += -b elf$(PLATFORM_RISCV_XLEN)-littleriscv
|
||||
MERGEFLAGS += -m elf$(PLATFORM_RISCV_XLEN)lriscv
|
||||
|
||||
DTCFLAGS = -O dtb
|
||||
DTSCPPFLAGS = $(CPPFLAGS) -nostdinc -nostdlib -fno-builtin -D__DTS__ -x assembler-with-cpp
|
||||
|
||||
# Setup functions for compilation
|
||||
define dynamic_flags
|
||||
@@ -215,12 +252,12 @@ copy_file = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
|
||||
echo " COPY $(subst $(build_dir)/,,$(1))"; \
|
||||
cp -f $(2) $(1)
|
||||
inst_file = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
|
||||
echo " INSTALL $(subst $(install_dir)/,,$(1))"; \
|
||||
echo " INSTALL $(subst $(install_root_dir)/,,$(1))"; \
|
||||
cp -f $(2) $(1)
|
||||
inst_file_list = $(CMD_PREFIX)if [ ! -z "$(4)" ]; then \
|
||||
mkdir -p $(1)/$(3); \
|
||||
for file in $(4) ; do \
|
||||
rel_file=`echo $$file | sed -e 's@$(2)/$(3)/@@'`; \
|
||||
rel_file=`echo $$file | sed -e 's@$(2)/$(subst $(install_firmware_path),platform,$(3))@@'`; \
|
||||
dest_file=$(1)"/"$(3)"/"`echo $$rel_file`; \
|
||||
dest_dir=`dirname $$dest_file`; \
|
||||
echo " INSTALL "$(3)"/"`echo $$rel_file`; \
|
||||
@@ -229,7 +266,7 @@ inst_file_list = $(CMD_PREFIX)if [ ! -z "$(4)" ]; then \
|
||||
done \
|
||||
fi
|
||||
inst_header_dir = $(CMD_PREFIX)mkdir -p $(1); \
|
||||
echo " INSTALL $(subst $(install_dir)/,,$(1))"; \
|
||||
echo " INSTALL $(subst $(install_root_dir)/,,$(1))"; \
|
||||
cp -rf $(2) $(1)
|
||||
compile_cpp = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
|
||||
echo " CPP $(subst $(build_dir)/,,$(1))"; \
|
||||
@@ -261,13 +298,21 @@ compile_objcopy = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
|
||||
$(OBJCOPY) -S -O binary $(2) $(1)
|
||||
compile_dts = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
|
||||
echo " DTC $(subst $(build_dir)/,,$(1))"; \
|
||||
$(DTC) $(DTCFLAGS) -o $(1) $(2)
|
||||
$(CPP) $(DTSCPPFLAGS) $(2) | $(DTC) -O dtb -i `dirname $(2)` -o $(1)
|
||||
compile_d2c = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
|
||||
echo " D2C $(subst $(build_dir)/,,$(1))"; \
|
||||
$(if $($(2)-varalign-$(3)),$(eval D2C_ALIGN_BYTES := $($(2)-varalign-$(3))),$(eval D2C_ALIGN_BYTES := $(4))) \
|
||||
$(if $($(2)-varprefix-$(3)),$(eval D2C_NAME_PREFIX := $($(2)-varprefix-$(3))),$(eval D2C_NAME_PREFIX := $(5))) \
|
||||
$(if $($(2)-padding-$(3)),$(eval D2C_PADDING_BYTES := $($(2)-padding-$(3))),$(eval D2C_PADDING_BYTES := 0)) \
|
||||
$(src_dir)/scripts/d2c.sh -i $(6) -a $(D2C_ALIGN_BYTES) -p $(D2C_NAME_PREFIX) -t $(D2C_PADDING_BYTES) > $(1)
|
||||
compile_gen_dep = $(CMD_PREFIX)mkdir -p `dirname $(1)`; \
|
||||
echo " GEN-DEP $(subst $(build_dir)/,,$(1))"; \
|
||||
echo "$(1:.dep=$(2)): $(3)" >> $(1)
|
||||
|
||||
targets-y = $(build_dir)/lib/libsbi.a
|
||||
targets-y += $(build_dir)/lib/libsbiutils.a
|
||||
ifdef PLATFORM
|
||||
targets-y += $(platform_build_dir)/lib/libplatsbi.a
|
||||
targets-y += $(platform-dtb-path-y)
|
||||
endif
|
||||
targets-y += $(firmware-bins-path-y)
|
||||
|
||||
@@ -278,15 +323,6 @@ all: $(targets-y)
|
||||
# Preserve all intermediate files
|
||||
.SECONDARY:
|
||||
|
||||
$(build_dir)/%.bin: $(build_dir)/%.elf
|
||||
$(call compile_objcopy,$@,$<)
|
||||
|
||||
$(build_dir)/%.elf: $(build_dir)/%.o $(build_dir)/%.elf.ld $(platform_build_dir)/lib/libplatsbi.a
|
||||
$(call compile_elf,$@,$@.ld,$< $(platform_build_dir)/lib/libplatsbi.a)
|
||||
|
||||
$(platform_build_dir)/%.ld: $(src_dir)/%.ldS
|
||||
$(call compile_cpp,$@,$<)
|
||||
|
||||
$(build_dir)/lib/libsbi.a: $(libsbi-objs-path-y)
|
||||
$(call compile_ar,$@,$^)
|
||||
|
||||
@@ -308,18 +344,41 @@ $(build_dir)/%.dep: $(src_dir)/%.S
|
||||
$(build_dir)/%.o: $(src_dir)/%.S
|
||||
$(call compile_as,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.bin: $(platform_build_dir)/%.elf
|
||||
$(call compile_objcopy,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.elf: $(platform_build_dir)/%.o $(platform_build_dir)/%.elf.ld $(platform_build_dir)/lib/libplatsbi.a
|
||||
$(call compile_elf,$@,$@.ld,$< $(platform_build_dir)/lib/libplatsbi.a)
|
||||
|
||||
$(platform_build_dir)/%.ld: $(src_dir)/%.ldS
|
||||
$(call compile_cpp,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.dep: $(platform_src_dir)/%.c
|
||||
$(call compile_cc_dep,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.o: $(platform_src_dir)/%.c
|
||||
$(call compile_cc,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.o: $(platform_build_dir)/%.c
|
||||
$(call compile_cc,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.dep: $(platform_src_dir)/%.S
|
||||
$(call compile_as_dep,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.o: $(platform_src_dir)/%.S
|
||||
$(call compile_as,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.dep: $(platform_src_dir)/%.dts
|
||||
$(call compile_gen_dep,$@,.dtb,$<)
|
||||
$(call compile_gen_dep,$@,.c,$(@:.dep=.dtb))
|
||||
$(call compile_gen_dep,$@,.o,$(@:.dep=.c))
|
||||
|
||||
$(platform_build_dir)/%.c: $(platform_build_dir)/%.dtb
|
||||
$(call compile_d2c,$@,platform,$(subst .dtb,.o,$(subst /,-,$(subst $(platform_build_dir)/,,$<))),16,dt,$<)
|
||||
|
||||
$(platform_build_dir)/%.dtb: $(platform_src_dir)/%.dts
|
||||
$(call compile_dts,$@,$<)
|
||||
|
||||
$(platform_build_dir)/%.dep: $(src_dir)/%.c
|
||||
$(call compile_cc_dep,$@,$<)
|
||||
|
||||
@@ -332,9 +391,6 @@ $(platform_build_dir)/%.dep: $(src_dir)/%.S
|
||||
$(platform_build_dir)/%.o: $(src_dir)/%.S
|
||||
$(call compile_as,$@,$<)
|
||||
|
||||
$(build_dir)/%.dtb: $(src_dir)/%.dts
|
||||
$(call compile_dts,$@,$<)
|
||||
|
||||
# Rule for "make docs"
|
||||
$(build_dir)/docs/latex/refman.pdf: $(build_dir)/docs/latex/refman.tex
|
||||
$(CMD_PREFIX)mkdir -p $(build_dir)/docs
|
||||
@@ -385,26 +441,26 @@ install: $(install_targets-y)
|
||||
|
||||
.PHONY: install_libsbi
|
||||
install_libsbi: $(build_dir)/lib/libsbi.a
|
||||
$(call inst_header_dir,$(install_dir)/include,$(include_dir)/sbi)
|
||||
$(call inst_file,$(install_dir)/lib/libsbi.a,$(build_dir)/lib/libsbi.a)
|
||||
$(call inst_header_dir,$(install_root_dir)/$(install_include_path),$(include_dir)/sbi)
|
||||
$(call inst_file,$(install_root_dir)/$(install_lib_path)/libsbi.a,$(build_dir)/lib/libsbi.a)
|
||||
|
||||
.PHONY: install_libsbiutils
|
||||
install_libsbiutils: $(build_dir)/lib/libsbiutils.a
|
||||
$(call inst_header_dir,$(install_dir)/include,$(include_dir)/sbi_utils)
|
||||
$(call inst_file,$(install_dir)/lib/libsbiutils.a,$(build_dir)/lib/libsbiutils.a)
|
||||
$(call inst_header_dir,$(install_root_dir)/$(install_include_path),$(include_dir)/sbi_utils)
|
||||
$(call inst_file,$(install_root_dir)/$(install_lib_path)/libsbiutils.a,$(build_dir)/lib/libsbiutils.a)
|
||||
|
||||
.PHONY: install_libplatsbi
|
||||
install_libplatsbi: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a $(build_dir)/lib/libsbiutils.a
|
||||
$(call inst_file,$(install_dir)/platform/$(platform_subdir)/lib/libplatsbi.a,$(platform_build_dir)/lib/libplatsbi.a)
|
||||
$(call inst_file,$(install_root_dir)/$(install_lib_path)/opensbi/$(platform_subdir)/lib/libplatsbi.a,$(platform_build_dir)/lib/libplatsbi.a)
|
||||
|
||||
.PHONY: install_firmwares
|
||||
install_firmwares: $(platform_build_dir)/lib/libplatsbi.a $(build_dir)/lib/libsbi.a $(build_dir)/lib/libsbiutils.a $(firmware-bins-path-y)
|
||||
$(call inst_file_list,$(install_dir),$(build_dir),platform/$(platform_subdir)/firmware,$(firmware-elfs-path-y))
|
||||
$(call inst_file_list,$(install_dir),$(build_dir),platform/$(platform_subdir)/firmware,$(firmware-bins-path-y))
|
||||
$(call inst_file_list,$(install_root_dir),$(build_dir),$(install_firmware_path)/$(platform_subdir)/firmware,$(firmware-elfs-path-y))
|
||||
$(call inst_file_list,$(install_root_dir),$(build_dir),$(install_firmware_path)/$(platform_subdir)/firmware,$(firmware-bins-path-y))
|
||||
|
||||
.PHONY: install_docs
|
||||
install_docs: $(build_dir)/docs/latex/refman.pdf
|
||||
$(call inst_file,$(install_dir)/docs/refman.pdf,$(build_dir)/docs/latex/refman.pdf)
|
||||
$(call inst_file,$(install_root_dir)/$(install_docs_path)/refman.pdf,$(build_dir)/docs/latex/refman.pdf)
|
||||
|
||||
# Rule for "make clean"
|
||||
.PHONY: clean
|
||||
@@ -418,6 +474,8 @@ clean:
|
||||
$(CMD_PREFIX)find $(build_dir) -type f -name "*.elf" -exec rm -rf {} +
|
||||
$(if $(V), @echo " RM $(build_dir)/*.bin")
|
||||
$(CMD_PREFIX)find $(build_dir) -type f -name "*.bin" -exec rm -rf {} +
|
||||
$(if $(V), @echo " RM $(build_dir)/*.dtb")
|
||||
$(CMD_PREFIX)find $(build_dir) -type f -name "*.dtb" -exec rm -rf {} +
|
||||
|
||||
# Rule for "make distclean"
|
||||
.PHONY: distclean
|
||||
@@ -429,7 +487,7 @@ ifeq ($(build_dir),$(CURDIR)/build)
|
||||
$(if $(V), @echo " RM $(build_dir)")
|
||||
$(CMD_PREFIX)rm -rf $(build_dir)
|
||||
endif
|
||||
ifeq ($(install_dir),$(CURDIR)/install)
|
||||
$(if $(V), @echo " RM $(install_dir)")
|
||||
$(CMD_PREFIX)rm -rf $(install_dir)
|
||||
ifeq ($(install_root_dir),$(install_root_dir_default)/usr)
|
||||
$(if $(V), @echo " RM $(install_root_dir_default)")
|
||||
$(CMD_PREFIX)rm -rf $(install_root_dir_default)
|
||||
endif
|
||||
|
103
README.md
103
README.md
@@ -1,9 +1,41 @@
|
||||
Copyright (c) 2019 Western Digital Corporation or its affiliates
|
||||
and other contributors.
|
||||
|
||||
RISC-V Open Source Supervisor Binary Interface (OpenSBI)
|
||||
========================================================
|
||||
|
||||
Copyright and License
|
||||
---------------------
|
||||
|
||||
The OpenSBI project is copyright (c) 2019 Western Digital Corporation
|
||||
or its affiliates and other contributors.
|
||||
|
||||
It is distributed under the terms of the BSD 2-clause license
|
||||
("Simplified BSD License" or "FreeBSD License", SPDX: *BSD-2-Clause*).
|
||||
A copy of this license with OpenSBI copyright can be found in the file
|
||||
[COPYING.BSD].
|
||||
|
||||
All source files in OpenSBI contain the 2-Clause BSD license SPDX short
|
||||
identifier in place of the full license text.
|
||||
|
||||
```
|
||||
SPDX-License-Identifier: BSD-2-Clause
|
||||
```
|
||||
|
||||
This enables machine processing of license information based on the SPDX
|
||||
License Identifiers that are available on the [SPDX] web site.
|
||||
|
||||
OpenSBI source code also contains code reused from other projects as listed
|
||||
below. The original license text of these projects is included in the source
|
||||
files where the reused code is present.
|
||||
|
||||
* The libfdt source code is disjunctively dual licensed
|
||||
(GPL-2.0+ OR BSD-2-Clause). Some of this project code is used in OpenSBI
|
||||
under the terms of the BSD 2-Clause license. Any contributions to this
|
||||
code must be made under the terms of both licenses.
|
||||
|
||||
See also the [third party notices] file for more information.
|
||||
|
||||
Introduction
|
||||
------------
|
||||
|
||||
The **RISC-V Supervisor Binary Interface (SBI)** is the recommended interface
|
||||
between:
|
||||
|
||||
@@ -13,7 +45,7 @@ between:
|
||||
executing in VS-mode.
|
||||
|
||||
The *RISC-V SBI specification* is maintained as an independent project by the
|
||||
RISC-V Foundation on [Github] (https://github.com/riscv/riscv-sbi-doc).
|
||||
RISC-V Foundation on [Github].
|
||||
|
||||
The goal of the OpenSBI project is to provide an open-source reference
|
||||
implementation of the RISC-V SBI specifications for platform-specific firmwares
|
||||
@@ -37,15 +69,35 @@ platform-dependent hardware manipulation functions. For all supported platforms,
|
||||
OpenSBI also provides several runtime firmware examples built using the platform
|
||||
*libplatsbi.a*. These example firmwares can be used to replace the legacy
|
||||
*riscv-pk* bootloader (aka BBL) and enable the use of well-known bootloaders
|
||||
such as [U-Boot] (https://git.denx.de/u-boot.git).
|
||||
such as [U-Boot].
|
||||
|
||||
Supported SBI version
|
||||
---------------------
|
||||
Currently, OpenSBI fully supports SBI specification *v0.2*. OpenSBI also
|
||||
supports Hart State Management (HSM) SBI extension starting from OpenSBI v0.7.
|
||||
HSM extension allows S-mode software to boot all the harts a defined order
|
||||
rather than legacy method of random booting of harts. As a result, many
|
||||
required features such as CPU hotplug, kexec/kdump can also be supported easily
|
||||
in S-mode. HSM extension in OpenSBI is implemented in a non-backward compatible
|
||||
manner to reduce the maintenance burden and avoid confusion. That's why, any
|
||||
S-mode software using OpenSBI will not be able to boot more than 1 hart if HSM
|
||||
extension is not supported in S-mode.
|
||||
|
||||
Linux kernel already supports SBI v0.2 and HSM SBI extension starting from
|
||||
**v5.7-rc1**. If you are using an Linux kernel older than **5.7-rc1** or any
|
||||
other S-mode software without HSM SBI extension, you should stick to OpenSBI
|
||||
v0.6 to boot all the harts. For a UMP systems, it doesn't matter.
|
||||
|
||||
N.B. Any S-mode boot loader (i.e. U-Boot) doesn't need to support HSM extension,
|
||||
as it doesn't need to boot all the harts. The operating system should be
|
||||
capable enough to bring up all other non-booting harts using HSM extension.
|
||||
|
||||
Required Toolchain
|
||||
------------------
|
||||
|
||||
OpenSBI can be compiled natively or cross-compiled on a x86 host. For
|
||||
cross-compilation, you can build your own toolchain or just download
|
||||
a prebuilt one from the
|
||||
[Bootlin toolchain repository] (https://toolchains.bootlin.com/).
|
||||
a prebuilt one from the [Bootlin toolchain repository].
|
||||
|
||||
Please note that only a 64-bit version of the toolchain is available in
|
||||
the Bootlin toolchain repository for now.
|
||||
@@ -94,7 +146,7 @@ line, the platform-specific static library *libplatsbi.a* and firmware examples
|
||||
are built for the platform *<platform_subdir>* present in the directory
|
||||
*platform* in the OpenSBI top directory. For example, to compile the platform
|
||||
library and the firmware examples for the QEMU RISC-V *virt* machine,
|
||||
*<platform_subdir>* should be *qemu/virt*.
|
||||
*<platform_subdir>* should be *generic*.
|
||||
|
||||
To build *libsbi.a*, *libplatsbi.a* and the firmware for one of the supported
|
||||
platforms, run:
|
||||
@@ -150,35 +202,6 @@ export PLATFORM_RISCV_XLEN=32
|
||||
|
||||
will generate 32-bit OpenSBI images. And vice vesa.
|
||||
|
||||
License
|
||||
-------
|
||||
|
||||
OpenSBI is distributed under the terms of the BSD 2-clause license
|
||||
("Simplified BSD License" or "FreeBSD License", SPDX: *BSD-2-Clause*).
|
||||
A copy of this license with OpenSBI copyright can be found in the file
|
||||
[COPYING.BSD].
|
||||
|
||||
All source files in OpenSBI contain the 2-Clause BSD license SPDX short
|
||||
identifier in place of the full license text.
|
||||
|
||||
```
|
||||
SPDX-License-Identifier: BSD-2-Clause
|
||||
```
|
||||
|
||||
This enables machine processing of license information based on the SPDX
|
||||
License Identifiers that are available on the [SPDX] web site.
|
||||
|
||||
OpenSBI source code also contains code reused from other projects as listed
|
||||
below. The original license text of these projects is included in the source
|
||||
files where the reused code is present.
|
||||
|
||||
* The libfdt source code is disjunctively dual licensed
|
||||
(GPL-2.0+ OR BSD-2-Clause). Some of this project code is used in OpenSBI
|
||||
under the terms of the BSD 2-Clause license. Any contributions to this
|
||||
code must be made under the terms of both licenses.
|
||||
|
||||
See also the [third party notices] file for more information.
|
||||
|
||||
Contributing to OpenSBI
|
||||
-----------------------
|
||||
|
||||
@@ -197,10 +220,13 @@ Detailed documentation of various aspects of OpenSBI can be found under the
|
||||
|
||||
* [Contribution Guideline]: Guideline for contributing code to OpenSBI project
|
||||
* [Library Usage]: API documentation of OpenSBI static library *libsbi.a*
|
||||
* [Platform Requirements]: Requirements for using OpenSBI on a platform
|
||||
* [Platform Support Guide]: Guideline for implementing support for new platforms
|
||||
* [Platform Documentation]: Documentation of the platforms currently supported.
|
||||
* [Firmware Documentation]: Documentation for the different types of firmware
|
||||
examples build supported by OpenSBI.
|
||||
* [Domain Support]: Documentation for the OpenSBI domain support which helps
|
||||
users achieve system-level partitioning using OpenSBI.
|
||||
|
||||
OpenSBI source code is also well documented. For source level documentation,
|
||||
doxygen style is used. Please refer to the [Doxygen manual] for details on this
|
||||
@@ -244,14 +270,17 @@ make I=<install_directory> install_docs
|
||||
|
||||
[Github]: https://github.com/riscv/riscv-sbi-doc
|
||||
[U-Boot]: https://www.denx.de/wiki/U-Boot/SourceCode
|
||||
[Bootlin toolchain repository]: https://toolchains.bootlin.com/
|
||||
[COPYING.BSD]: COPYING.BSD
|
||||
[SPDX]: http://spdx.org/licenses/
|
||||
[Contribution Guideline]: docs/contributing.md
|
||||
[Contributors List]: CONTRIBUTORS.md
|
||||
[Library Usage]: docs/library_usage.md
|
||||
[Platform Requirements]: docs/platform_requirements.md
|
||||
[Platform Support Guide]: docs/platform_guide.md
|
||||
[Platform Documentation]: docs/platform/platform.md
|
||||
[Firmware Documentation]: docs/firmware/fw.md
|
||||
[Domain Support]: docs/domain_support.md
|
||||
[Doxygen manual]: http://www.doxygen.nl/manual/index.html
|
||||
[Kendryte standalone SDK]: https://github.com/kendryte/kendryte-standalone-sdk
|
||||
[third party notices]: ThirdPartyNotices.md
|
||||
|
314
docs/domain_support.md
Normal file
314
docs/domain_support.md
Normal file
@@ -0,0 +1,314 @@
|
||||
OpenSBI Domain Support
|
||||
======================
|
||||
|
||||
An OpenSBI domain is a system-level partition (subset) of underlying hardware
|
||||
having it's own memory regions (RAM and MMIO devices) and HARTs. The OpenSBI
|
||||
will try to achieve secure isolation between domains using RISC-V platform
|
||||
features such as PMP, ePMP, IOPMP, SiFive Shield, etc.
|
||||
|
||||
Important entities which help implement OpenSBI domain support are:
|
||||
|
||||
* **struct sbi_domain_memregion** - Representation of a domain memory region
|
||||
* **struct sbi_hartmask** - Representation of domain HART set
|
||||
* **struct sbi_domain** - Representation of a domain instance
|
||||
|
||||
Each HART of a RISC-V platform must have an OpenSBI domain assigned to it.
|
||||
The OpenSBI platform support is responsible for populating domains and
|
||||
providing HART id to domain mapping. The OpenSBI domain support will by
|
||||
default assign **the ROOT domain** to all HARTs of a RISC-V platform so
|
||||
it is not mandatory for the OpenSBI platform support to populate domains.
|
||||
|
||||
Domain Memory Region
|
||||
--------------------
|
||||
|
||||
A domain memory region is represented by **struct sbi_domain_memregion** in
|
||||
OpenSBI and has following details:
|
||||
|
||||
* **order** - The size of a memory region is **2 ^ order** where **order**
|
||||
must be **3 <= order <= __riscv_xlen**
|
||||
* **base** - The base address of a memory region is **2 ^ order**
|
||||
aligned start address
|
||||
* **flags** - The flags of a memory region represent memory type (i.e.
|
||||
RAM or MMIO) and allowed accesses (i.e. READ, WRITE, EXECUTE, etc)
|
||||
|
||||
Domain Instance
|
||||
---------------
|
||||
|
||||
A domain instance is represented by **struct sbi_domain** in OpenSBI and
|
||||
has following details:
|
||||
|
||||
* **index** - Logical index of this domain
|
||||
* **name** - Name of this domain
|
||||
* **assigned_harts** - HARTs assigned to this domain
|
||||
* **possible_harts** - HARTs possible in this domain
|
||||
* **regions** - Array of memory regions terminated by a memory region
|
||||
with order zero
|
||||
* **boot_hartid** - HART id of the HART booting this domain. The domain
|
||||
boot HART will be started at boot-time if boot HART is possible and
|
||||
assigned for this domain.
|
||||
* **next_addr** - Address of the next booting stage for this domain
|
||||
* **next_arg1** - Arg1 (or 'a1' register) of the next booting stage for
|
||||
this domain
|
||||
* **next_mode** - Privilege mode of the next booting stage for this
|
||||
domain. This can be either S-mode or U-mode.
|
||||
* **system_reset_allowed** - Is domain allowed to reset the system?
|
||||
|
||||
The memory regions represented by **regions** in **struct sbi_domain** have
|
||||
following additional constraints to align with RISC-V PMP requirements:
|
||||
|
||||
* A memory region to protect OpenSBI firmware from S-mode and U-mode
|
||||
should always be present
|
||||
* For two overlapping memory regions, one should be sub-region of another
|
||||
* Two overlapping memory regions should not be of same size
|
||||
* Two overlapping memory regions cannot have same flags
|
||||
* Memory access checks on overlapping address should prefer smallest
|
||||
overlapping memory region flags.
|
||||
|
||||
ROOT Domain
|
||||
-----------
|
||||
|
||||
**The ROOT domain** is the default OpenSBI domain which is assigned by
|
||||
default to all HARTs of a RISC-V platform. The OpenSBI domain support
|
||||
will hand-craft **the ROOT domain** very early at boot-time in the
|
||||
following manner:
|
||||
|
||||
* **index** - Logical index of the ROOT domain is always zero
|
||||
* **name** - Name of the ROOT domain is "root"
|
||||
* **assigned_harts** - At boot-time all valid HARTs of a RISC-V platform
|
||||
are assigned the ROOT domain which changes later based on OpenSBI
|
||||
platform support
|
||||
* **possible_harts** - All valid HARTs of a RISC-V platform are possible
|
||||
HARTs of the ROOT domain
|
||||
* **regions** - Two memory regions available to the ROOT domain:
|
||||
**A)** A memory region to protect OpenSBI firmware from S-mode and U-mode
|
||||
**B)** A memory region of **order=__riscv_xlen** allowing S-mode and
|
||||
U-mode access to full memory address space
|
||||
* **boot_hartid** - Coldboot HART is the HART booting the ROOT domain
|
||||
* **next_addr** - Next booting stage address in coldboot HART scratch
|
||||
space is the next address for the ROOT domain
|
||||
* **next_arg1** - Next booting stage arg1 in coldboot HART scratch space
|
||||
is the next arg1 for the ROOT domain
|
||||
* **next_mode** - Next booting stage mode in coldboot HART scratch space
|
||||
is the next mode for the ROOT domain
|
||||
* **system_reset_allowed** - The ROOT domain is allowed to reset the system
|
||||
|
||||
Domain Effects
|
||||
--------------
|
||||
|
||||
Few noteworthy effects of a system partitioned into domains are as follows:
|
||||
|
||||
* At any point in time, a HART is running in exactly one OpenSBI domain context
|
||||
* The SBI IPI and RFENCE calls from HART A are restricted to the HARTs in
|
||||
domain assigned to HART A
|
||||
* The SBI HSM calls which try to change/read state of HART B from HART A will
|
||||
only work if both HART A and HART B are assigned same domain
|
||||
* A HART running in S-mode or U-mode can only access memory based on the
|
||||
memory regions of the domain assigned to the HART
|
||||
|
||||
Domain Device Tree Bindings
|
||||
---------------------------
|
||||
|
||||
The OpenSBI domains can be described in the **device tree (DT) blob** (or
|
||||
flattened device tree) passed to the OpenSBI firmwares by the previous
|
||||
booting stage. This allows OpenSBI platform support to parse and populate
|
||||
OpenSBI domains from the device tree blob (or flattened device tree).
|
||||
|
||||
### Domain Configuration Node
|
||||
|
||||
All OpenSBI domain description related DT nodes should be under the domain
|
||||
configuration DT node. The **/chosen** DT node is the preferred parent of
|
||||
the domain configuration DT node.
|
||||
|
||||
The DT properties of a domain configuration DT node are as follows:
|
||||
|
||||
* **compatible** (Mandatory) - The compatible string of the domain
|
||||
configuration. This DT property should have value *"opensbi,domain,config"*
|
||||
|
||||
### Domain Memory Region Node
|
||||
|
||||
The domain memory region DT node describes details of a memory region and
|
||||
can be pointed by multiple domain instance DT nodes. The access permissions
|
||||
of the memory region are specified separately in domain instance node.
|
||||
|
||||
The DT properties of a domain memory region DT node are as follows:
|
||||
|
||||
* **compatible** (Mandatory) - The compatible string of the domain memory
|
||||
region. This DT property should have value *"opensbi,domain,memregion"*
|
||||
* **base** (Mandatory) - The base address of the domain memory region. This
|
||||
DT property should have a **2 ^ order** aligned 64 bit address (i.e. two
|
||||
DT cells).
|
||||
* **order** (Mandatory) - The order of the domain memory region. This DT
|
||||
property should have a 32 bit value (i.e. one DT cell) in the range
|
||||
**3 <= order <= __riscv_xlen**.
|
||||
* **mmio** (Optional) - A boolean flag representing whether the domain
|
||||
memory region is a memory-mapped I/O (MMIO) region.
|
||||
* **devices** (Optional) - The list of device DT node phandles for devices
|
||||
which fall under this domain memory region.
|
||||
|
||||
### Domain Instance Node
|
||||
|
||||
The domain instance DT node describes set of possible HARTs, set of memory
|
||||
regions, and other details of a domain instance.
|
||||
|
||||
The DT properties of a domain instance DT node are as follows:
|
||||
|
||||
* **compatible** (Mandatory) - The compatible string of the domain instance.
|
||||
This DT property should have value *"opensbi,domain,instance"*
|
||||
* **possible-harts** (Optional) - The list of CPU DT node phandles for the
|
||||
the domain instance. This list represents the possible HARTs of the
|
||||
domain instance.
|
||||
* **regions** (Optional) - The list of domain memory region DT node phandle
|
||||
and access permissions for the domain instance. Each list entry is a pair
|
||||
of DT node phandle and access permissions. The access permissions are
|
||||
represented as a 32bit bitmask having bits: **readable** (BIT[0]),
|
||||
**writeable** (BIT[1]), **executable** (BIT[2]), and **m-mode** (BIT[3]).
|
||||
* **boot-hart** (Optional) - The DT node phandle of the HART booting the
|
||||
domain instance. If coldboot HART is assigned to the domain instance then
|
||||
this DT property is ignored and the coldboot HART is assumed to be the
|
||||
boot HART of the domain instance.
|
||||
* **next-arg1** (Optional) - The 64 bit next booting stage arg1 for the
|
||||
domain instance. If this DT property is not available and coldboot HART
|
||||
is not assigned to the domain instance then **0x0** is used as default
|
||||
value. If this DT property is not available and coldboot HART is assigned
|
||||
to the domain instance then **next booting stage arg1 of coldboot HART**
|
||||
is used as default value.
|
||||
* **next-addr** (Optional) - The 64 bit next booting stage address for the
|
||||
domain instance. If this DT property is not available and coldboot HART
|
||||
is not assigned to the domain instance then **0x0** is used as default
|
||||
value. If this DT property is not available and coldboot HART is assigned
|
||||
to the domain instance then **next booting stage address of coldboot HART**
|
||||
is used as default value.
|
||||
* **next-mode** (Optional) - The 32 bit next booting stage mode for the
|
||||
domain instance. The possible values of this DT property are: **0x1**
|
||||
(s-mode), and **0x0** (u-mode). If this DT property is not available
|
||||
and coldboot HART is not assigned to the domain instance then **0x1**
|
||||
is used as default value. If this DT property is not available and
|
||||
coldboot HART is assigned to the domain instance then **next booting
|
||||
stage mode of coldboot HART** is used as default value.
|
||||
* **system-reset-allowed** (Optional) - A boolean flag representing
|
||||
whether the domain instance is allowed to do system reset.
|
||||
|
||||
### Assigning HART To Domain Instance
|
||||
|
||||
By default, all HARTs are assigned to **the ROOT domain**. The OpenSBI
|
||||
platform support can provide the HART to domain instance assignment using
|
||||
platform specific callback.
|
||||
|
||||
The HART to domain instance assignment can be parsed from the device tree
|
||||
using optional DT property **opensbi,domain** in each CPU DT node. The
|
||||
value of DT property **opensbi,domain** is the DT phandle of the domain
|
||||
instance DT node. If **opensbi,domain** DT property is not specified then
|
||||
corresponding HART is assigned to **the ROOT domain**.
|
||||
|
||||
### Domain Configuration Only Accessible to OpenSBI
|
||||
|
||||
The software running inside a domain instance should only be aware of
|
||||
devices and hardware resources accessible to itself.
|
||||
|
||||
To hide domain configuration from domain instances, the following should
|
||||
be done:
|
||||
|
||||
* The previous booting stage should preferably provide a separate device
|
||||
tree for each domain instance and mention location of device tree in
|
||||
respective domain instance DT nodes using **next-arg1** DT property.
|
||||
* If domain assigned to a HART does not have separate device tree then
|
||||
OpenSBI platform support should remove all domain configuration details
|
||||
from the device tree passed by previous booting stage before passing it
|
||||
to the next booting stage.
|
||||
|
||||
### Example
|
||||
|
||||
```
|
||||
chosen {
|
||||
opensbi-domains {
|
||||
compatible = "opensbi,domain,config";
|
||||
|
||||
tmem: tmem {
|
||||
compatible = "opensbi,domain,memregion";
|
||||
base = <0x0 0x80100000>;
|
||||
order = <20>;
|
||||
};
|
||||
|
||||
tuart: tuart {
|
||||
compatible = "opensbi,domain,memregion";
|
||||
base = <0x0 0x10011000>;
|
||||
order = <12>;
|
||||
mmio;
|
||||
devices = <&uart1>;
|
||||
};
|
||||
|
||||
allmem: allmem {
|
||||
compatible = "opensbi,domain,memregion";
|
||||
base = <0x0 0x0>;
|
||||
order = <64>;
|
||||
};
|
||||
|
||||
tdomain: trusted-domain {
|
||||
compatible = "opensbi,domain,instance";
|
||||
possible-harts = <&cpu0>;
|
||||
regions = <&tmem 0x7>, <&tuart 0x7>;
|
||||
boot-hart = <&cpu0>;
|
||||
next-arg1 = <0x0 0x0>;
|
||||
next-addr = <0x0 0x80100000>;
|
||||
next-mode = <0x0>;
|
||||
system-reset-allowed;
|
||||
};
|
||||
|
||||
udomain: untrusted-domain {
|
||||
compatible = "opensbi,domain,instance";
|
||||
possible-harts = <&cpu1 &cpu2 &cpu3 &cpu4>;
|
||||
regions = <&tmem 0x0>, <&tuart 0x0>, <&allmem 0x7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
timebase-frequency = <10000000>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x00>;
|
||||
compatible = "riscv";
|
||||
opensbi-domain = <&tdomain>;
|
||||
...
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
reg = <0x01>;
|
||||
compatible = "riscv";
|
||||
opensbi-domain = <&udomain>;
|
||||
...
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
reg = <0x02>;
|
||||
compatible = "riscv";
|
||||
opensbi-domain = <&udomain>;
|
||||
...
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
reg = <0x03>;
|
||||
compatible = "riscv";
|
||||
opensbi-domain = <&udomain>;
|
||||
...
|
||||
};
|
||||
|
||||
cpu4: cpu@4 {
|
||||
device_type = "cpu";
|
||||
reg = <0x04>;
|
||||
compatible = "riscv";
|
||||
opensbi-domain = <&udomain>;
|
||||
...
|
||||
};
|
||||
};
|
||||
|
||||
uart1: serial@10011000 {
|
||||
...
|
||||
};
|
||||
```
|
@@ -793,7 +793,9 @@ WARN_LOGFILE =
|
||||
INPUT = @@SRC_DIR@@/README.md \
|
||||
@@SRC_DIR@@/docs/contributing.md \
|
||||
@@SRC_DIR@@/docs/platform_guide.md \
|
||||
@@SRC_DIR@@/docs/platform_requirements.md \
|
||||
@@SRC_DIR@@/docs/library_usage.md \
|
||||
@@SRC_DIR@@/docs/domain_support.md \
|
||||
@@SRC_DIR@@/docs/firmware \
|
||||
@@SRC_DIR@@/docs/platform \
|
||||
@@SRC_DIR@@/include \
|
||||
@@ -948,7 +950,7 @@ FILTER_SOURCE_PATTERNS =
|
||||
# (index.html). This can be useful if you have a project on for instance GitHub
|
||||
# and want to reuse the introduction page also for the doxygen output.
|
||||
|
||||
USE_MDFILE_AS_MAINPAGE =
|
||||
USE_MDFILE_AS_MAINPAGE = README.md
|
||||
|
||||
#---------------------------------------------------------------------------
|
||||
# Configuration options related to source browsing
|
||||
@@ -1444,7 +1446,7 @@ DISABLE_INDEX = NO
|
||||
# The default value is: NO.
|
||||
# This tag requires that the tag GENERATE_HTML is set to YES.
|
||||
|
||||
GENERATE_TREEVIEW = NO
|
||||
GENERATE_TREEVIEW = YES
|
||||
|
||||
# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
|
||||
# doxygen will group on one line in the generated HTML documentation.
|
||||
|
@@ -51,11 +51,17 @@ case, a *FW_PAYLOAD* firmware allows embedding a flattened device tree in the
|
||||
Firmware Configuration and Compilation
|
||||
--------------------------------------
|
||||
|
||||
All firmware types mandate the definition of the following compile time
|
||||
configuration parameter.
|
||||
All firmware types support the following common compile time configuration
|
||||
parameters:
|
||||
|
||||
* **FW_TEXT_ADDR** - Defines the address at which the previous booting stage
|
||||
loads OpenSBI firmware.
|
||||
* **FW_TEXT_ADDR** - Defines the execution address of the OpenSBI firmware.
|
||||
This configuration parameter is mandatory.
|
||||
* **FW_FDT_PATH** - Path to an external flattened device tree binary file to
|
||||
be embedded in the *.rodata* section of the final firmware. If this option
|
||||
is not provided then the firmware will expect the FDT to be passed as an
|
||||
argument by the prior booting stage.
|
||||
* **FW_FDT_PADDING** - Optional zero bytes padding to the embedded flattened
|
||||
device tree binary file specified by **FW_FDT_PATH** option.
|
||||
|
||||
Additionally, each firmware type as a set of type specific configuration
|
||||
parameters. Detailed information for each firmware type can be found in the
|
||||
|
@@ -1,4 +1,4 @@
|
||||
OpenSBI Firmware with Dynamic Information *FW_DYNAMIC*
|
||||
OpenSBI Firmware with Dynamic Information (FW_DYNAMIC)
|
||||
======================================================
|
||||
|
||||
OpenSBI **firmware with dynamic info (FW_DYNAMIC)** is a firmware which gets
|
||||
|
@@ -1,4 +1,4 @@
|
||||
OpenSBI Firmware with Jump Address *FW_JUMP*
|
||||
OpenSBI Firmware with Jump Address (FW_JUMP)
|
||||
============================================
|
||||
|
||||
OpenSBI **firmware with Jump Address (FW_JUMP)** is a firmware which only
|
||||
|
@@ -1,4 +1,4 @@
|
||||
OpenSBI Firmware with Payload *FW_PAYLOAD*
|
||||
OpenSBI Firmware with Payload (FW_PAYLOAD)
|
||||
==========================================
|
||||
|
||||
OpenSBI **firmware with Payload (FW_PAYLOAD)** is a firmware which directly
|
||||
@@ -55,23 +55,9 @@ file. The parameters currently defined are as follows:
|
||||
automatically generated and used as a payload. This test payload executes
|
||||
an infinite `while (1)` loop after printing a message on the platform console.
|
||||
|
||||
* **FW_PAYLOAD_FDT_PATH** - Path to an external flattened device tree binary
|
||||
file to be embedded in the *.text* section of the final firmware. If this
|
||||
option is not provided and no internal device tree file is specified by the
|
||||
platform (c.f. *FW_PAYLOAD_FDT*), then the firmware will expect the FDT to
|
||||
be passed as an argument by the prior booting stage.
|
||||
|
||||
* **FW_PAYLOAD_FDT** - Path to an internal flattened device tree binary file
|
||||
defined by the platform code. The file name must match the DTB file name
|
||||
specified in the platform *objects.mk* file with the *platform-dtb-y* entry.
|
||||
This option results in *FW_PAYLOAD_FDT_PATH* to be automatically set.
|
||||
Specifying *FW_PAYLOAD_FDT_PATH* on the `make` command line disables
|
||||
*FW_PAYLOAD_FDT* and the command line specified device tree binary file is
|
||||
used for building the final firmware.
|
||||
|
||||
* **FW_PAYLOAD_FDT_ADDR** - Address where the FDT passed by the prior booting
|
||||
stage or specified by the *FW_PAYLOAD_FDT_PATH* parameter and embedded in
|
||||
the *.text* section will be placed before executing the next booting stage,
|
||||
stage or specified by the *FW_FDT_PATH* parameter and embedded in the
|
||||
*.rodata* section will be placed before executing the next booting stage,
|
||||
that is, the payload firmware. If this option is not provided, then the
|
||||
firmware will pass the FDT address passed by the previous booting stage
|
||||
to the next booting stage.
|
||||
@@ -83,7 +69,4 @@ The *[qemu/virt]* platforms illustrate how to configure and use a *FW_PAYLOAD*
|
||||
firmware. Detailed information regarding these platforms can be found in the
|
||||
platform documentation files.
|
||||
|
||||
The *kendryte/k210* platform also enables a build of a *FW_PAYLOAD* using an
|
||||
internally defined device tree file (*FW_PAYLOAD_FDT*).
|
||||
|
||||
[qemu/virt]: ../platform/qemu_virt.md
|
||||
|
@@ -7,34 +7,9 @@ environment. In the context of OpenSBI, U-Boot can be specified as a payload to
|
||||
the OpenSBI firmware, becoming the boot stage following the OpenSBI firmware
|
||||
execution.
|
||||
|
||||
The current stable upstream code of U-Boot does not yet include all patches
|
||||
necessary to fully support OpenSBI. To use U-Boot as an OpenSBI payload, the
|
||||
following out-of-tree patch series must be applied to the upstream U-Boot source
|
||||
code:
|
||||
|
||||
HiFive Unleashed support for U-Boot
|
||||
|
||||
https://lists.denx.de/pipermail/u-boot/2019-February/358058.html
|
||||
|
||||
This patch series enables a single CPU to execute U-Boot. As a result, the next
|
||||
stage boot code such as a Linux kernel can also only execute on a single CPU.
|
||||
U-Boot SMP support for RISC-V can be enabled with the following additional
|
||||
patches:
|
||||
|
||||
https://lists.denx.de/pipermail/u-boot/2019-February/358393.html
|
||||
|
||||
Building and Generating U-Boot images
|
||||
=====================================
|
||||
Please refer to the U-Boot build documentation for detailed instructions on
|
||||
how to build U-Boot images.
|
||||
how to build U-Boot image and boot high level operating systems from U-Boot
|
||||
prompt.
|
||||
|
||||
Once U-Boot images are built, the Linux kernel image needs to be converted
|
||||
into a format that U-Boot understands:
|
||||
|
||||
```
|
||||
<uboot-dir>/tools/mkimage -A riscv -O linux -T kernel -C none -a 0x80200000 -e 0x80200000 -n Linux -d \
|
||||
<linux_build_directory>arch/riscv/boot/Image \
|
||||
<linux_build_directory>/arch/riscv/boot/uImage
|
||||
```
|
||||
|
||||
Copy the uImage to your tftpboot server path if network boot is required.
|
||||
|
@@ -19,12 +19,12 @@ Building Andes AE350 Platform
|
||||
-----------------------------
|
||||
|
||||
To use Linux v5.2 should be used to build Andes AE350 OpenSBI binaries by using
|
||||
the compile time option FW_PAYLOAD_FDT_PATH.
|
||||
the compile time option FW_FDT_PATH.
|
||||
|
||||
AE350's dts is included in https://github.com/andestech/linux/tree/ast-v3_2_0-release-public
|
||||
|
||||
**Linux Kernel Payload**
|
||||
|
||||
```
|
||||
make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_PAYLOAD_FDT_PATH=<ae350.dtb path>
|
||||
make PLATFORM=andes/ae350 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<ae350.dtb path>
|
||||
```
|
||||
|
@@ -13,7 +13,7 @@ The FPGA SoC currently contains the following peripherals:
|
||||
- Bootrom containing zero stage bootloader and device tree.
|
||||
|
||||
To build platform specific library and firmwares, provide the
|
||||
*PLATFORM=ariane-fpga* parameter to the top level `make` command.
|
||||
*PLATFORM=fpga/ariane* parameter to the top level `make` command.
|
||||
|
||||
Platform Options
|
||||
----------------
|
||||
@@ -26,7 +26,7 @@ Building Ariane FPGA Platform
|
||||
**Linux Kernel Payload**
|
||||
|
||||
```
|
||||
make PLATFORM=ariane-fpga FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
make PLATFORM=fpga/ariane FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
```
|
||||
|
||||
Booting Ariane FPGA Platform
|
33
docs/platform/fpga-openpiton.md
Normal file
33
docs/platform/fpga-openpiton.md
Normal file
@@ -0,0 +1,33 @@
|
||||
OpenPiton FPGA SoC Platform
|
||||
========================
|
||||
OpenPiton is the world's first open source, general purpose, multithreaded
|
||||
manycore processor. It is a tiled manycore framework scalable from one to
|
||||
1/2 billion cores. Currently, OpenPiton supports the 64bit Ariane RISC-V
|
||||
processor from ETH Zurich. To this end, Ariane has been equipped with a
|
||||
different L1 cache subsystem that follows a write-through protocol and that has
|
||||
support for cache invalidations and atomics.
|
||||
|
||||
To build platform specific library and firmwares, provide the
|
||||
*PLATFORM=fpga/openpiton* parameter to the top level `make` command.
|
||||
|
||||
Platform Options
|
||||
----------------
|
||||
|
||||
The *OpenPiton* platform does not have any platform-specific options.
|
||||
|
||||
Building Ariane FPGA Platform
|
||||
-----------------------------
|
||||
|
||||
**Linux Kernel Payload**
|
||||
|
||||
```
|
||||
make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
```
|
||||
|
||||
Booting Ariane FPGA Platform
|
||||
----------------------------
|
||||
|
||||
**Linux Kernel Payload**
|
||||
|
||||
As Linux kernel image is embedded in the OpenSBI firmware binary, Ariane will
|
||||
directly boot into Linux directly after powered on.
|
54
docs/platform/generic.md
Normal file
54
docs/platform/generic.md
Normal file
@@ -0,0 +1,54 @@
|
||||
Generic Platform
|
||||
================
|
||||
|
||||
The **Generic** platform is a flattened device tree (FDT) based platform
|
||||
where all platform specific functionality is provided based on FDT passed
|
||||
by previous booting stage. The **Generic** platform allows us to use same
|
||||
OpenSBI firmware binaries on various emulators, simulators, FPGAs, and
|
||||
boards.
|
||||
|
||||
By default, the generic FDT platform makes following assumptions:
|
||||
|
||||
1. platform FW_TEXT_START is 0x80000000
|
||||
2. platform features are default
|
||||
3. platform stack size is default
|
||||
4. platform has no quirks or work-arounds
|
||||
|
||||
The above assumptions (except 1) can be overridden by adding special platform
|
||||
callbacks which will be called based on FDT root node compatible string.
|
||||
|
||||
Users of the generic FDT platform will have to ensure that:
|
||||
|
||||
1. Various FDT based drivers under lib/utils directory are upto date
|
||||
based on their platform requirements
|
||||
2. The FDT passed by previous booting stage has DT compatible strings and
|
||||
DT properties in sync with the FDT based drivers under lib/utils directory
|
||||
3. The FDT must have "stdout-path" DT property in the "/chosen" DT node when
|
||||
a platform has multiple serial ports or consoles
|
||||
4. On multi-HART platform, the FDT must have a DT node for IPI device and
|
||||
lib/utils/ipi directory must have corresponding FDT based IPI driver
|
||||
5. The FDT must have a DT node for timer device and lib/utils/timer directory
|
||||
must have corresponding FDT based timer driver
|
||||
|
||||
To build the platform-specific library and firmware images, provide the
|
||||
*PLATFORM=generic* parameter to the top level `make` command.
|
||||
|
||||
For custom FW_TEXT_START, we can build the platform-specific library and
|
||||
firmware images by passing *PLATFORM=generic FW_TEXT_START=<custom_text_start>*
|
||||
parameter to the top level `make` command.
|
||||
|
||||
Platform Options
|
||||
----------------
|
||||
|
||||
The *Generic* platform does not have any platform-specific options.
|
||||
|
||||
RISC-V Platforms Using Generic Platform
|
||||
---------------------------------------
|
||||
|
||||
* **QEMU RISC-V Virt Machine** (*[qemu_virt.md]*)
|
||||
* **Spike** (*[spike.md]*)
|
||||
* **Shakti C-class SoC Platform** (*[shakti_cclass.md]*)
|
||||
|
||||
[qemu_virt.md]: qemu_virt.md
|
||||
[spike.md]: spike.md
|
||||
[shakti_cclass.md]: shakti_cclass.md
|
22
docs/platform/nuclei_ux600.md
Normal file
22
docs/platform/nuclei_ux600.md
Normal file
@@ -0,0 +1,22 @@
|
||||
|
||||
Nuclei UX600 Platform
|
||||
=====================
|
||||
|
||||
The **Nuclei UX600** is a 64-bit RISC-V Core which is capable of running Linux.
|
||||
|
||||
> Nuclei UX600: single core, pipeline as single-issue and 6~9 variable stages, in-order dispatch and out-of-order write-back, running up to >1.2GHz
|
||||
|
||||
To build the platform-specific library and firmware images, provide the
|
||||
*PLATFORM=nuclei/ux600* parameter to the top level `make` command.
|
||||
|
||||
Platform Options
|
||||
----------------
|
||||
|
||||
The *Nuclei UX600* platform does not have any platform-specific options.
|
||||
|
||||
Building Nuclei UX600 Platform
|
||||
------------------------------
|
||||
|
||||
```
|
||||
make PLATFORM=nuclei/ux600 clean all
|
||||
```
|
@@ -3,6 +3,11 @@ OpenSBI Supported Platforms
|
||||
|
||||
OpenSBI currently supports the following virtual and hardware platforms:
|
||||
|
||||
* **Generic**: Flattened device tree (FDT) based platform where platform
|
||||
specific functionality is provided based on the FDT passed by previous
|
||||
booting stage. More details on this platform can be found in the file
|
||||
*[generic.md]*.
|
||||
|
||||
* **QEMU RISC-V Virt Machine**: Platform support for the QEMU *virt* virtual
|
||||
RISC-V machine. This virtual machine is intended for RISC-V software
|
||||
development and tests. More details on this platform can be found in the
|
||||
@@ -17,13 +22,25 @@ OpenSBI currently supports the following virtual and hardware platforms:
|
||||
boards such as the Kendryte KD233 or the Sipeed MAIX Dock.
|
||||
|
||||
* **Ariane FPGA SoC**: Platform support for the Ariane FPGA SoC used on
|
||||
Genesys 2 board.
|
||||
Genesys 2 board. More details on this platform can be found in the file
|
||||
*[fpga-ariane.md]*.
|
||||
|
||||
* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350).
|
||||
* **Andes AE350 SoC**: Platform support for the Andes's SoC (AE350). More
|
||||
details on this platform can be found in the file *[andes-ae350.md]*.
|
||||
|
||||
* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor.
|
||||
* **T-HEAD C910**: Platform support for the T-HEAD C910 Processor. More
|
||||
details on this platform can be found in the file *[thead-c910.md]*.
|
||||
|
||||
* **Spike**: Platform support for the Spike emulator.
|
||||
* **Spike**: Platform support for the Spike emulator. More
|
||||
details on this platform can be found in the file *[spike.md]*.
|
||||
|
||||
* **OpenPiton FPGA SoC**: Platform support OpenPiton research platform based
|
||||
on ariane core. More details on this platform can be found in the file
|
||||
*[fpga_openpiton.md]*.
|
||||
|
||||
* **Shakti C-class SoC Platform**: Platform support for Shakti C-class
|
||||
processor based SOCs. More details on this platform can be found in the
|
||||
file *[shakti_cclass.md]*.
|
||||
|
||||
The code for these supported platforms can be used as example to implement
|
||||
support for other platforms. The *platform/template* directory also provides
|
||||
@@ -31,9 +48,12 @@ template files for implementing support for a new platform. The *object.mk*,
|
||||
*config.mk* and *platform.c* template files provides enough comments to
|
||||
facilitate the implementation.
|
||||
|
||||
[generic.md]: generic.md
|
||||
[qemu_virt.md]: qemu_virt.md
|
||||
[sifive_fu540.md]: sifive_fu540.md
|
||||
[ariane-fpga.md]: ariane-fpga.md
|
||||
[andes_ae350.md]: andes-ae350.md
|
||||
[fpga-ariane.md]: fpga-ariane.md
|
||||
[andes-ae350.md]: andes-ae350.md
|
||||
[thead-c910.md]: thead-c910.md
|
||||
[spike.md]: spike.md
|
||||
[fpga_openpiton.md]: fpga_openpiton.md
|
||||
[shakti_cclass.md]: shakti_cclass.md
|
||||
|
@@ -7,7 +7,7 @@ software development and testing. It is also referred to as
|
||||
storage, and other types of IO.
|
||||
|
||||
To build the platform-specific library and firmware images, provide the
|
||||
*PLATFORM=qemu/virt* parameter to the top level `make` command.
|
||||
*PLATFORM=generic* parameter to the top level `make` command.
|
||||
|
||||
Platform Options
|
||||
----------------
|
||||
@@ -22,13 +22,13 @@ Execution on QEMU RISC-V 64-bit
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=qemu/virt
|
||||
make PLATFORM=generic
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv64 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_payload.elf
|
||||
-bios build/platform/generic/firmware/fw_payload.bin
|
||||
```
|
||||
|
||||
**U-Boot Payload**
|
||||
@@ -38,19 +38,19 @@ the `qemu-riscv64_smode_defconfig` configuration.
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
|
||||
make PLATFORM=generic FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv64 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_payload.elf
|
||||
-bios build/platform/generic/firmware/fw_payload.elf
|
||||
```
|
||||
or
|
||||
```
|
||||
qemu-system-riscv64 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
|
||||
-device loader,file=<uboot_build_directory>/u-boot.bin,addr=0x80200000
|
||||
-bios build/platform/generic/firmware/fw_jump.bin \
|
||||
-kernel <uboot_build_directory>/u-boot.bin
|
||||
```
|
||||
|
||||
**Linux Kernel Payload**
|
||||
@@ -60,13 +60,13 @@ Note: We assume that the Linux kernel is compiled using
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv64 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_payload.elf \
|
||||
-bios build/platform/generic/firmware/fw_payload.elf \
|
||||
-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
|
||||
-device virtio-blk-device,drive=hd0 \
|
||||
-append "root=/dev/vda rw console=ttyS0"
|
||||
@@ -74,8 +74,8 @@ qemu-system-riscv64 -M virt -m 256M -nographic \
|
||||
or
|
||||
```
|
||||
qemu-system-riscv64 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
|
||||
-device loader,file=<linux_build_directory>/arch/riscv/boot/Image,addr=0x80200000 \
|
||||
-bios build/platform/generic/firmware/fw_jump.bin \
|
||||
-kernel <linux_build_directory>/arch/riscv/boot/Image \
|
||||
-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
|
||||
-device virtio-blk-device,drive=hd0 \
|
||||
-append "root=/dev/vda rw console=ttyS0"
|
||||
@@ -89,13 +89,13 @@ Execution on QEMU RISC-V 32-bit
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=qemu/virt
|
||||
make PLATFORM=generic PLATFORM_RISCV_XLEN=32
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv32 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_payload.elf
|
||||
-bios build/platform/generic/firmware/fw_payload.bin
|
||||
```
|
||||
|
||||
**U-Boot Payload**
|
||||
@@ -105,37 +105,35 @@ the `qemu-riscv32_smode_defconfig` configuration.
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
|
||||
make PLATFORM=generic PLATFORM_RISCV_XLEN=32 FW_PAYLOAD_PATH=<uboot_build_directory>/u-boot.bin
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv32 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_payload.elf
|
||||
-bios build/platform/generic/firmware/fw_payload.elf
|
||||
```
|
||||
or
|
||||
```
|
||||
qemu-system-riscv32 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
|
||||
-device loader,file=<uboot_build_directory>/u-boot.bin,addr=0x80400000
|
||||
-bios build/platform/generic/firmware/fw_jump.bin \
|
||||
-kernel <uboot_build_directory>/u-boot.bin
|
||||
```
|
||||
|
||||
**Linux Kernel Payload**
|
||||
|
||||
Note: We assume that the Linux kernel is compiled using
|
||||
*arch/riscv/configs/rv32_defconfig* (kernel 5.1 and newer)
|
||||
respectively using *arch/riscv/configs/defconfig* plus setting
|
||||
CONFIG_ARCH_RV32I=y (kernel 5.0 and older).
|
||||
*arch/riscv/configs/rv32_defconfig*.
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=qemu/virt FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
make PLATFORM=generic PLATFORM_RISCV_XLEN=32 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv32 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_payload.elf \
|
||||
-bios build/platform/generic/firmware/fw_payload.elf \
|
||||
-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
|
||||
-device virtio-blk-device,drive=hd0 \
|
||||
-append "root=/dev/vda rw console=ttyS0"
|
||||
@@ -143,8 +141,8 @@ qemu-system-riscv32 -M virt -m 256M -nographic \
|
||||
or
|
||||
```
|
||||
qemu-system-riscv32 -M virt -m 256M -nographic \
|
||||
-kernel build/platform/qemu/virt/firmware/fw_jump.elf \
|
||||
-device loader,file=<linux_build_directory>/arch/riscv/boot/Image,addr=0x80400000 \
|
||||
-bios build/platform/generic/firmware/fw_jump.bin \
|
||||
-kernel <linux_build_directory>/arch/riscv/boot/Image \
|
||||
-drive file=<path_to_linux_rootfs>,format=raw,id=hd0 \
|
||||
-device virtio-blk-device,drive=hd0 \
|
||||
-append "root=/dev/vda rw console=ttyS0"
|
||||
|
33
docs/platform/shakti_cclass.md
Normal file
33
docs/platform/shakti_cclass.md
Normal file
@@ -0,0 +1,33 @@
|
||||
Shakti C-class SoC Platform
|
||||
===========================
|
||||
C-Class is a member of the SHAKTI family of processors from
|
||||
Indian Institute of Technology - Madras (IIT-M).
|
||||
|
||||
It is an extremely configurable and commercial-grade 5-stage
|
||||
in-order core supporting the standard RV64GCSUN ISA extensions.
|
||||
|
||||
For more details, refer:
|
||||
* https://gitlab.com/shaktiproject/cores/c-class/blob/master/README.md
|
||||
* https://c-class.readthedocs.io/en/latest
|
||||
* https://shakti.org.in
|
||||
|
||||
Platform Options
|
||||
----------------
|
||||
|
||||
The *Shakti C-class SoC* platform does not have any platform-specific
|
||||
options.
|
||||
|
||||
Building Shakti C-class Platform
|
||||
--------------------------------
|
||||
|
||||
**Linux Kernel Payload**
|
||||
|
||||
```
|
||||
make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<shakti.dtb path>
|
||||
```
|
||||
|
||||
**Test Payload**
|
||||
|
||||
```
|
||||
make PLATFORM=generic FW_FDT_PATH=<shakti.dtb path>
|
||||
```
|
@@ -13,16 +13,8 @@ To build platform specific library and firmwares, provide the
|
||||
Platform Options
|
||||
----------------
|
||||
|
||||
As hart0 in the FU540 doesn't have an MMU, only harts 1-4 boot by default.
|
||||
A hart mask i.e. *FU540_ENABLED_HART_MASK* compile time option is provided
|
||||
to select any other hart for booting. Please keep in mind that this is not
|
||||
a generic option and it can only be specified for FU540 platform in the
|
||||
following way:
|
||||
|
||||
```
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=Image FU540_ENABLED_HART_MASK=0x02
|
||||
```
|
||||
This will let the board boot only hart1 instead of default 1-4.
|
||||
The *SiFive FU540 SoC* platform does not have any platform-specific
|
||||
options.
|
||||
|
||||
Building SiFive Fu540 Platform
|
||||
------------------------------
|
||||
@@ -35,50 +27,28 @@ U-Boot v2020.01 (or higher) should be used.
|
||||
The HiFive Unleashed device tree(DT) is merged in Linux v5.2 release. This
|
||||
DT (device tree) is not backward compatible with the DT passed from FSBL.
|
||||
|
||||
To use Linux v5.2 (or higher, the pre-built DTB (DT binary) from Linux v5.2
|
||||
To use Linux v5.2 (or higher), the pre-built DTB (DT binary) from Linux v5.2
|
||||
(or higher) should be used to build SiFive FU540 OpenSBI binaries by using
|
||||
the compile time option *FW_PAYLOAD_FDT_PATH*.
|
||||
the compile time option *FW_FDT_PATH*.
|
||||
|
||||
```
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
or
|
||||
(For Linux v5.2 or higher)
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_PAYLOAD_FDT_PATH=<hifive-unleashed-a00.dtb path from Linux kernel>
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image FW_FDT_PATH=<hifive-unleashed-a00.dtb path from Linux kernel>
|
||||
```
|
||||
|
||||
**U-Boot Payload**
|
||||
|
||||
The command-line example here assumes that U-Boot was compiled using the
|
||||
sifive_fu540_defconfig configuration and with U-Boot v2020.01 (or higher).
|
||||
|
||||
The detailed U-Boot booting guide is avaialble at [U-Boot].
|
||||
sifive_fu540_defconfig configuration and with U-Boot v2020.01, and up to
|
||||
v2020.07-rc3.
|
||||
|
||||
```
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot-dtb.bin
|
||||
```
|
||||
|
||||
**U-Boot & Linux Kernel as a single payload**
|
||||
|
||||
A single monolithic image containing both U-Boot & Linux can also be used if
|
||||
network boot setup is not available.
|
||||
|
||||
1. Create a temporary image with u-boot-dtb.bin as the first payload. The
|
||||
command-line example here assumes that U-Boot was compiled using
|
||||
sifive_fu540_defconfig configuration.
|
||||
```
|
||||
dd if=~/workspace/u-boot-riscv/u-boot-dtb.bin of=/tmp/temp.bin bs=1M
|
||||
```
|
||||
2. Append the Linux Kernel image.
|
||||
```
|
||||
dd if=<linux_build_directory>/arch/riscv/boot/Image of=/tmp/temp.bin bs=1M seek=4
|
||||
```
|
||||
3. Compile OpenSBI with temp.bin (generated in step 2) as payload.
|
||||
```
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/tmp/temp.bin
|
||||
or
|
||||
(For U-Boot which follows Linux v5.2 (or higher) DT bindings)
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=/tmp/temp.bin
|
||||
```
|
||||
For U-Boot v2020.07-rc4 or later releases, SPL support was added in U-Boot.
|
||||
Please refer to the detailed U-Boot booting guide available at [U-Boot].
|
||||
|
||||
Flashing the OpenSBI firmware binary to storage media:
|
||||
------------------------------------------------------
|
||||
@@ -177,7 +147,7 @@ booti ${kernel_addr_r} - ${fdt_addr_r}
|
||||
QEMU Specific Instructions
|
||||
--------------------------
|
||||
If you want to test OpenSBI with QEMU 'sifive_u' machine, please follow the
|
||||
same instructions above, with the exception of not passing FW_PAYLOAD_FDT_PATH.
|
||||
same instructions above, with the exception of not passing FW_FDT_PATH.
|
||||
|
||||
This is because QEMU generates a device tree blob on the fly based on the
|
||||
command line parameters and it's compatible with the one used in the upstream
|
||||
@@ -186,13 +156,37 @@ Linux kernel.
|
||||
When U-Boot v2020.01 (or higher) is used as the payload, as the SiFive FU540
|
||||
DTB for the real hardware is embedded in U-Boot binary itself, due to the same
|
||||
reason above, we need to switch the U-Boot sifive_fu540_defconfig configuration
|
||||
from CONFIG_OF_SEPARATE to CONFIG_OF_PRIOR_STAGE so that U-Boot uses the DTB
|
||||
generated by QEMU, and u-boot.bin should be used as the payload image, like:
|
||||
from **CONFIG_OF_SEPARATE** to **CONFIG_OF_PRIOR_STAGE** so that U-Boot uses the
|
||||
DTB generated by QEMU, and u-boot.bin should be used as the payload image, like:
|
||||
|
||||
```
|
||||
make PLATFORM=sifive/fu540 FW_PAYLOAD_PATH=<u-boot_build_dir>/u-boot.bin
|
||||
```
|
||||
|
||||
U-Boot v2020.07 release added SPL support to SiFive HiFive Unleashed board,
|
||||
hence a build error will be seen after you switch to **CONFIG_OF_PRIOR_STAGE**.
|
||||
|
||||
```
|
||||
./tools/mkimage: Can't open arch/riscv/dts/hifive-unleashed-a00.dtb: No such file or directory
|
||||
./tools/mkimage: failed to build FIT
|
||||
Makefile:1402: recipe for target 'u-boot.img' failed
|
||||
make: *** [u-boot.img] Error 1
|
||||
```
|
||||
|
||||
The above errors can be safely ignored as we don't run U-Boot SPL under QEMU.
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv64 -M sifive_u -m 256M -nographic \
|
||||
-bios build/platform/sifive/fu540/firmware/fw_payload.bin
|
||||
```
|
||||
or
|
||||
```
|
||||
qemu-system-riscv64 -M sifive_u -m 256M -nographic \
|
||||
-bios build/platform/sifive/fu540/firmware/fw_jump.bin \
|
||||
-kernel <uboot_build_dir>/u-boot.bin
|
||||
```
|
||||
|
||||
While the real hardware operates at the 64-bit mode, it's possible for QEMU to
|
||||
test the 32-bit OpenSBI firmware. This can be helpful for testing 32-bit SiFive
|
||||
specific drivers.
|
||||
|
@@ -9,7 +9,7 @@ on **Spike** simulator and QEMU Spike machine.
|
||||
For more details, refer [Spike on GitHub](https://github.com/riscv/riscv-isa-sim)
|
||||
|
||||
To build the platform-specific library and firmware images, provide the
|
||||
*PLATFORM=spike* parameter to the top level `make` command.
|
||||
*PLATFORM=generic* parameter to the top level `make` command.
|
||||
|
||||
Platform Options
|
||||
----------------
|
||||
@@ -23,12 +23,12 @@ Execution on Spike Simulator
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=spike
|
||||
make PLATFORM=generic
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
spike build/platform/spike/firmware/fw_payload.elf
|
||||
spike build/platform/generic/firmware/fw_payload.elf
|
||||
```
|
||||
|
||||
**Linux Kernel Payload**
|
||||
@@ -38,12 +38,12 @@ Note: We assume that the Linux kernel is compiled using
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=spike FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
spike --initrd <path_to_cpio_ramdisk> build/platform/spike/firmware/fw_payload.elf
|
||||
spike --initrd <path_to_cpio_ramdisk> build/platform/generic/firmware/fw_payload.elf
|
||||
```
|
||||
|
||||
Execution on QEMU RISC-V 64-bit
|
||||
@@ -53,13 +53,13 @@ Execution on QEMU RISC-V 64-bit
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=spike
|
||||
make PLATFORM=generic
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv64 -M spike -m 256M -nographic \
|
||||
-kernel build/platform/spike/firmware/fw_payload.elf
|
||||
-bios build/platform/generic/firmware/fw_payload.elf
|
||||
```
|
||||
|
||||
**Linux Kernel Payload**
|
||||
@@ -69,20 +69,20 @@ Note: We assume that the Linux kernel is compiled using
|
||||
|
||||
Build:
|
||||
```
|
||||
make PLATFORM=spike FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
make PLATFORM=generic FW_PAYLOAD_PATH=<linux_build_directory>/arch/riscv/boot/Image
|
||||
```
|
||||
|
||||
Run:
|
||||
```
|
||||
qemu-system-riscv64 -M spike -m 256M -nographic \
|
||||
-kernel build/platform/spike/firmware/fw_payload.elf \
|
||||
-bios build/platform/generic/firmware/fw_payload.elf \
|
||||
-initrd <path_to_cpio_ramdisk> \
|
||||
-append "root=/dev/ram rw console=hvc0 earlycon=sbi"
|
||||
```
|
||||
or
|
||||
```
|
||||
qemu-system-riscv64 -M spike -m 256M -nographic \
|
||||
-bios build/platform/spike/firmware/fw_jump.elf \
|
||||
-bios build/platform/generic/firmware/fw_jump.elf \
|
||||
-kernel <linux_build_directory>/arch/riscv/boot/Image \
|
||||
-initrd <path_to_cpio_ramdisk> \
|
||||
-append "root=/dev/ram rw console=hvc0 earlycon=sbi"
|
||||
|
44
docs/platform_requirements.md
Normal file
44
docs/platform_requirements.md
Normal file
@@ -0,0 +1,44 @@
|
||||
OpenSBI Platform Requirements
|
||||
=============================
|
||||
|
||||
The RISC-V platform requirements for OpenSBI can change over time
|
||||
with advances in RISC-V specifications and ecosystem.
|
||||
|
||||
To handle this, we have two types of RISC-V platform requirements:
|
||||
|
||||
1. **Base platform requirements** which apply to all OpenSBI releases
|
||||
2. **Release specific platform requirements** which apply to a OpenSBI
|
||||
release and later releases
|
||||
|
||||
Currently, we don't have any **Release specific platform requirements**
|
||||
but such platform requirements will be added in future.
|
||||
|
||||
Base Platform Requirements
|
||||
--------------------------
|
||||
|
||||
The base RISC-V platform requirements for OpenSBI are as follows:
|
||||
|
||||
1. At least rv32ima or rv64ima required on all HARTs
|
||||
2. At least one HART should have S-mode support because:
|
||||
|
||||
* SBI calls are meant for RISC-V S-mode (Supervisor mode)
|
||||
* OpenSBI implements SBI calls for S-mode software
|
||||
|
||||
3. The MTVEC CSR on all HARTs must support direct mode
|
||||
4. The PMP CSRs are optional. If PMP CSRs are not implemented then
|
||||
OpenSBI cannot protect M-mode firmware and secured memory regions
|
||||
5. The TIME CSR is optional. If TIME CSR is not implemented in
|
||||
hardware then a 64-bit MMIO counter is required to track time
|
||||
and emulate TIME CSR
|
||||
6. Hardware support for injecting M-mode software interrupts on
|
||||
a multi-HART platform
|
||||
|
||||
The RISC-V extensions not covered by rv32ima or rv64ima are optional
|
||||
for OpenSBI. Although, OpenSBI will detect and handle some of these
|
||||
optional RISC-V extensions at runtime.
|
||||
|
||||
The optional RISC-V extensions handled by OpenSBI at runtime are:
|
||||
|
||||
* D-extension: Double precision floating point
|
||||
* F-extension: Single precision floating point
|
||||
* H-extension: Hypervisor
|
@@ -7,5 +7,8 @@
|
||||
# Anup Patel <anup.patel@wdc.com>
|
||||
#
|
||||
|
||||
$(platform_build_dir)/firmware/fw_dynamic.o: $(FW_FDT_PATH)
|
||||
$(platform_build_dir)/firmware/fw_jump.o: $(FW_FDT_PATH)
|
||||
$(platform_build_dir)/firmware/fw_payload.o: $(FW_FDT_PATH)
|
||||
|
||||
$(platform_build_dir)/firmware/fw_payload.o: $(FW_PAYLOAD_PATH_FINAL)
|
||||
$(platform_build_dir)/firmware/fw_payload.o: $(FW_PAYLOAD_FDT_PATH)
|
||||
|
@@ -160,11 +160,44 @@ _relocate_done:
|
||||
li ra, 0
|
||||
call _reset_regs
|
||||
|
||||
/* Zero-out BSS */
|
||||
la s4, _bss_start
|
||||
la s5, _bss_end
|
||||
_bss_zero:
|
||||
REG_S zero, (s4)
|
||||
add s4, s4, __SIZEOF_POINTER__
|
||||
blt s4, s5, _bss_zero
|
||||
|
||||
/* Setup temporary trap handler */
|
||||
la s4, _start_hang
|
||||
csrw CSR_MTVEC, s4
|
||||
|
||||
/* Setup temporary stack */
|
||||
la s4, _fw_end
|
||||
li s5, (SBI_SCRATCH_SIZE * 2)
|
||||
add sp, s4, s5
|
||||
|
||||
/* Allow main firmware to save info */
|
||||
MOV_5R s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
|
||||
call fw_save_info
|
||||
MOV_5R a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
|
||||
|
||||
#ifdef FW_FDT_PATH
|
||||
/* Override previous arg1 */
|
||||
la a1, fw_fdt_bin
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize platform
|
||||
* Note: The a0 to a4 registers passed to the
|
||||
* firmware are parameters to this function.
|
||||
*/
|
||||
MOV_5R s0, a0, s1, a1, s2, a2, s3, a3, s4, a4
|
||||
call fw_platform_init
|
||||
add t0, a0, zero
|
||||
MOV_5R a0, s0, a1, s1, a2, s2, a3, s3, a4, s4
|
||||
add a1, t0, zero
|
||||
|
||||
/* Preload HART details
|
||||
* s7 -> HART Count
|
||||
* s8 -> HART Stack Size
|
||||
@@ -228,40 +261,24 @@ _scratch_init:
|
||||
/* Store hartid-to-scratch function address in scratch space */
|
||||
la a4, _hartid_to_scratch
|
||||
REG_S a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
|
||||
/* Store trap-exit function address in scratch space */
|
||||
la a4, _trap_exit
|
||||
REG_S a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(tp)
|
||||
/* Clear tmp0 in scratch space */
|
||||
REG_S zero, SBI_SCRATCH_TMP0_OFFSET(tp)
|
||||
/* Store firmware options in scratch space */
|
||||
MOV_3R s0, a0, s1, a1, s2, a2
|
||||
#ifdef FW_OPTIONS
|
||||
li a4, FW_OPTIONS
|
||||
li a0, FW_OPTIONS
|
||||
#else
|
||||
add a4, zero, zero
|
||||
#endif
|
||||
call fw_options
|
||||
or a4, a4, a0
|
||||
REG_S a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
|
||||
#endif
|
||||
REG_S a0, SBI_SCRATCH_OPTIONS_OFFSET(tp)
|
||||
MOV_3R a0, s0, a1, s1, a2, s2
|
||||
/* Move to next scratch space */
|
||||
add t1, t1, t2
|
||||
blt t1, s7, _scratch_init
|
||||
|
||||
/* Zero-out BSS */
|
||||
la a4, _bss_start
|
||||
la a5, _bss_end
|
||||
_bss_zero:
|
||||
REG_S zero, (a4)
|
||||
add a4, a4, __SIZEOF_POINTER__
|
||||
blt a4, a5, _bss_zero
|
||||
|
||||
/* Override pervious arg1 */
|
||||
MOV_3R s0, a0, s1, a1, s2, a2
|
||||
call fw_prev_arg1
|
||||
add t1, a0, zero
|
||||
MOV_3R a0, s0, a1, s1, a2, s2
|
||||
beqz t1, _prev_arg1_override_done
|
||||
add a1, t1, zero
|
||||
_prev_arg1_override_done:
|
||||
|
||||
/*
|
||||
* Relocate Flatened Device Tree (FDT)
|
||||
* source FDT address = previous arg1
|
||||
@@ -331,7 +348,7 @@ _fdt_reloc_done:
|
||||
fence rw, rw
|
||||
j _start_warm
|
||||
|
||||
/* waitting for boot hart done (_boot_status == 2) */
|
||||
/* waiting for boot hart to be done (_boot_status == 2) */
|
||||
_wait_for_boot_hart:
|
||||
li t0, BOOT_STATUS_BOOT_HART_DONE
|
||||
la t1, _boot_status
|
||||
@@ -351,6 +368,7 @@ _start_warm:
|
||||
csrw CSR_MIE, zero
|
||||
csrw CSR_MIP, zero
|
||||
|
||||
/* Find HART count and HART stack size */
|
||||
la a4, platform
|
||||
#if __riscv_xlen == 64
|
||||
lwu s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
|
||||
@@ -359,12 +377,29 @@ _start_warm:
|
||||
lw s7, SBI_PLATFORM_HART_COUNT_OFFSET(a4)
|
||||
lw s8, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(a4)
|
||||
#endif
|
||||
REG_L s9, SBI_PLATFORM_HART_INDEX2ID_OFFSET(a4)
|
||||
|
||||
/* HART ID should be within expected limit */
|
||||
/* Find HART id */
|
||||
csrr s6, CSR_MHARTID
|
||||
bge s6, s7, _start_hang
|
||||
|
||||
/* find the scratch space for this hart */
|
||||
/* Find HART index */
|
||||
beqz s9, 3f
|
||||
li a4, 0
|
||||
1:
|
||||
#if __riscv_xlen == 64
|
||||
lwu a5, (s9)
|
||||
#else
|
||||
lw a5, (s9)
|
||||
#endif
|
||||
beq a5, s6, 2f
|
||||
add s9, s9, 4
|
||||
add a4, a4, 1
|
||||
blt a4, s7, 1b
|
||||
li a4, -1
|
||||
2: add s6, a4, zero
|
||||
3: bge s6, s7, _start_hang
|
||||
|
||||
/* Find the scratch space based on HART index */
|
||||
la tp, _fw_end
|
||||
mul a5, s7, s8
|
||||
add tp, tp, a5
|
||||
@@ -381,10 +416,27 @@ _start_warm:
|
||||
|
||||
/* Setup trap handler */
|
||||
la a4, _trap_handler
|
||||
#if __riscv_xlen == 32
|
||||
csrr a5, CSR_MISA
|
||||
srli a5, a5, ('H' - 'A')
|
||||
andi a5, a5, 0x1
|
||||
beq a5, zero, _skip_trap_handler_rv32_hyp
|
||||
la a4, _trap_handler_rv32_hyp
|
||||
_skip_trap_handler_rv32_hyp:
|
||||
#endif
|
||||
csrw CSR_MTVEC, a4
|
||||
/* Make sure that mtvec is updated */
|
||||
1: csrr a5, CSR_MTVEC
|
||||
bne a4, a5, 1b
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
/* Override trap exit for H-extension */
|
||||
csrr a5, CSR_MISA
|
||||
srli a5, a5, ('H' - 'A')
|
||||
andi a5, a5, 0x1
|
||||
beq a5, zero, _skip_trap_exit_rv32_hyp
|
||||
la a4, _trap_exit_rv32_hyp
|
||||
csrr a5, CSR_MSCRATCH
|
||||
REG_S a4, SBI_SCRATCH_TRAP_EXIT_OFFSET(a5)
|
||||
_skip_trap_exit_rv32_hyp:
|
||||
#endif
|
||||
|
||||
/* Initialize SBI runtime */
|
||||
csrr a0, CSR_MSCRATCH
|
||||
@@ -409,35 +461,27 @@ _link_end:
|
||||
.align 3
|
||||
.globl _hartid_to_scratch
|
||||
_hartid_to_scratch:
|
||||
add sp, sp, -(3 * __SIZEOF_POINTER__)
|
||||
REG_S s0, (sp)
|
||||
REG_S s1, (__SIZEOF_POINTER__)(sp)
|
||||
REG_S s2, (__SIZEOF_POINTER__ * 2)(sp)
|
||||
/*
|
||||
* a0 -> HART ID (passed by caller)
|
||||
* s0 -> HART Stack Size
|
||||
* s1 -> HART Stack End
|
||||
* s2 -> Temporary
|
||||
* a1 -> HART Index (passed by caller)
|
||||
* t0 -> HART Stack Size
|
||||
* t1 -> HART Stack End
|
||||
* t2 -> Temporary
|
||||
*/
|
||||
la s2, platform
|
||||
la t2, platform
|
||||
#if __riscv_xlen == 64
|
||||
lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
|
||||
lwu s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
|
||||
lwu t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
|
||||
lwu t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
|
||||
#else
|
||||
lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2)
|
||||
lw s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2)
|
||||
lw t0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(t2)
|
||||
lw t2, SBI_PLATFORM_HART_COUNT_OFFSET(t2)
|
||||
#endif
|
||||
mul s2, s2, s0
|
||||
la s1, _fw_end
|
||||
add s1, s1, s2
|
||||
mul s2, s0, a0
|
||||
sub s1, s1, s2
|
||||
li s2, SBI_SCRATCH_SIZE
|
||||
sub a0, s1, s2
|
||||
REG_L s0, (sp)
|
||||
REG_L s1, (__SIZEOF_POINTER__)(sp)
|
||||
REG_L s2, (__SIZEOF_POINTER__ * 2)(sp)
|
||||
add sp, sp, (3 * __SIZEOF_POINTER__)
|
||||
sub t2, t2, a1
|
||||
mul t2, t2, t0
|
||||
la t1, _fw_end
|
||||
add t1, t1, t2
|
||||
li t2, SBI_SCRATCH_SIZE
|
||||
sub a0, t1, t2
|
||||
ret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
@@ -449,43 +493,43 @@ _start_hang:
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.globl _trap_handler
|
||||
_trap_handler:
|
||||
.globl fw_platform_init
|
||||
.weak fw_platform_init
|
||||
fw_platform_init:
|
||||
add a0, a1, zero
|
||||
ret
|
||||
|
||||
.macro TRAP_SAVE_AND_SETUP_SP_T0
|
||||
/* Swap TP and MSCRATCH */
|
||||
csrrw tp, CSR_MSCRATCH, tp
|
||||
|
||||
/* Save T0 in scratch space */
|
||||
REG_S t0, SBI_SCRATCH_TMP0_OFFSET(tp)
|
||||
|
||||
/* Check which mode we came from */
|
||||
/*
|
||||
* Set T0 to appropriate exception stack
|
||||
*
|
||||
* Came_From_M_Mode = ((MSTATUS.MPP < PRV_M) ? 1 : 0) - 1;
|
||||
* Exception_Stack = TP ^ (Came_From_M_Mode & (SP ^ TP))
|
||||
*
|
||||
* Came_From_M_Mode = 0 ==> Exception_Stack = TP
|
||||
* Came_From_M_Mode = -1 ==> Exception_Stack = SP
|
||||
*/
|
||||
csrr t0, CSR_MSTATUS
|
||||
srl t0, t0, MSTATUS_MPP_SHIFT
|
||||
and t0, t0, PRV_M
|
||||
xori t0, t0, PRV_M
|
||||
beq t0, zero, _trap_handler_m_mode
|
||||
slti t0, t0, PRV_M
|
||||
add t0, t0, -1
|
||||
xor sp, sp, tp
|
||||
and t0, t0, sp
|
||||
xor sp, sp, tp
|
||||
xor t0, tp, t0
|
||||
|
||||
/* We came from S-mode or U-mode */
|
||||
_trap_handler_s_mode:
|
||||
/* Set T0 to original SP */
|
||||
add t0, sp, zero
|
||||
/* Save original SP on exception stack */
|
||||
REG_S sp, (SBI_TRAP_REGS_OFFSET(sp) - SBI_TRAP_REGS_SIZE)(t0)
|
||||
|
||||
/* Setup exception stack */
|
||||
add sp, tp, -(SBI_TRAP_REGS_SIZE)
|
||||
|
||||
/* Jump to code common for all modes */
|
||||
j _trap_handler_all_mode
|
||||
|
||||
/* We came from M-mode */
|
||||
_trap_handler_m_mode:
|
||||
/* Set T0 to original SP */
|
||||
add t0, sp, zero
|
||||
|
||||
/* Re-use current SP as exception stack */
|
||||
add sp, sp, -(SBI_TRAP_REGS_SIZE)
|
||||
|
||||
_trap_handler_all_mode:
|
||||
/* Save original SP (from T0) on stack */
|
||||
REG_S t0, SBI_TRAP_REGS_OFFSET(sp)(sp)
|
||||
/* Set SP to exception stack and make room for trap registers */
|
||||
add sp, t0, -(SBI_TRAP_REGS_SIZE)
|
||||
|
||||
/* Restore T0 from scratch space */
|
||||
REG_L t0, SBI_SCRATCH_TMP0_OFFSET(tp)
|
||||
@@ -495,23 +539,23 @@ _trap_handler_all_mode:
|
||||
|
||||
/* Swap TP and MSCRATCH */
|
||||
csrrw tp, CSR_MSCRATCH, tp
|
||||
.endm
|
||||
|
||||
.macro TRAP_SAVE_MEPC_MSTATUS have_mstatush
|
||||
/* Save MEPC and MSTATUS CSRs */
|
||||
csrr t0, CSR_MEPC
|
||||
REG_S t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
|
||||
csrr t0, CSR_MSTATUS
|
||||
REG_S t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
|
||||
REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
|
||||
#if __riscv_xlen == 32
|
||||
csrr t0, CSR_MISA
|
||||
srli t0, t0, ('H' - 'A')
|
||||
andi t0, t0, 0x1
|
||||
beq t0, zero, _skip_mstatush_save
|
||||
.if \have_mstatush
|
||||
csrr t0, CSR_MSTATUSH
|
||||
REG_S t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
|
||||
_skip_mstatush_save:
|
||||
#endif
|
||||
.else
|
||||
REG_S zero, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
|
||||
.endif
|
||||
.endm
|
||||
|
||||
.macro TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
/* Save all general regisers except SP and T0 */
|
||||
REG_S zero, SBI_TRAP_REGS_OFFSET(zero)(sp)
|
||||
REG_S ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
|
||||
@@ -543,12 +587,15 @@ _skip_mstatush_save:
|
||||
REG_S t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
|
||||
REG_S t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
|
||||
REG_S t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
|
||||
.endm
|
||||
|
||||
.macro TRAP_CALL_C_ROUTINE
|
||||
/* Call C routine */
|
||||
add a0, sp, zero
|
||||
csrr a1, CSR_MSCRATCH
|
||||
call sbi_trap_handler
|
||||
.endm
|
||||
|
||||
.macro TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
/* Restore all general regisers except SP and T0 */
|
||||
REG_L ra, SBI_TRAP_REGS_OFFSET(ra)(sp)
|
||||
REG_L gp, SBI_TRAP_REGS_OFFSET(gp)(sp)
|
||||
@@ -579,30 +626,98 @@ _skip_mstatush_save:
|
||||
REG_L t4, SBI_TRAP_REGS_OFFSET(t4)(sp)
|
||||
REG_L t5, SBI_TRAP_REGS_OFFSET(t5)(sp)
|
||||
REG_L t6, SBI_TRAP_REGS_OFFSET(t6)(sp)
|
||||
.endm
|
||||
|
||||
.macro TRAP_RESTORE_MEPC_MSTATUS have_mstatush
|
||||
/* Restore MEPC and MSTATUS CSRs */
|
||||
REG_L t0, SBI_TRAP_REGS_OFFSET(mepc)(sp)
|
||||
csrw CSR_MEPC, t0
|
||||
REG_L t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp)
|
||||
csrw CSR_MSTATUS, t0
|
||||
#if __riscv_xlen == 32
|
||||
csrr t0, CSR_MISA
|
||||
srli t0, t0, ('H' - 'A')
|
||||
andi t0, t0, 0x1
|
||||
beq t0, zero, _skip_mstatush_restore
|
||||
.if \have_mstatush
|
||||
REG_L t0, SBI_TRAP_REGS_OFFSET(mstatusH)(sp)
|
||||
csrw CSR_MSTATUSH, t0
|
||||
_skip_mstatush_restore:
|
||||
#endif
|
||||
.endif
|
||||
.endm
|
||||
|
||||
.macro TRAP_RESTORE_SP_T0
|
||||
/* Restore T0 */
|
||||
REG_L t0, SBI_TRAP_REGS_OFFSET(t0)(sp)
|
||||
|
||||
/* Restore SP */
|
||||
REG_L sp, SBI_TRAP_REGS_OFFSET(sp)(sp)
|
||||
.endm
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.globl _trap_handler
|
||||
_trap_handler:
|
||||
TRAP_SAVE_AND_SETUP_SP_T0
|
||||
|
||||
TRAP_SAVE_MEPC_MSTATUS 0
|
||||
|
||||
TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
|
||||
TRAP_CALL_C_ROUTINE
|
||||
|
||||
TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
|
||||
TRAP_RESTORE_MEPC_MSTATUS 0
|
||||
|
||||
TRAP_RESTORE_SP_T0
|
||||
|
||||
mret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.globl _trap_exit
|
||||
_trap_exit:
|
||||
add sp, a0, zero
|
||||
|
||||
TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
|
||||
TRAP_RESTORE_MEPC_MSTATUS 0
|
||||
|
||||
TRAP_RESTORE_SP_T0
|
||||
|
||||
mret
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.globl _trap_handler_rv32_hyp
|
||||
_trap_handler_rv32_hyp:
|
||||
TRAP_SAVE_AND_SETUP_SP_T0
|
||||
|
||||
TRAP_SAVE_MEPC_MSTATUS 1
|
||||
|
||||
TRAP_SAVE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
|
||||
TRAP_CALL_C_ROUTINE
|
||||
|
||||
TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
|
||||
TRAP_RESTORE_MEPC_MSTATUS 1
|
||||
|
||||
TRAP_RESTORE_SP_T0
|
||||
|
||||
mret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.globl _trap_exit_rv32_hyp
|
||||
_trap_exit_rv32_hyp:
|
||||
add sp, a0, zero
|
||||
|
||||
TRAP_RESTORE_GENERAL_REGS_EXCEPT_SP_T0
|
||||
|
||||
TRAP_RESTORE_MEPC_MSTATUS 1
|
||||
|
||||
TRAP_RESTORE_SP_T0
|
||||
|
||||
mret
|
||||
#endif
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.globl _reset_regs
|
||||
@@ -641,3 +756,14 @@ _reset_regs:
|
||||
csrw CSR_MSCRATCH, 0
|
||||
|
||||
ret
|
||||
|
||||
#ifdef FW_FDT_PATH
|
||||
.section .rodata
|
||||
.align 4
|
||||
.globl fw_fdt_bin
|
||||
fw_fdt_bin:
|
||||
.incbin FW_FDT_PATH
|
||||
#ifdef FW_FDT_PADDING
|
||||
.fill FW_FDT_PADDING, 1, 0
|
||||
#endif
|
||||
#endif
|
||||
|
@@ -86,19 +86,6 @@ fw_save_info:
|
||||
2:
|
||||
ret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.global fw_prev_arg1
|
||||
/*
|
||||
* We can only use a0, a1, and a2 registers here.
|
||||
* The a0, a1, and a2 registers will be same as passed by
|
||||
* previous booting stage.
|
||||
* The previous arg1 should be returned in 'a0'.
|
||||
*/
|
||||
fw_prev_arg1:
|
||||
add a0, zero, zero
|
||||
ret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.global fw_next_arg1
|
||||
|
@@ -34,19 +34,6 @@ fw_boot_hart:
|
||||
fw_save_info:
|
||||
ret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.global fw_prev_arg1
|
||||
/*
|
||||
* We can only use a0, a1, and a2 registers here.
|
||||
* The a0, a1, and a2 registers will be same as passed by
|
||||
* previous booting stage.
|
||||
* The previous arg1 should be returned in 'a0'.
|
||||
*/
|
||||
fw_prev_arg1:
|
||||
add a0, zero, zero
|
||||
ret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.global fw_next_arg1
|
||||
|
@@ -34,23 +34,6 @@ fw_boot_hart:
|
||||
fw_save_info:
|
||||
ret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.global fw_prev_arg1
|
||||
/*
|
||||
* We can only use a0, a1, and a2 registers here.
|
||||
* The a0, a1, and a2 registers will be same as passed by
|
||||
* previous booting stage.
|
||||
* The previous arg1 should be returned in 'a0'.
|
||||
*/
|
||||
fw_prev_arg1:
|
||||
#ifdef FW_PAYLOAD_FDT_PATH
|
||||
la a0, fdt_bin
|
||||
#else
|
||||
add a0, zero, zero
|
||||
#endif
|
||||
ret
|
||||
|
||||
.section .entry, "ax", %progbits
|
||||
.align 3
|
||||
.global fw_next_arg1
|
||||
@@ -102,14 +85,6 @@ fw_options:
|
||||
add a0, zero, zero
|
||||
ret
|
||||
|
||||
#ifdef FW_PAYLOAD_FDT_PATH
|
||||
.section .text, "ax", %progbits
|
||||
.align 4
|
||||
.globl fdt_bin
|
||||
fdt_bin:
|
||||
.incbin FW_PAYLOAD_FDT_PATH
|
||||
#endif
|
||||
|
||||
.section .payload, "ax", %progbits
|
||||
.align 4
|
||||
.globl payload_bin
|
||||
|
@@ -17,6 +17,13 @@ ifdef FW_TEXT_START
|
||||
firmware-genflags-y += -DFW_TEXT_START=$(FW_TEXT_START)
|
||||
endif
|
||||
|
||||
ifdef FW_FDT_PATH
|
||||
firmware-genflags-y += -DFW_FDT_PATH=\"$(FW_FDT_PATH)\"
|
||||
ifdef FW_FDT_PADDING
|
||||
firmware-genflags-y += -DFW_FDT_PADDING=$(FW_FDT_PADDING)
|
||||
endif
|
||||
endif
|
||||
|
||||
firmware-bins-$(FW_DYNAMIC) += fw_dynamic.bin
|
||||
|
||||
firmware-bins-$(FW_JUMP) += fw_jump.bin
|
||||
@@ -41,14 +48,6 @@ ifdef FW_PAYLOAD_ALIGN
|
||||
firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_ALIGN=$(FW_PAYLOAD_ALIGN)
|
||||
endif
|
||||
|
||||
ifndef FW_PAYLOAD_FDT_PATH
|
||||
ifdef FW_PAYLOAD_FDT
|
||||
FW_PAYLOAD_FDT_PATH=$(platform_build_dir)/$(FW_PAYLOAD_FDT)
|
||||
endif
|
||||
endif
|
||||
ifdef FW_PAYLOAD_FDT_PATH
|
||||
firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_FDT_PATH=\"$(FW_PAYLOAD_FDT_PATH)\"
|
||||
endif
|
||||
ifdef FW_PAYLOAD_FDT_ADDR
|
||||
firmware-genflags-$(FW_PAYLOAD) += -DFW_PAYLOAD_FDT_ADDR=$(FW_PAYLOAD_FDT_ADDR)
|
||||
endif
|
||||
|
@@ -28,9 +28,9 @@
|
||||
#error "Unexpected __riscv_xlen"
|
||||
#endif
|
||||
|
||||
#define PAGE_SHIFT (12)
|
||||
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
|
||||
#define PAGE_MASK (~(PAGE_SIZE - 1))
|
||||
#define PAGE_SHIFT (12)
|
||||
#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
|
||||
#define PAGE_MASK (~(PAGE_SIZE - 1))
|
||||
|
||||
#define REG_L __REG_SEL(ld, lw)
|
||||
#define REG_S __REG_SEL(sd, sw)
|
||||
@@ -38,7 +38,6 @@
|
||||
#define LGREG __REG_SEL(3, 2)
|
||||
|
||||
#if __SIZEOF_POINTER__ == 8
|
||||
#define BITS_PER_LONG 64
|
||||
#ifdef __ASSEMBLY__
|
||||
#define RISCV_PTR .dword
|
||||
#define RISCV_SZPTR 8
|
||||
@@ -49,7 +48,6 @@
|
||||
#define RISCV_LGPTR "3"
|
||||
#endif
|
||||
#elif __SIZEOF_POINTER__ == 4
|
||||
#define BITS_PER_LONG 32
|
||||
#ifdef __ASSEMBLY__
|
||||
#define RISCV_PTR .word
|
||||
#define RISCV_SZPTR 4
|
||||
@@ -159,6 +157,8 @@ void csr_write_num(int csr_num, unsigned long val);
|
||||
__asm__ __volatile__("wfi" ::: "memory"); \
|
||||
} while (0)
|
||||
|
||||
/* Get current HART id */
|
||||
#define current_hartid() ((unsigned int)csr_read(CSR_MHARTID))
|
||||
|
||||
/* determine CPU extension, return non-zero support */
|
||||
int misa_extension_imp(char ext);
|
||||
@@ -173,25 +173,14 @@ int misa_extension_imp(char ext);
|
||||
/* Get MXL field of misa, return -1 on error */
|
||||
int misa_xlen(void);
|
||||
|
||||
static inline void misa_string(char *out, unsigned int out_sz)
|
||||
{
|
||||
unsigned long i;
|
||||
|
||||
for (i = 0; i < 26; i++) {
|
||||
if (misa_extension_imp('A' + i)) {
|
||||
*out = 'A' + i;
|
||||
out++;
|
||||
}
|
||||
}
|
||||
*out = '\0';
|
||||
out++;
|
||||
}
|
||||
/* Get RISC-V ISA string representation */
|
||||
void misa_string(int xlen, char *out, unsigned int out_sz);
|
||||
|
||||
int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
|
||||
unsigned long log2len);
|
||||
|
||||
int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
|
||||
unsigned long *log2len_out);
|
||||
unsigned long *log2len);
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
|
@@ -29,9 +29,9 @@ long atomic_add_return(atomic_t *atom, long value);
|
||||
|
||||
long atomic_sub_return(atomic_t *atom, long value);
|
||||
|
||||
long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval);
|
||||
long atomic_cmpxchg(atomic_t *atom, long oldval, long newval);
|
||||
|
||||
long arch_atomic_xchg(atomic_t *atom, long newval);
|
||||
long atomic_xchg(atomic_t *atom, long newval);
|
||||
|
||||
unsigned int atomic_raw_xchg_uint(volatile unsigned int *ptr,
|
||||
unsigned int newval);
|
||||
|
@@ -25,6 +25,7 @@
|
||||
#define MSTATUS_MPP (_UL(3) << MSTATUS_MPP_SHIFT)
|
||||
#define MSTATUS_FS _UL(0x00006000)
|
||||
#define MSTATUS_XS _UL(0x00018000)
|
||||
#define MSTATUS_VS _UL(0x01800000)
|
||||
#define MSTATUS_MPRV _UL(0x00020000)
|
||||
#define MSTATUS_SUM _UL(0x00040000)
|
||||
#define MSTATUS_MXR _UL(0x00080000)
|
||||
@@ -53,18 +54,27 @@
|
||||
#define SSTATUS_SPP MSTATUS_SPP
|
||||
#define SSTATUS_FS MSTATUS_FS
|
||||
#define SSTATUS_XS MSTATUS_XS
|
||||
#define SSTATUS_VS MSTATUS_VS
|
||||
#define SSTATUS_SUM MSTATUS_SUM
|
||||
#define SSTATUS_MXR MSTATUS_MXR
|
||||
#define SSTATUS32_SD MSTATUS32_SD
|
||||
#define SSTATUS64_UXL MSTATUS_UXL
|
||||
#define SSTATUS64_SD MSTATUS64_SD
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
#define HSTATUS_VSXL _UL(0x300000000)
|
||||
#define HSTATUS_VSXL_SHIFT 32
|
||||
#endif
|
||||
#define HSTATUS_VTSR _UL(0x00400000)
|
||||
#define HSTATUS_VTW _UL(0x00200000)
|
||||
#define HSTATUS_VTVM _UL(0x00100000)
|
||||
#define HSTATUS_SP2V _UL(0x00000200)
|
||||
#define HSTATUS_SP2P _UL(0x00000100)
|
||||
#define HSTATUS_VGEIN _UL(0x0003f000)
|
||||
#define HSTATUS_VGEIN_SHIFT 12
|
||||
#define HSTATUS_HU _UL(0x00000200)
|
||||
#define HSTATUS_SPVP _UL(0x00000100)
|
||||
#define HSTATUS_SPV _UL(0x00000080)
|
||||
#define HSTATUS_SPRV _UL(0x00000001)
|
||||
#define HSTATUS_GVA _UL(0x00000040)
|
||||
#define HSTATUS_VSBE _UL(0x00000020)
|
||||
|
||||
#define IRQ_S_SOFT 1
|
||||
#define IRQ_VS_SOFT 2
|
||||
@@ -109,6 +119,21 @@
|
||||
#define SATP_MODE_SV57 _UL(10)
|
||||
#define SATP_MODE_SV64 _UL(11)
|
||||
|
||||
#define HGATP_MODE_OFF _UL(0)
|
||||
#define HGATP_MODE_SV32X4 _UL(1)
|
||||
#define HGATP_MODE_SV39X4 _UL(8)
|
||||
#define HGATP_MODE_SV48X4 _UL(9)
|
||||
|
||||
#define HGATP32_MODE_SHIFT 31
|
||||
#define HGATP32_VMID_SHIFT 22
|
||||
#define HGATP32_VMID_MASK _UL(0x1FC00000)
|
||||
#define HGATP32_PPN _UL(0x003FFFFF)
|
||||
|
||||
#define HGATP64_MODE_SHIFT 60
|
||||
#define HGATP64_VMID_SHIFT 44
|
||||
#define HGATP64_VMID_MASK _ULL(0x03FFF00000000000)
|
||||
#define HGATP64_PPN _ULL(0x00000FFFFFFFFFFF)
|
||||
|
||||
#define PMP_R _UL(0x01)
|
||||
#define PMP_W _UL(0x02)
|
||||
#define PMP_X _UL(0x04)
|
||||
@@ -119,50 +144,54 @@
|
||||
#define PMP_L _UL(0x80)
|
||||
|
||||
#define PMP_SHIFT 2
|
||||
#define PMP_COUNT 16
|
||||
|
||||
/* page table entry (PTE) fields */
|
||||
#define PTE_V _UL(0x001) /* Valid */
|
||||
#define PTE_R _UL(0x002) /* Read */
|
||||
#define PTE_W _UL(0x004) /* Write */
|
||||
#define PTE_X _UL(0x008) /* Execute */
|
||||
#define PTE_U _UL(0x010) /* User */
|
||||
#define PTE_G _UL(0x020) /* Global */
|
||||
#define PTE_A _UL(0x040) /* Accessed */
|
||||
#define PTE_D _UL(0x080) /* Dirty */
|
||||
#define PTE_SOFT _UL(0x300) /* Reserved for Software */
|
||||
|
||||
#define PTE_PPN_SHIFT 10
|
||||
|
||||
#define PTE_TABLE(PTE) \
|
||||
(((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
|
||||
#define PMP_COUNT 64
|
||||
#if __riscv_xlen == 64
|
||||
#define PMP_ADDR_MASK ((_ULL(0x1) << 54) - 1)
|
||||
#else
|
||||
#define PMP_ADDR_MASK _UL(0xFFFFFFFF)
|
||||
#endif
|
||||
|
||||
#if __riscv_xlen == 64
|
||||
#define MSTATUS_SD MSTATUS64_SD
|
||||
#define SSTATUS_SD SSTATUS64_SD
|
||||
#define RISCV_PGLEVEL_BITS 9
|
||||
#define SATP_MODE SATP64_MODE
|
||||
|
||||
#define HGATP_PPN HGATP64_PPN
|
||||
#define HGATP_VMID_SHIFT HGATP64_VMID_SHIFT
|
||||
#define HGATP_VMID_MASK HGATP64_VMID_MASK
|
||||
#define HGATP_MODE_SHIFT HGATP64_MODE_SHIFT
|
||||
#else
|
||||
#define MSTATUS_SD MSTATUS32_SD
|
||||
#define SSTATUS_SD SSTATUS32_SD
|
||||
#define RISCV_PGLEVEL_BITS 10
|
||||
#define SATP_MODE SATP32_MODE
|
||||
#endif
|
||||
#define RISCV_PGSHIFT 12
|
||||
#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
|
||||
|
||||
#define CSR_USTATUS 0x0
|
||||
#define CSR_FFLAGS 0x1
|
||||
#define CSR_FRM 0x2
|
||||
#define CSR_FCSR 0x3
|
||||
#define HGATP_PPN HGATP32_PPN
|
||||
#define HGATP_VMID_SHIFT HGATP32_VMID_SHIFT
|
||||
#define HGATP_VMID_MASK HGATP32_VMID_MASK
|
||||
#define HGATP_MODE_SHIFT HGATP32_MODE_SHIFT
|
||||
#endif
|
||||
|
||||
/* ===== User-level CSRs ===== */
|
||||
|
||||
/* User Trap Setup (N-extension) */
|
||||
#define CSR_USTATUS 0x000
|
||||
#define CSR_UIE 0x004
|
||||
#define CSR_UTVEC 0x005
|
||||
|
||||
/* User Trap Handling (N-extension) */
|
||||
#define CSR_USCRATCH 0x040
|
||||
#define CSR_UEPC 0x041
|
||||
#define CSR_UCAUSE 0x042
|
||||
#define CSR_UTVAL 0x043
|
||||
#define CSR_UIP 0x044
|
||||
|
||||
/* User Floating-point CSRs */
|
||||
#define CSR_FFLAGS 0x001
|
||||
#define CSR_FRM 0x002
|
||||
#define CSR_FCSR 0x003
|
||||
|
||||
/* User Counters/Timers */
|
||||
#define CSR_CYCLE 0xc00
|
||||
#define CSR_UIE 0x4
|
||||
#define CSR_UTVEC 0x5
|
||||
#define CSR_USCRATCH 0x40
|
||||
#define CSR_UEPC 0x41
|
||||
#define CSR_UCAUSE 0x42
|
||||
#define CSR_UTVAL 0x43
|
||||
#define CSR_UIP 0x44
|
||||
#define CSR_TIME 0xc01
|
||||
#define CSR_INSTRET 0xc02
|
||||
#define CSR_HPMCOUNTER3 0xc03
|
||||
@@ -194,148 +223,6 @@
|
||||
#define CSR_HPMCOUNTER29 0xc1d
|
||||
#define CSR_HPMCOUNTER30 0xc1e
|
||||
#define CSR_HPMCOUNTER31 0xc1f
|
||||
#define CSR_SSTATUS 0x100
|
||||
#define CSR_SIE 0x104
|
||||
#define CSR_STVEC 0x105
|
||||
#define CSR_SCOUNTEREN 0x106
|
||||
#define CSR_SSCRATCH 0x140
|
||||
#define CSR_SEPC 0x141
|
||||
#define CSR_SCAUSE 0x142
|
||||
#define CSR_STVAL 0x143
|
||||
#define CSR_SIP 0x144
|
||||
#define CSR_SATP 0x180
|
||||
|
||||
#define CSR_HSTATUS 0x600
|
||||
#define CSR_HEDELEG 0x602
|
||||
#define CSR_HIDELEG 0x603
|
||||
#define CSR_HIE 0x604
|
||||
#define CSR_HTIMEDELTA 0x605
|
||||
#define CSR_HTIMEDELTAH 0x615
|
||||
#define CSR_HCOUNTERNEN 0x606
|
||||
#define CSR_HGEIE 0x607
|
||||
#define CSR_HTVAL 0x643
|
||||
#define CSR_HIP 0x644
|
||||
#define CSR_HTINST 0x64a
|
||||
#define CSR_HGATP 0x680
|
||||
#define CSR_HGEIP 0xe07
|
||||
|
||||
#define CSR_VSSTATUS 0x200
|
||||
#define CSR_VSIE 0x204
|
||||
#define CSR_VSTVEC 0x205
|
||||
#define CSR_VSSCRATCH 0x240
|
||||
#define CSR_VSEPC 0x241
|
||||
#define CSR_VSCAUSE 0x242
|
||||
#define CSR_VSTVAL 0x243
|
||||
#define CSR_VSIP 0x244
|
||||
#define CSR_VSATP 0x280
|
||||
|
||||
#define CSR_MSTATUS 0x300
|
||||
#define CSR_MISA 0x301
|
||||
#define CSR_MEDELEG 0x302
|
||||
#define CSR_MIDELEG 0x303
|
||||
#define CSR_MIE 0x304
|
||||
#define CSR_MTVEC 0x305
|
||||
#define CSR_MCOUNTEREN 0x306
|
||||
#define CSR_MSTATUSH 0x310
|
||||
#define CSR_MSCRATCH 0x340
|
||||
#define CSR_MEPC 0x341
|
||||
#define CSR_MCAUSE 0x342
|
||||
#define CSR_MTVAL 0x343
|
||||
#define CSR_MIP 0x344
|
||||
#define CSR_MTINST 0x34a
|
||||
#define CSR_MTVAL2 0x34b
|
||||
#define CSR_PMPCFG0 0x3a0
|
||||
#define CSR_PMPCFG1 0x3a1
|
||||
#define CSR_PMPCFG2 0x3a2
|
||||
#define CSR_PMPCFG3 0x3a3
|
||||
#define CSR_PMPADDR0 0x3b0
|
||||
#define CSR_PMPADDR1 0x3b1
|
||||
#define CSR_PMPADDR2 0x3b2
|
||||
#define CSR_PMPADDR3 0x3b3
|
||||
#define CSR_PMPADDR4 0x3b4
|
||||
#define CSR_PMPADDR5 0x3b5
|
||||
#define CSR_PMPADDR6 0x3b6
|
||||
#define CSR_PMPADDR7 0x3b7
|
||||
#define CSR_PMPADDR8 0x3b8
|
||||
#define CSR_PMPADDR9 0x3b9
|
||||
#define CSR_PMPADDR10 0x3ba
|
||||
#define CSR_PMPADDR11 0x3bb
|
||||
#define CSR_PMPADDR12 0x3bc
|
||||
#define CSR_PMPADDR13 0x3bd
|
||||
#define CSR_PMPADDR14 0x3be
|
||||
#define CSR_PMPADDR15 0x3bf
|
||||
#define CSR_TSELECT 0x7a0
|
||||
#define CSR_TDATA1 0x7a1
|
||||
#define CSR_TDATA2 0x7a2
|
||||
#define CSR_TDATA3 0x7a3
|
||||
#define CSR_DCSR 0x7b0
|
||||
#define CSR_DPC 0x7b1
|
||||
#define CSR_DSCRATCH 0x7b2
|
||||
|
||||
#define CSR_MCYCLE 0xb00
|
||||
#define CSR_MINSTRET 0xb02
|
||||
#define CSR_MHPMCOUNTER3 0xb03
|
||||
#define CSR_MHPMCOUNTER4 0xb04
|
||||
#define CSR_MHPMCOUNTER5 0xb05
|
||||
#define CSR_MHPMCOUNTER6 0xb06
|
||||
#define CSR_MHPMCOUNTER7 0xb07
|
||||
#define CSR_MHPMCOUNTER8 0xb08
|
||||
#define CSR_MHPMCOUNTER9 0xb09
|
||||
#define CSR_MHPMCOUNTER10 0xb0a
|
||||
#define CSR_MHPMCOUNTER11 0xb0b
|
||||
#define CSR_MHPMCOUNTER12 0xb0c
|
||||
#define CSR_MHPMCOUNTER13 0xb0d
|
||||
#define CSR_MHPMCOUNTER14 0xb0e
|
||||
#define CSR_MHPMCOUNTER15 0xb0f
|
||||
#define CSR_MHPMCOUNTER16 0xb10
|
||||
#define CSR_MHPMCOUNTER17 0xb11
|
||||
#define CSR_MHPMCOUNTER18 0xb12
|
||||
#define CSR_MHPMCOUNTER19 0xb13
|
||||
#define CSR_MHPMCOUNTER20 0xb14
|
||||
#define CSR_MHPMCOUNTER21 0xb15
|
||||
#define CSR_MHPMCOUNTER22 0xb16
|
||||
#define CSR_MHPMCOUNTER23 0xb17
|
||||
#define CSR_MHPMCOUNTER24 0xb18
|
||||
#define CSR_MHPMCOUNTER25 0xb19
|
||||
#define CSR_MHPMCOUNTER26 0xb1a
|
||||
#define CSR_MHPMCOUNTER27 0xb1b
|
||||
#define CSR_MHPMCOUNTER28 0xb1c
|
||||
#define CSR_MHPMCOUNTER29 0xb1d
|
||||
#define CSR_MHPMCOUNTER30 0xb1e
|
||||
#define CSR_MHPMCOUNTER31 0xb1f
|
||||
#define CSR_MHPMEVENT3 0x323
|
||||
#define CSR_MHPMEVENT4 0x324
|
||||
#define CSR_MHPMEVENT5 0x325
|
||||
#define CSR_MHPMEVENT6 0x326
|
||||
#define CSR_MHPMEVENT7 0x327
|
||||
#define CSR_MHPMEVENT8 0x328
|
||||
#define CSR_MHPMEVENT9 0x329
|
||||
#define CSR_MHPMEVENT10 0x32a
|
||||
#define CSR_MHPMEVENT11 0x32b
|
||||
#define CSR_MHPMEVENT12 0x32c
|
||||
#define CSR_MHPMEVENT13 0x32d
|
||||
#define CSR_MHPMEVENT14 0x32e
|
||||
#define CSR_MHPMEVENT15 0x32f
|
||||
#define CSR_MHPMEVENT16 0x330
|
||||
#define CSR_MHPMEVENT17 0x331
|
||||
#define CSR_MHPMEVENT18 0x332
|
||||
#define CSR_MHPMEVENT19 0x333
|
||||
#define CSR_MHPMEVENT20 0x334
|
||||
#define CSR_MHPMEVENT21 0x335
|
||||
#define CSR_MHPMEVENT22 0x336
|
||||
#define CSR_MHPMEVENT23 0x337
|
||||
#define CSR_MHPMEVENT24 0x338
|
||||
#define CSR_MHPMEVENT25 0x339
|
||||
#define CSR_MHPMEVENT26 0x33a
|
||||
#define CSR_MHPMEVENT27 0x33b
|
||||
#define CSR_MHPMEVENT28 0x33c
|
||||
#define CSR_MHPMEVENT29 0x33d
|
||||
#define CSR_MHPMEVENT30 0x33e
|
||||
#define CSR_MHPMEVENT31 0x33f
|
||||
#define CSR_MVENDORID 0xf11
|
||||
#define CSR_MARCHID 0xf12
|
||||
#define CSR_MIMPID 0xf13
|
||||
#define CSR_MHARTID 0xf14
|
||||
#define CSR_CYCLEH 0xc80
|
||||
#define CSR_TIMEH 0xc81
|
||||
#define CSR_INSTRETH 0xc82
|
||||
@@ -368,6 +255,203 @@
|
||||
#define CSR_HPMCOUNTER29H 0xc9d
|
||||
#define CSR_HPMCOUNTER30H 0xc9e
|
||||
#define CSR_HPMCOUNTER31H 0xc9f
|
||||
|
||||
/* ===== Supervisor-level CSRs ===== */
|
||||
|
||||
/* Supervisor Trap Setup */
|
||||
#define CSR_SSTATUS 0x100
|
||||
#define CSR_SEDELEG 0x102
|
||||
#define CSR_SIDELEG 0x103
|
||||
#define CSR_SIE 0x104
|
||||
#define CSR_STVEC 0x105
|
||||
#define CSR_SCOUNTEREN 0x106
|
||||
|
||||
/* Supervisor Trap Handling */
|
||||
#define CSR_SSCRATCH 0x140
|
||||
#define CSR_SEPC 0x141
|
||||
#define CSR_SCAUSE 0x142
|
||||
#define CSR_STVAL 0x143
|
||||
#define CSR_SIP 0x144
|
||||
|
||||
/* Supervisor Protection and Translation */
|
||||
#define CSR_SATP 0x180
|
||||
|
||||
/* ===== Hypervisor-level CSRs ===== */
|
||||
|
||||
/* Hypervisor Trap Setup (H-extension) */
|
||||
#define CSR_HSTATUS 0x600
|
||||
#define CSR_HEDELEG 0x602
|
||||
#define CSR_HIDELEG 0x603
|
||||
#define CSR_HIE 0x604
|
||||
#define CSR_HCOUNTEREN 0x606
|
||||
#define CSR_HGEIE 0x607
|
||||
|
||||
/* Hypervisor Trap Handling (H-extension) */
|
||||
#define CSR_HTVAL 0x643
|
||||
#define CSR_HIP 0x644
|
||||
#define CSR_HVIP 0x645
|
||||
#define CSR_HTINST 0x64a
|
||||
#define CSR_HGEIP 0xe12
|
||||
|
||||
/* Hypervisor Protection and Translation (H-extension) */
|
||||
#define CSR_HGATP 0x680
|
||||
|
||||
/* Hypervisor Counter/Timer Virtualization Registers (H-extension) */
|
||||
#define CSR_HTIMEDELTA 0x605
|
||||
#define CSR_HTIMEDELTAH 0x615
|
||||
|
||||
/* Virtual Supervisor Registers (H-extension) */
|
||||
#define CSR_VSSTATUS 0x200
|
||||
#define CSR_VSIE 0x204
|
||||
#define CSR_VSTVEC 0x205
|
||||
#define CSR_VSSCRATCH 0x240
|
||||
#define CSR_VSEPC 0x241
|
||||
#define CSR_VSCAUSE 0x242
|
||||
#define CSR_VSTVAL 0x243
|
||||
#define CSR_VSIP 0x244
|
||||
#define CSR_VSATP 0x280
|
||||
|
||||
/* ===== Machine-level CSRs ===== */
|
||||
|
||||
/* Machine Information Registers */
|
||||
#define CSR_MVENDORID 0xf11
|
||||
#define CSR_MARCHID 0xf12
|
||||
#define CSR_MIMPID 0xf13
|
||||
#define CSR_MHARTID 0xf14
|
||||
|
||||
/* Machine Trap Setup */
|
||||
#define CSR_MSTATUS 0x300
|
||||
#define CSR_MISA 0x301
|
||||
#define CSR_MEDELEG 0x302
|
||||
#define CSR_MIDELEG 0x303
|
||||
#define CSR_MIE 0x304
|
||||
#define CSR_MTVEC 0x305
|
||||
#define CSR_MCOUNTEREN 0x306
|
||||
#define CSR_MSTATUSH 0x310
|
||||
|
||||
/* Machine Trap Handling */
|
||||
#define CSR_MSCRATCH 0x340
|
||||
#define CSR_MEPC 0x341
|
||||
#define CSR_MCAUSE 0x342
|
||||
#define CSR_MTVAL 0x343
|
||||
#define CSR_MIP 0x344
|
||||
#define CSR_MTINST 0x34a
|
||||
#define CSR_MTVAL2 0x34b
|
||||
|
||||
/* Machine Memory Protection */
|
||||
#define CSR_PMPCFG0 0x3a0
|
||||
#define CSR_PMPCFG1 0x3a1
|
||||
#define CSR_PMPCFG2 0x3a2
|
||||
#define CSR_PMPCFG3 0x3a3
|
||||
#define CSR_PMPCFG4 0x3a4
|
||||
#define CSR_PMPCFG5 0x3a5
|
||||
#define CSR_PMPCFG6 0x3a6
|
||||
#define CSR_PMPCFG7 0x3a7
|
||||
#define CSR_PMPCFG8 0x3a8
|
||||
#define CSR_PMPCFG9 0x3a9
|
||||
#define CSR_PMPCFG10 0x3aa
|
||||
#define CSR_PMPCFG11 0x3ab
|
||||
#define CSR_PMPCFG12 0x3ac
|
||||
#define CSR_PMPCFG13 0x3ad
|
||||
#define CSR_PMPCFG14 0x3ae
|
||||
#define CSR_PMPCFG15 0x3af
|
||||
#define CSR_PMPADDR0 0x3b0
|
||||
#define CSR_PMPADDR1 0x3b1
|
||||
#define CSR_PMPADDR2 0x3b2
|
||||
#define CSR_PMPADDR3 0x3b3
|
||||
#define CSR_PMPADDR4 0x3b4
|
||||
#define CSR_PMPADDR5 0x3b5
|
||||
#define CSR_PMPADDR6 0x3b6
|
||||
#define CSR_PMPADDR7 0x3b7
|
||||
#define CSR_PMPADDR8 0x3b8
|
||||
#define CSR_PMPADDR9 0x3b9
|
||||
#define CSR_PMPADDR10 0x3ba
|
||||
#define CSR_PMPADDR11 0x3bb
|
||||
#define CSR_PMPADDR12 0x3bc
|
||||
#define CSR_PMPADDR13 0x3bd
|
||||
#define CSR_PMPADDR14 0x3be
|
||||
#define CSR_PMPADDR15 0x3bf
|
||||
#define CSR_PMPADDR16 0x3c0
|
||||
#define CSR_PMPADDR17 0x3c1
|
||||
#define CSR_PMPADDR18 0x3c2
|
||||
#define CSR_PMPADDR19 0x3c3
|
||||
#define CSR_PMPADDR20 0x3c4
|
||||
#define CSR_PMPADDR21 0x3c5
|
||||
#define CSR_PMPADDR22 0x3c6
|
||||
#define CSR_PMPADDR23 0x3c7
|
||||
#define CSR_PMPADDR24 0x3c8
|
||||
#define CSR_PMPADDR25 0x3c9
|
||||
#define CSR_PMPADDR26 0x3ca
|
||||
#define CSR_PMPADDR27 0x3cb
|
||||
#define CSR_PMPADDR28 0x3cc
|
||||
#define CSR_PMPADDR29 0x3cd
|
||||
#define CSR_PMPADDR30 0x3ce
|
||||
#define CSR_PMPADDR31 0x3cf
|
||||
#define CSR_PMPADDR32 0x3d0
|
||||
#define CSR_PMPADDR33 0x3d1
|
||||
#define CSR_PMPADDR34 0x3d2
|
||||
#define CSR_PMPADDR35 0x3d3
|
||||
#define CSR_PMPADDR36 0x3d4
|
||||
#define CSR_PMPADDR37 0x3d5
|
||||
#define CSR_PMPADDR38 0x3d6
|
||||
#define CSR_PMPADDR39 0x3d7
|
||||
#define CSR_PMPADDR40 0x3d8
|
||||
#define CSR_PMPADDR41 0x3d9
|
||||
#define CSR_PMPADDR42 0x3da
|
||||
#define CSR_PMPADDR43 0x3db
|
||||
#define CSR_PMPADDR44 0x3dc
|
||||
#define CSR_PMPADDR45 0x3dd
|
||||
#define CSR_PMPADDR46 0x3de
|
||||
#define CSR_PMPADDR47 0x3df
|
||||
#define CSR_PMPADDR48 0x3e0
|
||||
#define CSR_PMPADDR49 0x3e1
|
||||
#define CSR_PMPADDR50 0x3e2
|
||||
#define CSR_PMPADDR51 0x3e3
|
||||
#define CSR_PMPADDR52 0x3e4
|
||||
#define CSR_PMPADDR53 0x3e5
|
||||
#define CSR_PMPADDR54 0x3e6
|
||||
#define CSR_PMPADDR55 0x3e7
|
||||
#define CSR_PMPADDR56 0x3e8
|
||||
#define CSR_PMPADDR57 0x3e9
|
||||
#define CSR_PMPADDR58 0x3ea
|
||||
#define CSR_PMPADDR59 0x3eb
|
||||
#define CSR_PMPADDR60 0x3ec
|
||||
#define CSR_PMPADDR61 0x3ed
|
||||
#define CSR_PMPADDR62 0x3ee
|
||||
#define CSR_PMPADDR63 0x3ef
|
||||
|
||||
/* Machine Counters/Timers */
|
||||
#define CSR_MCYCLE 0xb00
|
||||
#define CSR_MINSTRET 0xb02
|
||||
#define CSR_MHPMCOUNTER3 0xb03
|
||||
#define CSR_MHPMCOUNTER4 0xb04
|
||||
#define CSR_MHPMCOUNTER5 0xb05
|
||||
#define CSR_MHPMCOUNTER6 0xb06
|
||||
#define CSR_MHPMCOUNTER7 0xb07
|
||||
#define CSR_MHPMCOUNTER8 0xb08
|
||||
#define CSR_MHPMCOUNTER9 0xb09
|
||||
#define CSR_MHPMCOUNTER10 0xb0a
|
||||
#define CSR_MHPMCOUNTER11 0xb0b
|
||||
#define CSR_MHPMCOUNTER12 0xb0c
|
||||
#define CSR_MHPMCOUNTER13 0xb0d
|
||||
#define CSR_MHPMCOUNTER14 0xb0e
|
||||
#define CSR_MHPMCOUNTER15 0xb0f
|
||||
#define CSR_MHPMCOUNTER16 0xb10
|
||||
#define CSR_MHPMCOUNTER17 0xb11
|
||||
#define CSR_MHPMCOUNTER18 0xb12
|
||||
#define CSR_MHPMCOUNTER19 0xb13
|
||||
#define CSR_MHPMCOUNTER20 0xb14
|
||||
#define CSR_MHPMCOUNTER21 0xb15
|
||||
#define CSR_MHPMCOUNTER22 0xb16
|
||||
#define CSR_MHPMCOUNTER23 0xb17
|
||||
#define CSR_MHPMCOUNTER24 0xb18
|
||||
#define CSR_MHPMCOUNTER25 0xb19
|
||||
#define CSR_MHPMCOUNTER26 0xb1a
|
||||
#define CSR_MHPMCOUNTER27 0xb1b
|
||||
#define CSR_MHPMCOUNTER28 0xb1c
|
||||
#define CSR_MHPMCOUNTER29 0xb1d
|
||||
#define CSR_MHPMCOUNTER30 0xb1e
|
||||
#define CSR_MHPMCOUNTER31 0xb1f
|
||||
#define CSR_MCYCLEH 0xb80
|
||||
#define CSR_MINSTRETH 0xb82
|
||||
#define CSR_MHPMCOUNTER3H 0xb83
|
||||
@@ -400,6 +484,52 @@
|
||||
#define CSR_MHPMCOUNTER30H 0xb9e
|
||||
#define CSR_MHPMCOUNTER31H 0xb9f
|
||||
|
||||
/* Machine Counter Setup */
|
||||
#define CSR_MCOUNTINHIBIT 0x320
|
||||
#define CSR_MHPMEVENT3 0x323
|
||||
#define CSR_MHPMEVENT4 0x324
|
||||
#define CSR_MHPMEVENT5 0x325
|
||||
#define CSR_MHPMEVENT6 0x326
|
||||
#define CSR_MHPMEVENT7 0x327
|
||||
#define CSR_MHPMEVENT8 0x328
|
||||
#define CSR_MHPMEVENT9 0x329
|
||||
#define CSR_MHPMEVENT10 0x32a
|
||||
#define CSR_MHPMEVENT11 0x32b
|
||||
#define CSR_MHPMEVENT12 0x32c
|
||||
#define CSR_MHPMEVENT13 0x32d
|
||||
#define CSR_MHPMEVENT14 0x32e
|
||||
#define CSR_MHPMEVENT15 0x32f
|
||||
#define CSR_MHPMEVENT16 0x330
|
||||
#define CSR_MHPMEVENT17 0x331
|
||||
#define CSR_MHPMEVENT18 0x332
|
||||
#define CSR_MHPMEVENT19 0x333
|
||||
#define CSR_MHPMEVENT20 0x334
|
||||
#define CSR_MHPMEVENT21 0x335
|
||||
#define CSR_MHPMEVENT22 0x336
|
||||
#define CSR_MHPMEVENT23 0x337
|
||||
#define CSR_MHPMEVENT24 0x338
|
||||
#define CSR_MHPMEVENT25 0x339
|
||||
#define CSR_MHPMEVENT26 0x33a
|
||||
#define CSR_MHPMEVENT27 0x33b
|
||||
#define CSR_MHPMEVENT28 0x33c
|
||||
#define CSR_MHPMEVENT29 0x33d
|
||||
#define CSR_MHPMEVENT30 0x33e
|
||||
#define CSR_MHPMEVENT31 0x33f
|
||||
|
||||
/* Debug/Trace Registers */
|
||||
#define CSR_TSELECT 0x7a0
|
||||
#define CSR_TDATA1 0x7a1
|
||||
#define CSR_TDATA2 0x7a2
|
||||
#define CSR_TDATA3 0x7a3
|
||||
|
||||
/* Debug Mode Registers */
|
||||
#define CSR_DCSR 0x7b0
|
||||
#define CSR_DPC 0x7b1
|
||||
#define CSR_DSCRATCH0 0x7b2
|
||||
#define CSR_DSCRATCH1 0x7b3
|
||||
|
||||
/* ===== Trap/Exception Causes ===== */
|
||||
|
||||
#define CAUSE_MISALIGNED_FETCH 0x0
|
||||
#define CAUSE_FETCH_ACCESS 0x1
|
||||
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
|
||||
@@ -409,16 +539,19 @@
|
||||
#define CAUSE_MISALIGNED_STORE 0x6
|
||||
#define CAUSE_STORE_ACCESS 0x7
|
||||
#define CAUSE_USER_ECALL 0x8
|
||||
#define CAUSE_HYPERVISOR_ECALL 0x9
|
||||
#define CAUSE_SUPERVISOR_ECALL 0xa
|
||||
#define CAUSE_SUPERVISOR_ECALL 0x9
|
||||
#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa
|
||||
#define CAUSE_MACHINE_ECALL 0xb
|
||||
#define CAUSE_FETCH_PAGE_FAULT 0xc
|
||||
#define CAUSE_LOAD_PAGE_FAULT 0xd
|
||||
#define CAUSE_STORE_PAGE_FAULT 0xf
|
||||
#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
|
||||
#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
|
||||
#define CAUSE_VIRTUAL_INST_FAULT 0x16
|
||||
#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
|
||||
|
||||
/* ===== Instruction Encodings ===== */
|
||||
|
||||
#define INSN_MATCH_LB 0x3
|
||||
#define INSN_MASK_LB 0x707f
|
||||
#define INSN_MATCH_LH 0x1003
|
||||
|
128
include/sbi/sbi_bitmap.h
Normal file
128
include/sbi/sbi_bitmap.h
Normal file
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_BITMAP_H__
|
||||
#define __SBI_BITMAP_H__
|
||||
|
||||
#include <sbi/sbi_bitops.h>
|
||||
|
||||
#define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) % BITS_PER_LONG))
|
||||
#define BITMAP_LAST_WORD_MASK(nbits) \
|
||||
( \
|
||||
((nbits) % BITS_PER_LONG) ? \
|
||||
((1UL << ((nbits) % BITS_PER_LONG)) - 1) : ~0UL \
|
||||
)
|
||||
|
||||
#define small_const_nbits(nbits) \
|
||||
(__builtin_constant_p(nbits) && (nbits) <= BITS_PER_LONG)
|
||||
|
||||
#define DECLARE_BITMAP(name, nbits) unsigned long name[BITS_TO_LONGS(nbits)]
|
||||
#define DEFINE_BITMAP(name) extern unsigned long name[]
|
||||
|
||||
static inline unsigned long bitmap_estimate_size(int nbits)
|
||||
{
|
||||
return (BITS_TO_LONGS(nbits) * sizeof(unsigned long));
|
||||
}
|
||||
|
||||
void __bitmap_and(unsigned long *dst, const unsigned long *bitmap1,
|
||||
const unsigned long *bitmap2, int bits);
|
||||
void __bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
|
||||
const unsigned long *bitmap2, int bits);
|
||||
void __bitmap_xor(unsigned long *dst, const unsigned long *bitmap1,
|
||||
const unsigned long *bitmap2, int bits);
|
||||
|
||||
static inline void bitmap_set(unsigned long *bmap, int start, int len)
|
||||
{
|
||||
int bit;
|
||||
for (bit = start; bit < (start + len); bit++)
|
||||
bmap[BIT_WORD(bit)] |= (0x1UL << BIT_WORD_OFFSET(bit));
|
||||
}
|
||||
|
||||
static inline void bitmap_clear(unsigned long *bmap, int start, int len)
|
||||
{
|
||||
int bit;
|
||||
for (bit = start; bit < (start + len); bit++)
|
||||
bmap[BIT_WORD(bit)] &= ~(0x1UL << BIT_WORD_OFFSET(bit));
|
||||
}
|
||||
|
||||
static inline void bitmap_zero(unsigned long *dst, int nbits)
|
||||
{
|
||||
if (small_const_nbits(nbits))
|
||||
*dst = 0UL;
|
||||
else {
|
||||
size_t i, len = BITS_TO_LONGS(nbits);
|
||||
for (i = 0; i < len; i++)
|
||||
dst[i] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void bitmap_zero_except(unsigned long *dst,
|
||||
int exception, int nbits)
|
||||
{
|
||||
if (small_const_nbits(nbits))
|
||||
*dst = 0UL;
|
||||
else {
|
||||
size_t i, len = BITS_TO_LONGS(nbits);
|
||||
for (i = 0; i < len; i++)
|
||||
dst[i] = 0;
|
||||
}
|
||||
if (exception < nbits)
|
||||
__set_bit(exception, dst);
|
||||
}
|
||||
|
||||
static inline void bitmap_fill(unsigned long *dst, int nbits)
|
||||
{
|
||||
size_t i, nlongs = BITS_TO_LONGS(nbits);
|
||||
if (!small_const_nbits(nbits)) {
|
||||
for (i = 0; i < (nlongs - 1); i++)
|
||||
dst[i] = -1UL;
|
||||
}
|
||||
dst[nlongs - 1] = BITMAP_LAST_WORD_MASK(nbits);
|
||||
}
|
||||
|
||||
static inline void bitmap_copy(unsigned long *dst,
|
||||
const unsigned long *src, int nbits)
|
||||
{
|
||||
if (small_const_nbits(nbits))
|
||||
*dst = *src;
|
||||
else {
|
||||
size_t i, len = BITS_TO_LONGS(nbits);
|
||||
for (i = 0; i < len; i++)
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
static inline void bitmap_and(unsigned long *dst, const unsigned long *src1,
|
||||
const unsigned long *src2, int nbits)
|
||||
{
|
||||
if (small_const_nbits(nbits))
|
||||
*dst = *src1 & *src2;
|
||||
else
|
||||
__bitmap_and(dst, src1, src2, nbits);
|
||||
}
|
||||
|
||||
static inline void bitmap_or(unsigned long *dst, const unsigned long *src1,
|
||||
const unsigned long *src2, int nbits)
|
||||
{
|
||||
if (small_const_nbits(nbits))
|
||||
*dst = *src1 | *src2;
|
||||
else
|
||||
__bitmap_or(dst, src1, src2, nbits);
|
||||
}
|
||||
|
||||
static inline void bitmap_xor(unsigned long *dst, const unsigned long *src1,
|
||||
const unsigned long *src2, int nbits)
|
||||
{
|
||||
if (small_const_nbits(nbits))
|
||||
*dst = *src1 ^ *src2;
|
||||
else
|
||||
__bitmap_xor(dst, src1, src2, nbits);
|
||||
}
|
||||
|
||||
#endif
|
@@ -4,14 +4,37 @@
|
||||
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra<atish.patra@wdc.com>
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_BITOPS_H__
|
||||
#define __SBI_BITOPS_H__
|
||||
|
||||
#include <sbi/sbi_bits.h>
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
#if __SIZEOF_POINTER__ == 8
|
||||
#define BITS_PER_LONG 64
|
||||
#elif __SIZEOF_POINTER__ == 4
|
||||
#define BITS_PER_LONG 32
|
||||
#else
|
||||
#error "Unexpected __SIZEOF_POINTER__"
|
||||
#endif
|
||||
|
||||
#define EXTRACT_FIELD(val, which) \
|
||||
(((val) & (which)) / ((which) & ~((which)-1)))
|
||||
#define INSERT_FIELD(val, which, fieldval) \
|
||||
(((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
|
||||
|
||||
#define BITS_TO_LONGS(nbits) (((nbits) + BITS_PER_LONG - 1) / \
|
||||
BITS_PER_LONG)
|
||||
|
||||
#define BIT(nr) (1UL << (nr))
|
||||
#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
|
||||
#define BIT_WORD(bit) ((bit) / BITS_PER_LONG)
|
||||
#define BIT_WORD_OFFSET(bit) ((bit) & (BITS_PER_LONG - 1))
|
||||
|
||||
#define GENMASK(h, l) \
|
||||
(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
|
||||
|
||||
/**
|
||||
* ffs - Find first bit set
|
||||
@@ -43,10 +66,8 @@ static inline int ffs(int x)
|
||||
x >>= 2;
|
||||
r += 2;
|
||||
}
|
||||
if (!(x & 1)) {
|
||||
x >>= 1;
|
||||
if (!(x & 1))
|
||||
r += 1;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
@@ -125,10 +146,8 @@ static inline int fls(int x)
|
||||
x <<= 2;
|
||||
r -= 2;
|
||||
}
|
||||
if (!(x & 0x80000000u)) {
|
||||
x <<= 1;
|
||||
if (!(x & 0x80000000u))
|
||||
r -= 1;
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
@@ -169,4 +188,133 @@ static inline unsigned long __fls(unsigned long word)
|
||||
return num;
|
||||
}
|
||||
|
||||
#define for_each_set_bit(bit, addr, size) \
|
||||
for ((bit) = find_first_bit((addr), (size)); \
|
||||
(bit) < (size); \
|
||||
(bit) = find_next_bit((addr), (size), (bit) + 1))
|
||||
|
||||
/* same as for_each_set_bit() but use bit as value to start with */
|
||||
#define for_each_set_bit_from(bit, addr, size) \
|
||||
for ((bit) = find_next_bit((addr), (size), (bit)); \
|
||||
(bit) < (size); \
|
||||
(bit) = find_next_bit((addr), (size), (bit) + 1))
|
||||
|
||||
#define for_each_clear_bit(bit, addr, size) \
|
||||
for ((bit) = find_first_zero_bit((addr), (size)); \
|
||||
(bit) < (size); \
|
||||
(bit) = find_next_zero_bit((addr), (size), (bit) + 1))
|
||||
|
||||
/* same as for_each_clear_bit() but use bit as value to start with */
|
||||
#define for_each_clear_bit_from(bit, addr, size) \
|
||||
for ((bit) = find_next_zero_bit((addr), (size), (bit)); \
|
||||
(bit) < (size); \
|
||||
(bit) = find_next_zero_bit((addr), (size), (bit) + 1))
|
||||
|
||||
unsigned long find_first_bit(const unsigned long *addr,
|
||||
unsigned long size);
|
||||
|
||||
unsigned long find_first_zero_bit(const unsigned long *addr,
|
||||
unsigned long size);
|
||||
|
||||
unsigned long find_last_bit(const unsigned long *addr,
|
||||
unsigned long size);
|
||||
|
||||
unsigned long find_next_bit(const unsigned long *addr,
|
||||
unsigned long size, unsigned long offset);
|
||||
|
||||
unsigned long find_next_zero_bit(const unsigned long *addr,
|
||||
unsigned long size,
|
||||
unsigned long offset);
|
||||
|
||||
/**
|
||||
* __set_bit - Set a bit in memory
|
||||
* @nr: the bit to set
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* This function is non-atomic and may be reordered.
|
||||
*/
|
||||
static inline void __set_bit(int nr, volatile unsigned long *addr)
|
||||
{
|
||||
unsigned long mask = BIT_MASK(nr);
|
||||
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
|
||||
|
||||
*p |= mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* __clear_bit - Clear a bit in memory
|
||||
* @nr: the bit to clear
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* This function is non-atomic and may be reordered.
|
||||
*/
|
||||
static inline void __clear_bit(int nr, volatile unsigned long *addr)
|
||||
{
|
||||
unsigned long mask = BIT_MASK(nr);
|
||||
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
|
||||
|
||||
*p &= ~mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* __change_bit - Toggle a bit in memory
|
||||
* @nr: the bit to change
|
||||
* @addr: the address to start counting from
|
||||
*
|
||||
* This function is non-atomic and may be reordered.
|
||||
*/
|
||||
static inline void __change_bit(int nr, volatile unsigned long *addr)
|
||||
{
|
||||
unsigned long mask = BIT_MASK(nr);
|
||||
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
|
||||
|
||||
*p ^= mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* __test_and_set_bit - Set a bit and return its old value
|
||||
* @nr: Bit to set
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
*/
|
||||
static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
|
||||
{
|
||||
unsigned long mask = BIT_MASK(nr);
|
||||
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
|
||||
unsigned long old = *p;
|
||||
|
||||
*p = old | mask;
|
||||
return (old & mask) != 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* __test_and_clear_bit - Clear a bit and return its old value
|
||||
* @nr: Bit to clear
|
||||
* @addr: Address to count from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
*/
|
||||
static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
|
||||
{
|
||||
unsigned long mask = BIT_MASK(nr);
|
||||
unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
|
||||
unsigned long old = *p;
|
||||
|
||||
*p = old & ~mask;
|
||||
return (old & mask) != 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* __test_bit - Determine whether a bit is set
|
||||
* @nr: bit number to test
|
||||
* @addr: Address to start counting from
|
||||
*
|
||||
* This operation is non-atomic and can be reordered.
|
||||
*/
|
||||
static inline int __test_bit(int nr, const volatile unsigned long *addr)
|
||||
{
|
||||
return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
@@ -1,19 +0,0 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2019 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_BITS_H__
|
||||
#define __SBI_BITS_H__
|
||||
|
||||
#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
|
||||
#define INSERT_FIELD(val, which, fieldval) \
|
||||
(((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
|
||||
|
||||
#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
|
||||
#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
|
||||
#endif
|
@@ -30,10 +30,9 @@ int __printf(3, 4) sbi_snprintf(char *out, u32 out_sz, const char *format, ...);
|
||||
|
||||
int __printf(1, 2) sbi_printf(const char *format, ...);
|
||||
|
||||
struct sbi_scratch;
|
||||
int __printf(1, 2) sbi_dprintf(const char *format, ...);
|
||||
|
||||
int __printf(2, 3) sbi_dprintf(struct sbi_scratch *scratch,
|
||||
const char *format, ...);
|
||||
struct sbi_scratch;
|
||||
|
||||
int sbi_console_init(struct sbi_scratch *scratch);
|
||||
|
||||
|
@@ -10,7 +10,8 @@
|
||||
#ifndef __SBI_CONST_H__
|
||||
#define __SBI_CONST_H__
|
||||
|
||||
/* Some constant macros are used in both assembler and
|
||||
/*
|
||||
* Some constant macros are used in both assembler and
|
||||
* C code. Therefore we cannot annotate them always with
|
||||
* 'UL' and other type specifiers unilaterally. We
|
||||
* use the following macros to deal with this.
|
||||
@@ -39,8 +40,8 @@
|
||||
#define UL(x) (_UL(x))
|
||||
#define ULL(x) (_ULL(x))
|
||||
|
||||
#define __STR(s) #s
|
||||
#define STRINGIFY(s) __STR(s)
|
||||
#define __STR(s) #s
|
||||
#define STRINGIFY(s) __STR(s)
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
|
50
include/sbi/sbi_csr_detect.h
Normal file
50
include/sbi/sbi_csr_detect.h
Normal file
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_CSR_DETECT__H
|
||||
#define __SBI_CSR_DETECT__H
|
||||
|
||||
#include <sbi/riscv_encoding.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
|
||||
#define csr_read_allowed(csr_num, trap) \
|
||||
({ \
|
||||
register ulong tinfo asm("a3") = (ulong)trap; \
|
||||
register ulong ttmp asm("a4"); \
|
||||
register ulong mtvec = sbi_hart_expected_trap_addr(); \
|
||||
register ulong ret = 0; \
|
||||
asm volatile( \
|
||||
"add %[ttmp], %[tinfo], zero\n" \
|
||||
"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
|
||||
"csrr %[ret], %[csr]\n" \
|
||||
"csrw " STR(CSR_MTVEC) ", %[mtvec]" \
|
||||
: [mtvec] "+&r"(mtvec), [tinfo] "+&r"(tinfo), \
|
||||
[ttmp] "+&r"(ttmp), [ret] "=&r" (ret) \
|
||||
: [csr] "i" (csr_num) \
|
||||
: "memory"); \
|
||||
ret; \
|
||||
}) \
|
||||
|
||||
#define csr_write_allowed(csr_num, trap, value) \
|
||||
({ \
|
||||
register ulong tinfo asm("a3") = (ulong)trap; \
|
||||
register ulong ttmp asm("a4"); \
|
||||
register ulong mtvec = sbi_hart_expected_trap_addr(); \
|
||||
asm volatile( \
|
||||
"add %[ttmp], %[tinfo], zero\n" \
|
||||
"csrrw %[mtvec], " STR(CSR_MTVEC) ", %[mtvec]\n" \
|
||||
"csrw %[csr], %[val]\n" \
|
||||
"csrw " STR(CSR_MTVEC) ", %[mtvec]" \
|
||||
: [mtvec] "+&r"(mtvec), \
|
||||
[tinfo] "+&r"(tinfo), [ttmp] "+&r"(ttmp) \
|
||||
: [csr] "i" (csr_num), [val] "r" (value) \
|
||||
: "memory"); \
|
||||
}) \
|
||||
|
||||
#endif
|
165
include/sbi/sbi_domain.h
Normal file
165
include/sbi/sbi_domain.h
Normal file
@@ -0,0 +1,165 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_DOMAIN_H__
|
||||
#define __SBI_DOMAIN_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
#include <sbi/sbi_hartmask.h>
|
||||
|
||||
struct sbi_scratch;
|
||||
|
||||
/** Domain access types */
|
||||
enum sbi_domain_access {
|
||||
SBI_DOMAIN_READ = (1UL << 0),
|
||||
SBI_DOMAIN_WRITE = (1UL << 1),
|
||||
SBI_DOMAIN_EXECUTE = (1UL << 2),
|
||||
SBI_DOMAIN_MMIO = (1UL << 3)
|
||||
};
|
||||
|
||||
/** Representation of OpenSBI domain memory region */
|
||||
struct sbi_domain_memregion {
|
||||
/**
|
||||
* Size of memory region as power of 2
|
||||
* It has to be minimum 3 and maximum __riscv_xlen
|
||||
*/
|
||||
unsigned long order;
|
||||
/**
|
||||
* Base address of memory region
|
||||
* It must be 2^order aligned address
|
||||
*/
|
||||
unsigned long base;
|
||||
/** Flags representing memory region attributes */
|
||||
#define SBI_DOMAIN_MEMREGION_READABLE (1UL << 0)
|
||||
#define SBI_DOMAIN_MEMREGION_WRITEABLE (1UL << 1)
|
||||
#define SBI_DOMAIN_MEMREGION_EXECUTABLE (1UL << 2)
|
||||
#define SBI_DOMAIN_MEMREGION_MMODE (1UL << 3)
|
||||
#define SBI_DOMAIN_MEMREGION_ACCESS_MASK (0xfUL)
|
||||
|
||||
#define SBI_DOMAIN_MEMREGION_MMIO (1UL << 31)
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
/** Maximum number of domains */
|
||||
#define SBI_DOMAIN_MAX_INDEX 32
|
||||
|
||||
/** Representation of OpenSBI domain */
|
||||
struct sbi_domain {
|
||||
/**
|
||||
* Logical index of this domain
|
||||
* Note: This set by sbi_domain_finalize() in the coldboot path
|
||||
*/
|
||||
u32 index;
|
||||
/**
|
||||
* HARTs assigned to this domain
|
||||
* Note: This set by sbi_domain_init() and sbi_domain_finalize()
|
||||
* in the coldboot path
|
||||
*/
|
||||
struct sbi_hartmask assigned_harts;
|
||||
/** Name of this domain */
|
||||
char name[64];
|
||||
/** Possible HARTs in this domain */
|
||||
const struct sbi_hartmask *possible_harts;
|
||||
/** Array of memory regions terminated by a region with order zero */
|
||||
struct sbi_domain_memregion *regions;
|
||||
/** HART id of the HART booting this domain */
|
||||
u32 boot_hartid;
|
||||
/** Arg1 (or 'a1' register) of next booting stage for this domain */
|
||||
unsigned long next_arg1;
|
||||
/** Address of next booting stage for this domain */
|
||||
unsigned long next_addr;
|
||||
/** Privilege mode of next booting stage for this domain */
|
||||
unsigned long next_mode;
|
||||
/** Is domain allowed to reset the system */
|
||||
bool system_reset_allowed;
|
||||
};
|
||||
|
||||
/** HART id to domain table */
|
||||
extern struct sbi_domain *hartid_to_domain_table[];
|
||||
|
||||
/** Get pointer to sbi_domain from HART id */
|
||||
#define sbi_hartid_to_domain(__hartid) \
|
||||
hartid_to_domain_table[__hartid]
|
||||
|
||||
/** Get pointer to sbi_domain for current HART */
|
||||
#define sbi_domain_thishart_ptr() \
|
||||
sbi_hartid_to_domain(current_hartid())
|
||||
|
||||
/** Index to domain table */
|
||||
extern struct sbi_domain *domidx_to_domain_table[];
|
||||
|
||||
/** Get pointer to sbi_domain from index */
|
||||
#define sbi_index_to_domain(__index) \
|
||||
domidx_to_domain_table[__index]
|
||||
|
||||
/** Iterate over each domain */
|
||||
#define sbi_domain_for_each(__i, __d) \
|
||||
for ((__i) = 0; ((__d) = sbi_index_to_domain(__i)); (__i)++)
|
||||
|
||||
/** Iterate over each memory region of a domain */
|
||||
#define sbi_domain_for_each_memregion(__d, __r) \
|
||||
for ((__r) = (__d)->regions; (__r)->order; (__r)++)
|
||||
|
||||
/**
|
||||
* Check whether given HART is assigned to specified domain
|
||||
* @param dom pointer to domain
|
||||
* @param hartid the HART ID
|
||||
* @return TRUE if HART is assigned to domain otherwise FALSE
|
||||
*/
|
||||
bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid);
|
||||
|
||||
/**
|
||||
* Get ulong assigned HART mask for given domain and HART base ID
|
||||
* @param dom pointer to domain
|
||||
* @param hbase the HART base ID
|
||||
* @return ulong possible HART mask
|
||||
* Note: the return ulong mask will be set to zero on failure.
|
||||
*/
|
||||
ulong sbi_domain_get_assigned_hartmask(const struct sbi_domain *dom,
|
||||
ulong hbase);
|
||||
|
||||
/** Initialize a domain memory region as firmware region */
|
||||
void sbi_domain_memregion_initfw(struct sbi_domain_memregion *reg);
|
||||
|
||||
/**
|
||||
* Check whether we can access specified address for given mode and
|
||||
* memory region flags under a domain
|
||||
* @param dom pointer to domain
|
||||
* @param addr the address to be checked
|
||||
* @param mode the privilege mode of access
|
||||
* @param access_flags bitmask of domain access types (enum sbi_domain_access)
|
||||
* @return TRUE if access allowed otherwise FALSE
|
||||
*/
|
||||
bool sbi_domain_check_addr(const struct sbi_domain *dom,
|
||||
unsigned long addr, unsigned long mode,
|
||||
unsigned long access_flags);
|
||||
|
||||
/** Dump domain details on the console */
|
||||
void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix);
|
||||
|
||||
/** Dump all domain details on the console */
|
||||
void sbi_domain_dump_all(const char *suffix);
|
||||
|
||||
/**
|
||||
* Register a new domain
|
||||
* @param dom pointer to domain
|
||||
* @param assign_mask pointer to HART mask of HARTs assigned to the domain
|
||||
*
|
||||
* @return 0 on success and negative error code on failure
|
||||
*/
|
||||
int sbi_domain_register(struct sbi_domain *dom,
|
||||
const struct sbi_hartmask *assign_mask);
|
||||
|
||||
/** Finalize domain tables and startup non-root domains */
|
||||
int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid);
|
||||
|
||||
/** Initialize domains */
|
||||
int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid);
|
||||
|
||||
#endif
|
@@ -19,17 +19,15 @@
|
||||
|
||||
struct sbi_trap_regs;
|
||||
struct sbi_trap_info;
|
||||
struct sbi_scratch;
|
||||
|
||||
struct sbi_ecall_extension {
|
||||
struct sbi_dlist head;
|
||||
unsigned long extid_start;
|
||||
unsigned long extid_end;
|
||||
int (* probe)(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long *out_val);
|
||||
int (* handle)(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long funcid,
|
||||
unsigned long *args, unsigned long *out_val,
|
||||
int (* probe)(unsigned long extid, unsigned long *out_val);
|
||||
int (* handle)(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap);
|
||||
};
|
||||
|
||||
@@ -39,19 +37,24 @@ extern struct sbi_ecall_extension ecall_time;
|
||||
extern struct sbi_ecall_extension ecall_rfence;
|
||||
extern struct sbi_ecall_extension ecall_ipi;
|
||||
extern struct sbi_ecall_extension ecall_vendor;
|
||||
extern struct sbi_ecall_extension ecall_hsm;
|
||||
extern struct sbi_ecall_extension ecall_srst;
|
||||
|
||||
u16 sbi_ecall_version_major(void);
|
||||
|
||||
u16 sbi_ecall_version_minor(void);
|
||||
|
||||
unsigned long sbi_ecall_get_impid(void);
|
||||
|
||||
void sbi_ecall_set_impid(unsigned long impid);
|
||||
|
||||
struct sbi_ecall_extension *sbi_ecall_find_extension(unsigned long extid);
|
||||
|
||||
int sbi_ecall_register_extension(struct sbi_ecall_extension *ext);
|
||||
|
||||
void sbi_ecall_unregister_extension(struct sbi_ecall_extension *ext);
|
||||
|
||||
int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch);
|
||||
int sbi_ecall_handler(struct sbi_trap_regs *regs);
|
||||
|
||||
int sbi_ecall_init(void);
|
||||
|
||||
|
@@ -13,7 +13,7 @@
|
||||
/* clang-format off */
|
||||
|
||||
/* SBI Extension IDs */
|
||||
#define SBI_EXT_0_1_SET_TIMER 0x0
|
||||
#define SBI_EXT_0_1_SET_TIMER 0x0
|
||||
#define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
|
||||
#define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
|
||||
#define SBI_EXT_0_1_CLEAR_IPI 0x3
|
||||
@@ -26,15 +26,17 @@
|
||||
#define SBI_EXT_TIME 0x54494D45
|
||||
#define SBI_EXT_IPI 0x735049
|
||||
#define SBI_EXT_RFENCE 0x52464E43
|
||||
#define SBI_EXT_HSM 0x48534D
|
||||
#define SBI_EXT_SRST 0x53525354
|
||||
|
||||
/* SBI function IDs for BASE extension*/
|
||||
#define SBI_EXT_BASE_GET_SPEC_VERSION 0x0
|
||||
#define SBI_EXT_BASE_GET_IMP_ID 0x1
|
||||
#define SBI_EXT_BASE_GET_IMP_VERSION 0x2
|
||||
#define SBI_EXT_BASE_PROBE_EXT 0x3
|
||||
#define SBI_EXT_BASE_GET_MVENDORID 0x4
|
||||
#define SBI_EXT_BASE_GET_MARCHID 0x5
|
||||
#define SBI_EXT_BASE_GET_MIMPID 0x6
|
||||
#define SBI_EXT_BASE_GET_IMP_VERSION 0x2
|
||||
#define SBI_EXT_BASE_PROBE_EXT 0x3
|
||||
#define SBI_EXT_BASE_GET_MVENDORID 0x4
|
||||
#define SBI_EXT_BASE_GET_MARCHID 0x5
|
||||
#define SBI_EXT_BASE_GET_MIMPID 0x6
|
||||
|
||||
/* SBI function IDs for TIME extension*/
|
||||
#define SBI_EXT_TIME_SET_TIMER 0x0
|
||||
@@ -43,7 +45,7 @@
|
||||
#define SBI_EXT_IPI_SEND_IPI 0x0
|
||||
|
||||
/* SBI function IDs for RFENCE extension*/
|
||||
#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
|
||||
#define SBI_EXT_RFENCE_REMOTE_FENCE_I 0x0
|
||||
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA 0x1
|
||||
#define SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID 0x2
|
||||
#define SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA 0x3
|
||||
@@ -51,11 +53,46 @@
|
||||
#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA 0x5
|
||||
#define SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID 0x6
|
||||
|
||||
#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
|
||||
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
|
||||
#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
|
||||
#define SBI_EXT_VENDOR_START 0x09000000
|
||||
#define SBI_EXT_VENDOR_END 0x09FFFFFF
|
||||
/* SBI function IDs for HSM extension */
|
||||
#define SBI_EXT_HSM_HART_START 0x0
|
||||
#define SBI_EXT_HSM_HART_STOP 0x1
|
||||
#define SBI_EXT_HSM_HART_GET_STATUS 0x2
|
||||
|
||||
#define SBI_HSM_HART_STATUS_STARTED 0x0
|
||||
#define SBI_HSM_HART_STATUS_STOPPED 0x1
|
||||
#define SBI_HSM_HART_STATUS_START_PENDING 0x2
|
||||
#define SBI_HSM_HART_STATUS_STOP_PENDING 0x3
|
||||
|
||||
/* SBI function IDs for SRST extension */
|
||||
#define SBI_EXT_SRST_RESET 0x0
|
||||
|
||||
#define SBI_SRST_RESET_TYPE_SHUTDOWN 0x0
|
||||
#define SBI_SRST_RESET_TYPE_COLD_REBOOT 0x1
|
||||
#define SBI_SRST_RESET_TYPE_WARM_REBOOT 0x2
|
||||
#define SBI_SRST_RESET_TYPE_LAST SBI_SRST_RESET_TYPE_WARM_REBOOT
|
||||
|
||||
#define SBI_SRST_RESET_REASON_NONE 0x0
|
||||
#define SBI_SRST_RESET_REASON_SYSFAIL 0x1
|
||||
|
||||
#define SBI_SPEC_VERSION_MAJOR_OFFSET 24
|
||||
#define SBI_SPEC_VERSION_MAJOR_MASK 0x7f
|
||||
#define SBI_SPEC_VERSION_MINOR_MASK 0xffffff
|
||||
#define SBI_EXT_VENDOR_START 0x09000000
|
||||
#define SBI_EXT_VENDOR_END 0x09FFFFFF
|
||||
#define SBI_EXT_FIRMWARE_START 0x0A000000
|
||||
#define SBI_EXT_FIRMWARE_END 0x0AFFFFFF
|
||||
|
||||
/* SBI return error codes */
|
||||
#define SBI_SUCCESS 0
|
||||
#define SBI_ERR_FAILED -1
|
||||
#define SBI_ERR_NOT_SUPPORTED -2
|
||||
#define SBI_ERR_INVALID_PARAM -3
|
||||
#define SBI_ERR_DENIED -4
|
||||
#define SBI_ERR_INVALID_ADDRESS -5
|
||||
#define SBI_ERR_ALREADY_AVAILABLE -6
|
||||
|
||||
#define SBI_LAST_ERR SBI_ERR_ALREADY_AVAILABLE
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
#endif
|
||||
|
@@ -13,12 +13,11 @@
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct sbi_trap_regs;
|
||||
struct sbi_scratch;
|
||||
|
||||
int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch, ulong *csr_val);
|
||||
int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
|
||||
ulong *csr_val);
|
||||
|
||||
int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch, ulong csr_val);
|
||||
int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
|
||||
ulong csr_val);
|
||||
|
||||
#endif
|
||||
|
@@ -10,24 +10,28 @@
|
||||
#ifndef __SBI_ERROR_H__
|
||||
#define __SBI_ERROR_H__
|
||||
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
#define SBI_OK 0
|
||||
#define SBI_EFAIL -1
|
||||
#define SBI_ENOTSUPP -2
|
||||
#define SBI_EINVAL -3
|
||||
#define SBI_DENIED -4
|
||||
#define SBI_INVALID_ADDR -5
|
||||
#define SBI_ENODEV -6
|
||||
#define SBI_ENOSYS -7
|
||||
#define SBI_ETIMEDOUT -8
|
||||
#define SBI_EIO -9
|
||||
#define SBI_EILL -10
|
||||
#define SBI_ENOSPC -11
|
||||
#define SBI_ENOMEM -12
|
||||
#define SBI_ETRAP -13
|
||||
#define SBI_EUNKNOWN -14
|
||||
#define SBI_ENOENT -15
|
||||
#define SBI_OK 0
|
||||
#define SBI_EFAIL SBI_ERR_FAILED
|
||||
#define SBI_ENOTSUPP SBI_ERR_NOT_SUPPORTED
|
||||
#define SBI_EINVAL SBI_ERR_INVALID_PARAM
|
||||
#define SBI_EDENIED SBI_ERR_DENIED
|
||||
#define SBI_EINVALID_ADDR SBI_ERR_INVALID_ADDRESS
|
||||
#define SBI_EALREADY SBI_ERR_ALREADY_AVAILABLE
|
||||
|
||||
#define SBI_ENODEV -1000
|
||||
#define SBI_ENOSYS -1001
|
||||
#define SBI_ETIMEDOUT -1002
|
||||
#define SBI_EIO -1003
|
||||
#define SBI_EILL -1004
|
||||
#define SBI_ENOSPC -1005
|
||||
#define SBI_ENOMEM -1006
|
||||
#define SBI_ETRAP -1007
|
||||
#define SBI_EUNKNOWN -1008
|
||||
#define SBI_ENOENT -1009
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
|
@@ -12,16 +12,39 @@
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
/** Possible feature flags of a hart */
|
||||
enum sbi_hart_features {
|
||||
/** Hart has S-mode counter enable */
|
||||
SBI_HART_HAS_SCOUNTEREN = (1 << 0),
|
||||
/** Hart has M-mode counter enable */
|
||||
SBI_HART_HAS_MCOUNTEREN = (1 << 1),
|
||||
/** HART has timer csr implementation in hardware */
|
||||
SBI_HART_HAS_TIME = (1 << 2),
|
||||
|
||||
/** Last index of Hart features*/
|
||||
SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_TIME,
|
||||
};
|
||||
|
||||
struct sbi_scratch;
|
||||
|
||||
int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
|
||||
int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot);
|
||||
|
||||
void *sbi_hart_get_trap_info(struct sbi_scratch *scratch);
|
||||
extern void (*sbi_hart_expected_trap)(void);
|
||||
static inline ulong sbi_hart_expected_trap_addr(void)
|
||||
{
|
||||
return (ulong)sbi_hart_expected_trap;
|
||||
}
|
||||
|
||||
void sbi_hart_set_trap_info(struct sbi_scratch *scratch, void *data);
|
||||
|
||||
void sbi_hart_delegation_dump(struct sbi_scratch *scratch);
|
||||
void sbi_hart_pmp_dump(struct sbi_scratch *scratch);
|
||||
unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch);
|
||||
void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
|
||||
const char *prefix, const char *suffix);
|
||||
unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch);
|
||||
unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch);
|
||||
unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch);
|
||||
int sbi_hart_pmp_configure(struct sbi_scratch *scratch);
|
||||
bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature);
|
||||
void sbi_hart_get_features_str(struct sbi_scratch *scratch,
|
||||
char *features_str, int nfstr);
|
||||
|
||||
void __attribute__((noreturn)) sbi_hart_hang(void);
|
||||
|
||||
@@ -30,19 +53,4 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
|
||||
unsigned long next_addr, unsigned long next_mode,
|
||||
bool next_virt);
|
||||
|
||||
void sbi_hart_mark_available(u32 hartid);
|
||||
|
||||
ulong sbi_hart_available_mask(void);
|
||||
|
||||
void sbi_hart_unmark_available(u32 hartid);
|
||||
|
||||
struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
|
||||
u32 hartid);
|
||||
|
||||
void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid);
|
||||
|
||||
void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid);
|
||||
|
||||
u32 sbi_current_hartid(void);
|
||||
|
||||
#endif
|
||||
|
141
include/sbi/sbi_hartmask.h
Normal file
141
include/sbi/sbi_hartmask.h
Normal file
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_HARTMASK_H__
|
||||
#define __SBI_HARTMASK_H__
|
||||
|
||||
#include <sbi/sbi_bitmap.h>
|
||||
|
||||
/**
|
||||
* Maximum number of bits in a hartmask
|
||||
*
|
||||
* The hartmask is indexed using physical HART id so this define
|
||||
* also represents the maximum number of HART ids generic OpenSBI
|
||||
* can handle.
|
||||
*/
|
||||
#define SBI_HARTMASK_MAX_BITS 128
|
||||
|
||||
/** Representation of hartmask */
|
||||
struct sbi_hartmask {
|
||||
DECLARE_BITMAP(bits, SBI_HARTMASK_MAX_BITS);
|
||||
};
|
||||
|
||||
/** Initialize hartmask to zero */
|
||||
#define SBI_HARTMASK_INIT(__m) \
|
||||
bitmap_zero(((__m)->bits), SBI_HARTMASK_MAX_BITS)
|
||||
|
||||
/** Initialize hartmask to zero except a particular HART id */
|
||||
#define SBI_HARTMASK_INIT_EXCEPT(__m, __h) \
|
||||
bitmap_zero_except(((__m)->bits), (__h), SBI_HARTMASK_MAX_BITS)
|
||||
|
||||
/**
|
||||
* Get underlying bitmap of hartmask
|
||||
* @param m the hartmask pointer
|
||||
*/
|
||||
#define sbi_hartmask_bits(__m) ((__m)->bits)
|
||||
|
||||
/**
|
||||
* Set a HART in hartmask
|
||||
* @param h HART id to set
|
||||
* @param m the hartmask pointer
|
||||
*/
|
||||
static inline void sbi_hartmask_set_hart(u32 h, struct sbi_hartmask *m)
|
||||
{
|
||||
if (h < SBI_HARTMASK_MAX_BITS)
|
||||
__set_bit(h, m->bits);
|
||||
}
|
||||
|
||||
/**
|
||||
* Clear a HART in hartmask
|
||||
* @param h HART id to clear
|
||||
* @param m the hartmask pointer
|
||||
*/
|
||||
static inline void sbi_hartmask_clear_hart(u32 h, struct sbi_hartmask *m)
|
||||
{
|
||||
if (h < SBI_HARTMASK_MAX_BITS)
|
||||
__clear_bit(h, m->bits);
|
||||
}
|
||||
|
||||
/**
|
||||
* Test a HART in hartmask
|
||||
* @param h HART id to test
|
||||
* @param m the hartmask pointer
|
||||
*/
|
||||
static inline int sbi_hartmask_test_hart(u32 h, const struct sbi_hartmask *m)
|
||||
{
|
||||
if (h < SBI_HARTMASK_MAX_BITS)
|
||||
return __test_bit(h, m->bits);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set all HARTs in a hartmask
|
||||
* @param dstp the hartmask pointer
|
||||
*/
|
||||
static inline void sbi_hartmask_set_all(struct sbi_hartmask *dstp)
|
||||
{
|
||||
bitmap_fill(sbi_hartmask_bits(dstp), SBI_HARTMASK_MAX_BITS);
|
||||
}
|
||||
|
||||
/**
|
||||
* Clear all HARTs in a hartmask
|
||||
* @param dstp the hartmask pointer
|
||||
*/
|
||||
static inline void sbi_hartmask_clear_all(struct sbi_hartmask *dstp)
|
||||
{
|
||||
bitmap_zero(sbi_hartmask_bits(dstp), SBI_HARTMASK_MAX_BITS);
|
||||
}
|
||||
|
||||
/**
|
||||
* *dstp = *src1p & *src2p
|
||||
* @param dstp the hartmask result
|
||||
* @param src1p the first input
|
||||
* @param src2p the second input
|
||||
*/
|
||||
static inline void sbi_hartmask_and(struct sbi_hartmask *dstp,
|
||||
const struct sbi_hartmask *src1p,
|
||||
const struct sbi_hartmask *src2p)
|
||||
{
|
||||
bitmap_and(sbi_hartmask_bits(dstp), sbi_hartmask_bits(src1p),
|
||||
sbi_hartmask_bits(src2p), SBI_HARTMASK_MAX_BITS);
|
||||
}
|
||||
|
||||
/**
|
||||
* *dstp = *src1p | *src2p
|
||||
* @param dstp the hartmask result
|
||||
* @param src1p the first input
|
||||
* @param src2p the second input
|
||||
*/
|
||||
static inline void sbi_hartmask_or(struct sbi_hartmask *dstp,
|
||||
const struct sbi_hartmask *src1p,
|
||||
const struct sbi_hartmask *src2p)
|
||||
{
|
||||
bitmap_or(sbi_hartmask_bits(dstp), sbi_hartmask_bits(src1p),
|
||||
sbi_hartmask_bits(src2p), SBI_HARTMASK_MAX_BITS);
|
||||
}
|
||||
|
||||
/**
|
||||
* *dstp = *src1p ^ *src2p
|
||||
* @param dstp the hartmask result
|
||||
* @param src1p the first input
|
||||
* @param src2p the second input
|
||||
*/
|
||||
static inline void sbi_hartmask_xor(struct sbi_hartmask *dstp,
|
||||
const struct sbi_hartmask *src1p,
|
||||
const struct sbi_hartmask *src2p)
|
||||
{
|
||||
bitmap_xor(sbi_hartmask_bits(dstp), sbi_hartmask_bits(src1p),
|
||||
sbi_hartmask_bits(src2p), SBI_HARTMASK_MAX_BITS);
|
||||
}
|
||||
|
||||
/** Iterate over each HART in hartmask */
|
||||
#define sbi_hartmask_for_each_hart(__h, __m) \
|
||||
for_each_set_bit(__h, (__m)->bits, SBI_HARTMASK_MAX_BITS)
|
||||
|
||||
#endif
|
@@ -10,8 +10,9 @@
|
||||
|
||||
#ifndef __SBI_FENCE_H__
|
||||
#define __SBI_FENCE_H__
|
||||
|
||||
/** Invalidate Stage2 TLBs for given VMID and guest physical address */
|
||||
void __sbi_hfence_gvma_vmid_gpa(unsigned long vmid, unsigned long gpa);
|
||||
void __sbi_hfence_gvma_vmid_gpa(unsigned long gpa, unsigned long vmid);
|
||||
|
||||
/** Invalidate Stage2 TLBs for given VMID */
|
||||
void __sbi_hfence_gvma_vmid(unsigned long vmid);
|
||||
@@ -23,7 +24,7 @@ void __sbi_hfence_gvma_gpa(unsigned long gpa);
|
||||
void __sbi_hfence_gvma_all(void);
|
||||
|
||||
/** Invalidate unified TLB entries for given asid and guest virtual address */
|
||||
void __sbi_hfence_vvma_asid_va(unsigned long asid, unsigned long va);
|
||||
void __sbi_hfence_vvma_asid_va(unsigned long va, unsigned long asid);
|
||||
|
||||
/** Invalidate unified TLB entries for given ASID for a guest*/
|
||||
void __sbi_hfence_vvma_asid(unsigned long asid);
|
||||
@@ -33,4 +34,5 @@ void __sbi_hfence_vvma_va(unsigned long va);
|
||||
|
||||
/** Invalidate all possible Stage2 TLBs */
|
||||
void __sbi_hfence_vvma_all(void);
|
||||
|
||||
#endif
|
||||
|
38
include/sbi/sbi_hsm.h
Normal file
38
include/sbi/sbi_hsm.h
Normal file
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_HSM_H__
|
||||
#define __SBI_HSM_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
/** Hart state values **/
|
||||
#define SBI_HART_STOPPED 0
|
||||
#define SBI_HART_STOPPING 1
|
||||
#define SBI_HART_STARTING 2
|
||||
#define SBI_HART_STARTED 3
|
||||
#define SBI_HART_UNKNOWN 4
|
||||
|
||||
struct sbi_domain;
|
||||
struct sbi_scratch;
|
||||
|
||||
int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
|
||||
void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch);
|
||||
|
||||
int sbi_hsm_hart_start(struct sbi_scratch *scratch,
|
||||
const struct sbi_domain *dom,
|
||||
u32 hartid, ulong saddr, ulong smode, ulong priv);
|
||||
int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow);
|
||||
int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid);
|
||||
int sbi_hsm_hart_state_to_status(int state);
|
||||
int sbi_hsm_hart_started_mask(const struct sbi_domain *dom,
|
||||
ulong hbase, ulong *out_hmask);
|
||||
void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid);
|
||||
|
||||
#endif
|
@@ -13,10 +13,7 @@
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct sbi_trap_regs;
|
||||
struct sbi_scratch;
|
||||
|
||||
int sbi_illegal_insn_handler(u32 hartid, ulong mcause, ulong insn,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch);
|
||||
int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs);
|
||||
|
||||
#endif
|
||||
|
@@ -25,41 +25,43 @@ struct sbi_ipi_event_ops {
|
||||
/** Name of the IPI event operations */
|
||||
char name[32];
|
||||
|
||||
/** Update callback to save/enqueue data for remote HART
|
||||
* Note: This is an optional callback and it is called just before
|
||||
* triggering IPI to remote HART.
|
||||
/**
|
||||
* Update callback to save/enqueue data for remote HART
|
||||
* Note: This is an optional callback and it is called just before
|
||||
* triggering IPI to remote HART.
|
||||
*/
|
||||
int (* update)(struct sbi_scratch *scratch,
|
||||
struct sbi_scratch *remote_scratch,
|
||||
u32 remote_hartid, void *data);
|
||||
|
||||
/** Sync callback to wait for remote HART
|
||||
* Note: This is an optional callback and it is called just after
|
||||
* triggering IPI to remote HART.
|
||||
/**
|
||||
* Sync callback to wait for remote HART
|
||||
* Note: This is an optional callback and it is called just after
|
||||
* triggering IPI to remote HART.
|
||||
*/
|
||||
void (* sync)(struct sbi_scratch *scratch);
|
||||
|
||||
/** Process callback to handle IPI event
|
||||
* Note: This is a mandatory callback and it is called on the
|
||||
* remote HART after IPI is triggered.
|
||||
/**
|
||||
* Process callback to handle IPI event
|
||||
* Note: This is a mandatory callback and it is called on the
|
||||
* remote HART after IPI is triggered.
|
||||
*/
|
||||
void (* process)(struct sbi_scratch *scratch);
|
||||
};
|
||||
|
||||
int sbi_ipi_send_many(struct sbi_scratch *scratch, ulong hmask,
|
||||
ulong hbase, u32 event, void *data);
|
||||
int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data);
|
||||
|
||||
int sbi_ipi_event_create(const struct sbi_ipi_event_ops *ops);
|
||||
|
||||
void sbi_ipi_event_destroy(u32 event);
|
||||
|
||||
int sbi_ipi_send_smode(struct sbi_scratch *scratch, ulong hmask, ulong hbase);
|
||||
int sbi_ipi_send_smode(ulong hmask, ulong hbase);
|
||||
|
||||
void sbi_ipi_clear_smode(struct sbi_scratch *scratch);
|
||||
void sbi_ipi_clear_smode(void);
|
||||
|
||||
int sbi_ipi_send_halt(struct sbi_scratch *scratch, ulong hmask, ulong hbase);
|
||||
int sbi_ipi_send_halt(ulong hmask, ulong hbase);
|
||||
|
||||
void sbi_ipi_process(struct sbi_scratch *scratch);
|
||||
void sbi_ipi_process(void);
|
||||
|
||||
int sbi_ipi_init(struct sbi_scratch *scratch, bool cold_boot);
|
||||
|
||||
|
15
include/sbi/sbi_math.h
Normal file
15
include/sbi/sbi_math.h
Normal file
@@ -0,0 +1,15 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SBI_MATH_H__
|
||||
#define __SBI_MATH_H__
|
||||
|
||||
unsigned long log2roundup(unsigned long x);
|
||||
|
||||
#endif
|
@@ -13,16 +13,11 @@
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct sbi_trap_regs;
|
||||
struct sbi_scratch;
|
||||
|
||||
int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
|
||||
ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch);
|
||||
int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs);
|
||||
|
||||
int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
|
||||
ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch);
|
||||
int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs);
|
||||
|
||||
#endif
|
||||
|
@@ -10,9 +10,10 @@
|
||||
#ifndef __SBI_PLATFORM_H__
|
||||
#define __SBI_PLATFORM_H__
|
||||
|
||||
/** OpenSBI 32-bit platform version with:
|
||||
* 1. upper 16-bits as major number
|
||||
* 2. lower 16-bits as minor number
|
||||
/**
|
||||
* OpenSBI 32-bit platform version with:
|
||||
* 1. upper 16-bits as major number
|
||||
* 2. lower 16-bits as minor number
|
||||
*/
|
||||
#define SBI_PLATFORM_VERSION(Major, Minor) ((Major << 16) | Minor)
|
||||
|
||||
@@ -28,44 +29,44 @@
|
||||
#define SBI_PLATFORM_HART_COUNT_OFFSET (0x50)
|
||||
/** Offset of hart_stack_size in struct sbi_platform */
|
||||
#define SBI_PLATFORM_HART_STACK_SIZE_OFFSET (0x54)
|
||||
/** Offset of disabled_hart_mask in struct sbi_platform */
|
||||
#define SBI_PLATFORM_DISABLED_HART_OFFSET (0x58)
|
||||
/** Offset of platform_ops_addr in struct sbi_platform */
|
||||
#define SBI_PLATFORM_OPS_OFFSET (0x60)
|
||||
#define SBI_PLATFORM_OPS_OFFSET (0x58)
|
||||
/** Offset of firmware_context in struct sbi_platform */
|
||||
#define SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET (0x60 + __SIZEOF_POINTER__)
|
||||
#define SBI_PLATFORM_FIRMWARE_CONTEXT_OFFSET (0x58 + __SIZEOF_POINTER__)
|
||||
/** Offset of hart_index2id in struct sbi_platform */
|
||||
#define SBI_PLATFORM_HART_INDEX2ID_OFFSET (0x58 + (__SIZEOF_POINTER__ * 2))
|
||||
|
||||
#define SBI_PLATFORM_TLB_RANGE_FLUSH_LIMIT_DEFAULT (1UL << 12)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <sbi/sbi_ecall.h>
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_scratch.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
#include <sbi/sbi_version.h>
|
||||
|
||||
struct sbi_domain_memregion;
|
||||
struct sbi_trap_info;
|
||||
struct sbi_trap_regs;
|
||||
|
||||
/** Possible feature flags of a platform */
|
||||
enum sbi_platform_features {
|
||||
/** Platform has timer value */
|
||||
SBI_PLATFORM_HAS_TIMER_VALUE = (1 << 0),
|
||||
/** Platform has HART hotplug support */
|
||||
SBI_PLATFORM_HAS_HART_HOTPLUG = (1 << 1),
|
||||
/** Platform has PMP support */
|
||||
SBI_PLATFORM_HAS_PMP = (1 << 2),
|
||||
/** Platform has S-mode counter enable */
|
||||
SBI_PLATFORM_HAS_SCOUNTEREN = (1 << 3),
|
||||
/** Platform has M-mode counter enable */
|
||||
SBI_PLATFORM_HAS_MCOUNTEREN = (1 << 4),
|
||||
/** Platform has fault delegation support */
|
||||
SBI_PLATFORM_HAS_MFAULTS_DELEGATION = (1 << 5),
|
||||
SBI_PLATFORM_HAS_MFAULTS_DELEGATION = (1 << 2),
|
||||
/** Platform has custom secondary hart booting support */
|
||||
SBI_PLATFORM_HAS_HART_SECONDARY_BOOT = (1 << 3),
|
||||
|
||||
/** Last index of Platform features*/
|
||||
SBI_PLATFORM_HAS_LAST_FEATURE = SBI_PLATFORM_HAS_HART_SECONDARY_BOOT,
|
||||
};
|
||||
|
||||
/** Default feature set for a platform */
|
||||
#define SBI_PLATFORM_DEFAULT_FEATURES \
|
||||
(SBI_PLATFORM_HAS_TIMER_VALUE | SBI_PLATFORM_HAS_PMP | \
|
||||
SBI_PLATFORM_HAS_SCOUNTEREN | SBI_PLATFORM_HAS_MCOUNTEREN | \
|
||||
SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
|
||||
(SBI_PLATFORM_HAS_TIMER_VALUE | SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
|
||||
|
||||
/** Platform functions */
|
||||
struct sbi_platform_operations {
|
||||
@@ -79,24 +80,22 @@ struct sbi_platform_operations {
|
||||
/** Platform final exit */
|
||||
void (*final_exit)(void);
|
||||
|
||||
/** For platforms that do not implement misa, non-standard
|
||||
/**
|
||||
* For platforms that do not implement misa, non-standard
|
||||
* methods are needed to determine cpu extension.
|
||||
*/
|
||||
int (*misa_check_extension)(char ext);
|
||||
|
||||
/** For platforms that do not implement misa, non-standard
|
||||
/**
|
||||
* For platforms that do not implement misa, non-standard
|
||||
* methods are needed to get MXL field of misa.
|
||||
*/
|
||||
int (*misa_get_xlen)(void);
|
||||
|
||||
/** Get number of PMP regions for given HART */
|
||||
u32 (*pmp_region_count)(u32 hartid);
|
||||
/**
|
||||
* Get PMP regions details (namely: protection, base address,
|
||||
* and size) for given HART
|
||||
*/
|
||||
int (*pmp_region_info)(u32 hartid, u32 index, ulong *prot, ulong *addr,
|
||||
ulong *log2size);
|
||||
/** Get platform specific root domain memory regions */
|
||||
struct sbi_domain_memregion *(*domains_root_regions)(void);
|
||||
/** Initialize (or populate) domains for the platform */
|
||||
int (*domains_init)(void);
|
||||
|
||||
/** Write a character to the platform console output */
|
||||
void (*console_putc)(char ch);
|
||||
@@ -133,19 +132,30 @@ struct sbi_platform_operations {
|
||||
/** Exit platform timer for current HART */
|
||||
void (*timer_exit)(void);
|
||||
|
||||
/** Reboot the platform */
|
||||
int (*system_reboot)(u32 type);
|
||||
/** Shutdown or poweroff the platform */
|
||||
int (*system_shutdown)(u32 type);
|
||||
/** Bringup the given hart */
|
||||
int (*hart_start)(u32 hartid, ulong saddr);
|
||||
/**
|
||||
* Stop the current hart from running. This call doesn't expect to
|
||||
* return if success.
|
||||
*/
|
||||
int (*hart_stop)(void);
|
||||
|
||||
/* Check whether reset type and reason supported by the platform */
|
||||
int (*system_reset_check)(u32 reset_type, u32 reset_reason);
|
||||
/** Reset the platform */
|
||||
void (*system_reset)(u32 reset_type, u32 reset_reason);
|
||||
|
||||
/** platform specific SBI extension implementation probe function */
|
||||
int (*vendor_ext_check)(long extid);
|
||||
/** platform specific SBI extension implementation provider */
|
||||
int (*vendor_ext_provider)(long extid, long funcid,
|
||||
unsigned long *args,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_value,
|
||||
struct sbi_trap_info *out_trap);
|
||||
} __packed;
|
||||
};
|
||||
|
||||
/** Platform default per-HART stack size for exception/interrupt handling */
|
||||
#define SBI_PLATFORM_DEFAULT_HART_STACK_SIZE 8192
|
||||
|
||||
/** Representation of a platform */
|
||||
struct sbi_platform {
|
||||
@@ -169,13 +179,27 @@ struct sbi_platform {
|
||||
u32 hart_count;
|
||||
/** Per-HART stack size for exception/interrupt handling */
|
||||
u32 hart_stack_size;
|
||||
/** Mask representing the set of disabled HARTs */
|
||||
u64 disabled_hart_mask;
|
||||
/** Pointer to sbi platform operations */
|
||||
unsigned long platform_ops_addr;
|
||||
/** Pointer to system firmware specific context */
|
||||
unsigned long firmware_context;
|
||||
} __packed;
|
||||
/**
|
||||
* HART index to HART id table
|
||||
*
|
||||
* For used HART index <abc>:
|
||||
* hart_index2id[<abc>] = some HART id
|
||||
* For unused HART index <abc>:
|
||||
* hart_index2id[<abc>] = -1U
|
||||
*
|
||||
* If hart_index2id == NULL then we assume identity mapping
|
||||
* hart_index2id[<abc>] = <abc>
|
||||
*
|
||||
* We have only two restrictions:
|
||||
* 1. HART index < sbi_platform hart_count
|
||||
* 2. HART id < SBI_HARTMASK_MAX_BITS
|
||||
*/
|
||||
const u32 *hart_index2id;
|
||||
};
|
||||
|
||||
/** Get pointer to sbi_platform for sbi_scratch pointer */
|
||||
#define sbi_platform_ptr(__s) \
|
||||
@@ -193,17 +217,34 @@ struct sbi_platform {
|
||||
/** Check whether the platform supports HART hotplug */
|
||||
#define sbi_platform_has_hart_hotplug(__p) \
|
||||
((__p)->features & SBI_PLATFORM_HAS_HART_HOTPLUG)
|
||||
/** Check whether the platform has PMP support */
|
||||
#define sbi_platform_has_pmp(__p) ((__p)->features & SBI_PLATFORM_HAS_PMP)
|
||||
/** Check whether the platform supports scounteren CSR */
|
||||
#define sbi_platform_has_scounteren(__p) \
|
||||
((__p)->features & SBI_PLATFORM_HAS_SCOUNTEREN)
|
||||
/** Check whether the platform supports mcounteren CSR */
|
||||
#define sbi_platform_has_mcounteren(__p) \
|
||||
((__p)->features & SBI_PLATFORM_HAS_MCOUNTEREN)
|
||||
/** Check whether the platform supports fault delegation */
|
||||
#define sbi_platform_has_mfaults_delegation(__p) \
|
||||
((__p)->features & SBI_PLATFORM_HAS_MFAULTS_DELEGATION)
|
||||
/** Check whether the platform supports custom secondary hart booting support */
|
||||
#define sbi_platform_has_hart_secondary_boot(__p) \
|
||||
((__p)->features & SBI_PLATFORM_HAS_HART_SECONDARY_BOOT)
|
||||
|
||||
/**
|
||||
* Get HART index for the given HART
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param hartid HART ID
|
||||
*
|
||||
* @return 0 <= value < hart_count for valid HART otherwise -1U
|
||||
*/
|
||||
u32 sbi_platform_hart_index(const struct sbi_platform *plat, u32 hartid);
|
||||
|
||||
/**
|
||||
* Get the platform features in string format
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param features_str pointer to a char array where the features string will be
|
||||
* updated
|
||||
* @param nfstr length of the features_str. The feature string will be truncated
|
||||
* if nfstr is not long enough.
|
||||
*/
|
||||
void sbi_platform_get_features_str(const struct sbi_platform *plat,
|
||||
char *features_str, int nfstr);
|
||||
|
||||
/**
|
||||
* Get name of the platform
|
||||
@@ -220,19 +261,18 @@ static inline const char *sbi_platform_name(const struct sbi_platform *plat)
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether the given HART is disabled
|
||||
* Get the platform features
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param hartid HART ID
|
||||
*
|
||||
* @return TRUE if HART is disabled and FALSE otherwise
|
||||
* @return the features value currently set for the given platform
|
||||
*/
|
||||
static inline bool sbi_platform_hart_disabled(const struct sbi_platform *plat,
|
||||
u32 hartid)
|
||||
static inline unsigned long sbi_platform_get_features(
|
||||
const struct sbi_platform *plat)
|
||||
{
|
||||
if (plat && (plat->disabled_hart_mask & (1 << hartid)))
|
||||
return TRUE;
|
||||
return FALSE;
|
||||
if (plat)
|
||||
return plat->features;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -279,6 +319,57 @@ static inline u32 sbi_platform_hart_stack_size(const struct sbi_platform *plat)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Check whether given HART is invalid
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param hartid HART ID
|
||||
*
|
||||
* @return TRUE if HART is invalid and FALSE otherwise
|
||||
*/
|
||||
static inline bool sbi_platform_hart_invalid(const struct sbi_platform *plat,
|
||||
u32 hartid)
|
||||
{
|
||||
if (!plat)
|
||||
return TRUE;
|
||||
if (plat->hart_count <= sbi_platform_hart_index(plat, hartid))
|
||||
return TRUE;
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
* Bringup a given hart from previous stage. Platform should implement this
|
||||
* operation if they support a custom mechanism to start a hart. Otherwise,
|
||||
* a generic WFI based approach will be used to start/stop a hart in OpenSBI.
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param hartid HART id
|
||||
* @param saddr M-mode start physical address for the HART
|
||||
*
|
||||
* @return 0 if sucessful and negative error code on failure
|
||||
*/
|
||||
static inline int sbi_platform_hart_start(const struct sbi_platform *plat,
|
||||
u32 hartid, ulong saddr)
|
||||
{
|
||||
if (plat && sbi_platform_ops(plat)->hart_start)
|
||||
return sbi_platform_ops(plat)->hart_start(hartid, saddr);
|
||||
return SBI_ENOTSUPP;
|
||||
}
|
||||
|
||||
/**
|
||||
* Stop the current hart in OpenSBI.
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
*
|
||||
* @return Negative error code on failure. It doesn't return on success.
|
||||
*/
|
||||
static inline int sbi_platform_hart_stop(const struct sbi_platform *plat)
|
||||
{
|
||||
if (plat && sbi_platform_ops(plat)->hart_stop)
|
||||
return sbi_platform_ops(plat)->hart_stop();
|
||||
return SBI_ENOTSUPP;
|
||||
}
|
||||
|
||||
/**
|
||||
* Early initialization for current HART
|
||||
*
|
||||
@@ -364,42 +455,32 @@ static inline int sbi_platform_misa_xlen(const struct sbi_platform *plat)
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the number of PMP regions of a HART
|
||||
* Get platform specific root domain memory regions
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param hartid HART ID
|
||||
*
|
||||
* @return number of PMP regions
|
||||
* @return an array of memory regions terminated by a region with order zero
|
||||
* or NULL for no memory regions
|
||||
*/
|
||||
static inline u32 sbi_platform_pmp_region_count(const struct sbi_platform *plat,
|
||||
u32 hartid)
|
||||
static inline struct sbi_domain_memregion *
|
||||
sbi_platform_domains_root_regions(const struct sbi_platform *plat)
|
||||
{
|
||||
if (plat && sbi_platform_ops(plat)->pmp_region_count)
|
||||
return sbi_platform_ops(plat)->pmp_region_count(hartid);
|
||||
return 0;
|
||||
if (plat && sbi_platform_ops(plat)->domains_root_regions)
|
||||
return sbi_platform_ops(plat)->domains_root_regions();
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get PMP regions details (namely: protection, base address,
|
||||
* and size) of a HART
|
||||
* Initialize (or populate) domains for the platform
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param hartid HART ID
|
||||
* @param index index of PMP region for which we want details
|
||||
* @param prot output pointer for PMP region protection
|
||||
* @param addr output pointer for PMP region base address
|
||||
* @param log2size output pointer for log-of-2 PMP region size
|
||||
*
|
||||
* @return 0 on success and negative error code on failure
|
||||
*/
|
||||
static inline int sbi_platform_pmp_region_info(const struct sbi_platform *plat,
|
||||
u32 hartid, u32 index,
|
||||
ulong *prot, ulong *addr,
|
||||
ulong *log2size)
|
||||
static inline int sbi_platform_domains_init(const struct sbi_platform *plat)
|
||||
{
|
||||
if (plat && sbi_platform_ops(plat)->pmp_region_info)
|
||||
return sbi_platform_ops(plat)->pmp_region_info(hartid, index, prot, addr,
|
||||
log2size);
|
||||
if (plat && sbi_platform_ops(plat)->domains_init)
|
||||
return sbi_platform_ops(plat)->domains_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -591,35 +672,38 @@ static inline void sbi_platform_timer_exit(const struct sbi_platform *plat)
|
||||
}
|
||||
|
||||
/**
|
||||
* Reboot the platform
|
||||
* Check whether reset type and reason supported by the platform
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param type type of reboot
|
||||
* @param reset_type type of reset
|
||||
* @param reset_reason reason for reset
|
||||
*
|
||||
* @return 0 on success and negative error code on failure
|
||||
* @return 0 if reset type and reason not supported and 1 if supported
|
||||
*/
|
||||
static inline int sbi_platform_system_reboot(const struct sbi_platform *plat,
|
||||
u32 type)
|
||||
static inline int sbi_platform_system_reset_check(
|
||||
const struct sbi_platform *plat,
|
||||
u32 reset_type, u32 reset_reason)
|
||||
{
|
||||
if (plat && sbi_platform_ops(plat)->system_reboot)
|
||||
return sbi_platform_ops(plat)->system_reboot(type);
|
||||
if (plat && sbi_platform_ops(plat)->system_reset_check)
|
||||
return sbi_platform_ops(plat)->system_reset_check(reset_type,
|
||||
reset_reason);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Shutdown or poweroff the platform
|
||||
* Reset the platform
|
||||
*
|
||||
* This function will not return for supported reset type and reset reason
|
||||
*
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param type type of shutdown or poweroff
|
||||
*
|
||||
* @return 0 on success and negative error code on failure
|
||||
* @param reset_type type of reset
|
||||
* @param reset_reason reason for reset
|
||||
*/
|
||||
static inline int sbi_platform_system_shutdown(const struct sbi_platform *plat,
|
||||
u32 type)
|
||||
static inline void sbi_platform_system_reset(const struct sbi_platform *plat,
|
||||
u32 reset_type, u32 reset_reason)
|
||||
{
|
||||
if (plat && sbi_platform_ops(plat)->system_shutdown)
|
||||
return sbi_platform_ops(plat)->system_shutdown(type);
|
||||
return 0;
|
||||
if (plat && sbi_platform_ops(plat)->system_reset)
|
||||
sbi_platform_ops(plat)->system_reset(reset_type, reset_reason);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -645,7 +729,7 @@ static inline int sbi_platform_vendor_ext_check(const struct sbi_platform *plat,
|
||||
* @param plat pointer to struct sbi_platform
|
||||
* @param extid vendor SBI extension id
|
||||
* @param funcid SBI function id within the extension id
|
||||
* @param args pointer to arguments passed by the caller
|
||||
* @param regs pointer to trap registers passed by the caller
|
||||
* @param out_value output value that can be filled by the callee
|
||||
* @param out_trap trap info that can be filled by the callee
|
||||
*
|
||||
@@ -654,13 +738,13 @@ static inline int sbi_platform_vendor_ext_check(const struct sbi_platform *plat,
|
||||
static inline int sbi_platform_vendor_ext_provider(
|
||||
const struct sbi_platform *plat,
|
||||
long extid, long funcid,
|
||||
unsigned long *args,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_value,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
if (plat && sbi_platform_ops(plat)->vendor_ext_provider) {
|
||||
return sbi_platform_ops(plat)->vendor_ext_provider(extid,
|
||||
funcid, args,
|
||||
funcid, regs,
|
||||
out_value,
|
||||
out_trap);
|
||||
}
|
||||
|
@@ -30,14 +30,16 @@
|
||||
#define SBI_SCRATCH_PLATFORM_ADDR_OFFSET (6 * __SIZEOF_POINTER__)
|
||||
/** Offset of hartid_to_scratch member in sbi_scratch */
|
||||
#define SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET (7 * __SIZEOF_POINTER__)
|
||||
/** Offset of trap_exit member in sbi_scratch */
|
||||
#define SBI_SCRATCH_TRAP_EXIT_OFFSET (8 * __SIZEOF_POINTER__)
|
||||
/** Offset of tmp0 member in sbi_scratch */
|
||||
#define SBI_SCRATCH_TMP0_OFFSET (8 * __SIZEOF_POINTER__)
|
||||
#define SBI_SCRATCH_TMP0_OFFSET (9 * __SIZEOF_POINTER__)
|
||||
/** Offset of options member in sbi_scratch */
|
||||
#define SBI_SCRATCH_OPTIONS_OFFSET (9 * __SIZEOF_POINTER__)
|
||||
#define SBI_SCRATCH_OPTIONS_OFFSET (10 * __SIZEOF_POINTER__)
|
||||
/** Offset of extra space in sbi_scratch */
|
||||
#define SBI_SCRATCH_EXTRA_SPACE_OFFSET (10 * __SIZEOF_POINTER__)
|
||||
/** Maximum size of sbi_scratch */
|
||||
#define SBI_SCRATCH_SIZE (64 * __SIZEOF_POINTER__)
|
||||
#define SBI_SCRATCH_EXTRA_SPACE_OFFSET (11 * __SIZEOF_POINTER__)
|
||||
/** Maximum size of sbi_scratch (4KB) */
|
||||
#define SBI_SCRATCH_SIZE (0x1000)
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
@@ -63,11 +65,13 @@ struct sbi_scratch {
|
||||
unsigned long platform_addr;
|
||||
/** Address of HART ID to sbi_scratch conversion function */
|
||||
unsigned long hartid_to_scratch;
|
||||
/** Address of trap exit function */
|
||||
unsigned long trap_exit;
|
||||
/** Temporary storage */
|
||||
unsigned long tmp0;
|
||||
/** Options for OpenSBI library */
|
||||
unsigned long options;
|
||||
} __packed;
|
||||
};
|
||||
|
||||
/** Possible options for OpenSBI library */
|
||||
enum sbi_scratch_options {
|
||||
@@ -85,7 +89,11 @@ enum sbi_scratch_options {
|
||||
#define sbi_scratch_thishart_arg1_ptr() \
|
||||
((void *)(sbi_scratch_thishart_ptr()->next_arg1))
|
||||
|
||||
/** Allocate from extra space in sbi_scratch
|
||||
/** Initialize scratch table and allocator */
|
||||
int sbi_scratch_init(struct sbi_scratch *scratch);
|
||||
|
||||
/**
|
||||
* Allocate from extra space in sbi_scratch
|
||||
*
|
||||
* @return zero on failure and non-zero (>= SBI_SCRATCH_EXTRA_SPACE_OFFSET)
|
||||
* on success
|
||||
@@ -102,6 +110,19 @@ void sbi_scratch_free_offset(unsigned long offset);
|
||||
#define sbi_scratch_thishart_offset_ptr(offset) \
|
||||
((void *)sbi_scratch_thishart_ptr() + (offset))
|
||||
|
||||
/** HART id to scratch table */
|
||||
extern struct sbi_scratch *hartid_to_scratch_table[];
|
||||
|
||||
/** Get sbi_scratch from HART id */
|
||||
#define sbi_hartid_to_scratch(__hartid) \
|
||||
hartid_to_scratch_table[__hartid]
|
||||
|
||||
/** Last HART id having a sbi_scratch pointer */
|
||||
extern u32 last_hartid_having_scratch;
|
||||
|
||||
/** Get last HART id having a sbi_scratch pointer */
|
||||
#define sbi_scratch_last_hartid() last_hartid_having_scratch
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
@@ -12,8 +12,15 @@
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
/*
|
||||
Provides sbi_strcmp for the completeness of supporting string functions.
|
||||
it is not recommended to use sbi_strcmp() but use sbi_strncmp instead.
|
||||
*/
|
||||
|
||||
int sbi_strcmp(const char *a, const char *b);
|
||||
|
||||
int sbi_strncmp(const char *a, const char *b, size_t count);
|
||||
|
||||
size_t sbi_strlen(const char *str);
|
||||
|
||||
size_t sbi_strnlen(const char *str, size_t count);
|
||||
|
@@ -12,18 +12,8 @@
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct sbi_scratch;
|
||||
bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason);
|
||||
|
||||
int sbi_system_early_init(struct sbi_scratch *scratch, bool cold_boot);
|
||||
|
||||
int sbi_system_final_init(struct sbi_scratch *scratch, bool cold_boot);
|
||||
|
||||
void sbi_system_early_exit(struct sbi_scratch *scratch);
|
||||
|
||||
void sbi_system_final_exit(struct sbi_scratch *scratch);
|
||||
|
||||
void __noreturn sbi_system_reboot(struct sbi_scratch *scratch, u32 type);
|
||||
|
||||
void __noreturn sbi_system_shutdown(struct sbi_scratch *scratch, u32 type);
|
||||
void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason);
|
||||
|
||||
#endif
|
||||
|
@@ -14,22 +14,31 @@
|
||||
|
||||
struct sbi_scratch;
|
||||
|
||||
u64 sbi_timer_value(struct sbi_scratch *scratch);
|
||||
/** Get timer value for current HART */
|
||||
u64 sbi_timer_value(void);
|
||||
|
||||
u64 sbi_timer_virt_value(struct sbi_scratch *scratch);
|
||||
/** Get virtualized timer value for current HART */
|
||||
u64 sbi_timer_virt_value(void);
|
||||
|
||||
u64 sbi_timer_get_delta(struct sbi_scratch *scratch);
|
||||
/** Get timer delta value for current HART */
|
||||
u64 sbi_timer_get_delta(void);
|
||||
|
||||
void sbi_timer_set_delta(struct sbi_scratch *scratch, ulong delta);
|
||||
/** Set timer delta value for current HART */
|
||||
void sbi_timer_set_delta(ulong delta);
|
||||
|
||||
void sbi_timer_set_delta_upper(struct sbi_scratch *scratch, ulong delta_upper);
|
||||
/** Set upper 32-bits of timer delta value for current HART */
|
||||
void sbi_timer_set_delta_upper(ulong delta_upper);
|
||||
|
||||
void sbi_timer_event_start(struct sbi_scratch *scratch, u64 next_event);
|
||||
/** Start timer event for current HART */
|
||||
void sbi_timer_event_start(u64 next_event);
|
||||
|
||||
void sbi_timer_process(struct sbi_scratch *scratch);
|
||||
/** Process timer event for current HART */
|
||||
void sbi_timer_process(void);
|
||||
|
||||
/* Initialize timer */
|
||||
int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot);
|
||||
|
||||
/* Exit timer */
|
||||
void sbi_timer_exit(struct sbi_scratch *scratch);
|
||||
|
||||
#endif
|
||||
|
@@ -12,6 +12,7 @@
|
||||
#define __SBI_TLB_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
#include <sbi/sbi_hartmask.h>
|
||||
|
||||
/* clang-format off */
|
||||
|
||||
@@ -21,30 +22,38 @@
|
||||
|
||||
#define SBI_TLB_FIFO_NUM_ENTRIES 8
|
||||
|
||||
enum sbi_tlb_info_types {
|
||||
SBI_TLB_FLUSH_VMA,
|
||||
SBI_TLB_FLUSH_VMA_ASID,
|
||||
SBI_TLB_FLUSH_GVMA,
|
||||
SBI_TLB_FLUSH_GVMA_VMID,
|
||||
SBI_TLB_FLUSH_VVMA,
|
||||
SBI_TLB_FLUSH_VVMA_ASID,
|
||||
SBI_ITLB_FLUSH
|
||||
};
|
||||
|
||||
struct sbi_scratch;
|
||||
|
||||
struct sbi_tlb_info {
|
||||
unsigned long start;
|
||||
unsigned long size;
|
||||
unsigned long asid;
|
||||
unsigned long type;
|
||||
unsigned long shart_mask;
|
||||
unsigned long vmid;
|
||||
void (*local_fn)(struct sbi_tlb_info *tinfo);
|
||||
struct sbi_hartmask smask;
|
||||
};
|
||||
|
||||
#define SBI_TLB_INFO_SIZE sizeof(struct sbi_tlb_info)
|
||||
void sbi_tlb_local_hfence_vvma(struct sbi_tlb_info *tinfo);
|
||||
void sbi_tlb_local_hfence_gvma(struct sbi_tlb_info *tinfo);
|
||||
void sbi_tlb_local_sfence_vma(struct sbi_tlb_info *tinfo);
|
||||
void sbi_tlb_local_hfence_vvma_asid(struct sbi_tlb_info *tinfo);
|
||||
void sbi_tlb_local_hfence_gvma_vmid(struct sbi_tlb_info *tinfo);
|
||||
void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo);
|
||||
void sbi_tlb_local_fence_i(struct sbi_tlb_info *tinfo);
|
||||
|
||||
int sbi_tlb_request(struct sbi_scratch *scratch, ulong hmask,
|
||||
ulong hbase, struct sbi_tlb_info *tinfo);
|
||||
#define SBI_TLB_INFO_INIT(__p, __start, __size, __asid, __vmid, __lfn, __src) \
|
||||
do { \
|
||||
(__p)->start = (__start); \
|
||||
(__p)->size = (__size); \
|
||||
(__p)->asid = (__asid); \
|
||||
(__p)->vmid = (__vmid); \
|
||||
(__p)->local_fn = (__lfn); \
|
||||
SBI_HARTMASK_INIT_EXCEPT(&(__p)->smask, (__src)); \
|
||||
} while (0)
|
||||
|
||||
#define SBI_TLB_INFO_SIZE sizeof(struct sbi_tlb_info)
|
||||
|
||||
int sbi_tlb_request(ulong hmask, ulong hbase, struct sbi_tlb_info *tinfo);
|
||||
|
||||
int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot);
|
||||
|
||||
|
@@ -85,6 +85,19 @@
|
||||
/** Last member index in sbi_trap_regs */
|
||||
#define SBI_TRAP_REGS_last 35
|
||||
|
||||
/** Index of epc member in sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_epc 0
|
||||
/** Index of cause member in sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_cause 1
|
||||
/** Index of tval member in sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_tval 2
|
||||
/** Index of tval2 member in sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_tval2 3
|
||||
/** Index of tinst member in sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_tinst 4
|
||||
/** Last member index in sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_last 5
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
/** Get offset of member with name 'x' in sbi_trap_regs */
|
||||
@@ -92,6 +105,11 @@
|
||||
/** Size (in bytes) of sbi_trap_regs */
|
||||
#define SBI_TRAP_REGS_SIZE SBI_TRAP_REGS_OFFSET(last)
|
||||
|
||||
/** Get offset of member with name 'x' in sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_OFFSET(x) ((SBI_TRAP_INFO_##x) * __SIZEOF_POINTER__)
|
||||
/** Size (in bytes) of sbi_trap_info */
|
||||
#define SBI_TRAP_INFO_SIZE SBI_TRAP_INFO_OFFSET(last)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
@@ -168,7 +186,7 @@ struct sbi_trap_regs {
|
||||
unsigned long mstatus;
|
||||
/** mstatusH register state (only for 32-bit) */
|
||||
unsigned long mstatusH;
|
||||
} __packed;
|
||||
};
|
||||
|
||||
/** Representation of trap details */
|
||||
struct sbi_trap_info {
|
||||
@@ -184,14 +202,12 @@ struct sbi_trap_info {
|
||||
unsigned long tinst;
|
||||
};
|
||||
|
||||
struct sbi_scratch;
|
||||
|
||||
int sbi_trap_redirect(struct sbi_trap_regs *regs,
|
||||
struct sbi_trap_info *trap,
|
||||
struct sbi_scratch *scratch);
|
||||
struct sbi_trap_info *trap);
|
||||
|
||||
void sbi_trap_handler(struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch);
|
||||
void sbi_trap_handler(struct sbi_trap_regs *regs);
|
||||
|
||||
void __noreturn sbi_trap_exit(const struct sbi_trap_regs *regs);
|
||||
|
||||
#endif
|
||||
|
||||
|
@@ -56,6 +56,8 @@ typedef unsigned long physical_size_t;
|
||||
|
||||
#define TRUE 1
|
||||
#define FALSE 0
|
||||
#define true TRUE
|
||||
#define false FALSE
|
||||
|
||||
#define NULL ((void *)0)
|
||||
|
||||
@@ -76,6 +78,8 @@ typedef unsigned long physical_size_t;
|
||||
const typeof(((type *)0)->member) * __mptr = (ptr); \
|
||||
(type *)((char *)__mptr - offsetof(type, member)); })
|
||||
|
||||
#define array_size(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
|
||||
@@ -89,7 +93,8 @@ typedef unsigned long physical_size_t;
|
||||
/* clang-format on */
|
||||
|
||||
#else
|
||||
/* OPENSBI_EXTERNAL_SBI_TYPES could be defined in CFLAGS for using the
|
||||
/*
|
||||
* OPENSBI_EXTERNAL_SBI_TYPES could be defined in CFLAGS for using the
|
||||
* external definitions of data types and common macros.
|
||||
* OPENSBI_EXTERNAL_SBI_TYPES is the file name to external header file,
|
||||
* the external build system should address the additional include
|
||||
|
@@ -17,12 +17,10 @@ struct sbi_trap_info;
|
||||
|
||||
#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type) \
|
||||
type sbi_load_##type(const type *addr, \
|
||||
struct sbi_scratch *scratch, \
|
||||
struct sbi_trap_info *trap);
|
||||
|
||||
#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type) \
|
||||
void sbi_store_##type(type *addr, type val, \
|
||||
struct sbi_scratch *scratch, \
|
||||
struct sbi_trap_info *trap);
|
||||
|
||||
DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8)
|
||||
@@ -38,7 +36,6 @@ DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64)
|
||||
DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64)
|
||||
DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong)
|
||||
|
||||
ulong sbi_get_insn(ulong mepc, struct sbi_scratch *scratch,
|
||||
struct sbi_trap_info *trap);
|
||||
ulong sbi_get_insn(ulong mepc, struct sbi_trap_info *trap);
|
||||
|
||||
#endif
|
||||
|
@@ -11,12 +11,12 @@
|
||||
#define __SBI_VERSION_H__
|
||||
|
||||
#define OPENSBI_VERSION_MAJOR 0
|
||||
#define OPENSBI_VERSION_MINOR 6
|
||||
#define OPENSBI_VERSION_MINOR 9
|
||||
|
||||
/**
|
||||
* OpenSBI 32-bit version with:
|
||||
* 1. upper 16-bits as major number
|
||||
* 2. lower 16-bits as minor number
|
||||
* OpenSBI 32-bit version with:
|
||||
* 1. upper 16-bits as major number
|
||||
* 2. lower 16-bits as minor number
|
||||
*/
|
||||
#define OPENSBI_VERSION ((OPENSBI_VERSION_MAJOR << 16) | \
|
||||
(OPENSBI_VERSION_MINOR))
|
||||
|
73
include/sbi_utils/fdt/fdt_domain.h
Normal file
73
include/sbi_utils/fdt/fdt_domain.h
Normal file
@@ -0,0 +1,73 @@
|
||||
// SPDX-License-Identifier: BSD-2-Clause
|
||||
/*
|
||||
* fdt_domain.c - Flat Device Tree Domain helper routines
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_DOMAIN_H__
|
||||
#define __FDT_DOMAIN_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct sbi_domain;
|
||||
|
||||
/**
|
||||
* Iterate over each domains in device tree
|
||||
*
|
||||
* @param fdt device tree blob
|
||||
* @param opaque private pointer for each iteration
|
||||
* @param fn callback function for each iteration
|
||||
*
|
||||
* @return 0 on success and negative error code on failure
|
||||
*/
|
||||
int fdt_iterate_each_domain(void *fdt, void *opaque,
|
||||
int (*fn)(void *fdt, int domain_offset,
|
||||
void *opaque));
|
||||
|
||||
/**
|
||||
* Iterate over each memregion of a domain in device tree
|
||||
*
|
||||
* @param fdt device tree blob
|
||||
* @param domain_offset domain DT node offset
|
||||
* @param opaque private pointer for each iteration
|
||||
* @param fn callback function for each iteration
|
||||
*
|
||||
* @return 0 on success and negative error code on failure
|
||||
*/
|
||||
int fdt_iterate_each_memregion(void *fdt, int domain_offset, void *opaque,
|
||||
int (*fn)(void *fdt, int domain_offset,
|
||||
int region_offset, u32 region_access,
|
||||
void *opaque));
|
||||
|
||||
/**
|
||||
* Fix up the domain configuration in the device tree
|
||||
*
|
||||
* This routine:
|
||||
* 1. Disables MMIO devices not accessible to the coldboot HART domain
|
||||
* 2. Removes "opensbi-domain" DT property from CPU DT nodes
|
||||
* 3. Removes domain configuration DT node under /chosen DT node
|
||||
*
|
||||
* It is recommended that platform support call this function in
|
||||
* their final_init() platform operation.
|
||||
*
|
||||
* @param fdt device tree blob
|
||||
*/
|
||||
void fdt_domain_fixup(void *fdt);
|
||||
|
||||
/**
|
||||
* Populate domains from device tree
|
||||
*
|
||||
* It is recommended that platform support call this function in
|
||||
* their domains_init() platform operation.
|
||||
*
|
||||
* @param fdt device tree blob
|
||||
*
|
||||
* @return 0 on success and negative error code on failure
|
||||
*/
|
||||
int fdt_domains_populate(void *fdt);
|
||||
|
||||
#endif /* __FDT_DOMAIN_H__ */
|
78
include/sbi_utils/fdt/fdt_fixup.h
Normal file
78
include/sbi_utils/fdt/fdt_fixup.h
Normal file
@@ -0,0 +1,78 @@
|
||||
// SPDX-License-Identifier: BSD-2-Clause
|
||||
/*
|
||||
* fdt_fixup.h - Flat Device Tree manipulation helper routines
|
||||
* Implement platform specific DT fixups on top of libfdt.
|
||||
*
|
||||
* Copyright (C) 2020 Bin Meng <bmeng.cn@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_FIXUP_H__
|
||||
#define __FDT_FIXUP_H__
|
||||
|
||||
/**
|
||||
* Fix up the CPU node in the device tree
|
||||
*
|
||||
* This routine updates the "status" property of a CPU node in the device tree
|
||||
* to "disabled" if that hart is in disabled state in OpenSBI.
|
||||
*
|
||||
* It is recommended that platform codes call this helper in their final_init()
|
||||
*
|
||||
* @param fdt: device tree blob
|
||||
*/
|
||||
void fdt_cpu_fixup(void *fdt);
|
||||
|
||||
/**
|
||||
* Fix up the PLIC node in the device tree
|
||||
*
|
||||
* This routine updates the "interrupt-extended" property of the PLIC node in
|
||||
* the device tree to hide the M-mode external interrupt from CPUs.
|
||||
*
|
||||
* It is recommended that platform codes call this helper in their final_init()
|
||||
*
|
||||
* @param fdt: device tree blob
|
||||
* @param compat: PLIC node compatible string
|
||||
*/
|
||||
void fdt_plic_fixup(void *fdt, const char *compat);
|
||||
|
||||
/**
|
||||
* Fix up the reserved memory node in the device tree
|
||||
*
|
||||
* This routine inserts a child node of the reserved memory node in the device
|
||||
* tree that describes the protected memory region done by OpenSBI via PMP.
|
||||
*
|
||||
* It is recommended that platform codes call this helper in their final_init()
|
||||
*
|
||||
* @param fdt: device tree blob
|
||||
* @return zero on success and -ve on failure
|
||||
*/
|
||||
int fdt_reserved_memory_fixup(void *fdt);
|
||||
|
||||
/**
|
||||
* Fix up the reserved memory subnodes in the device tree
|
||||
*
|
||||
* This routine adds the no-map property to the reserved memory subnodes so
|
||||
* that the OS does not map those PMP protected memory regions.
|
||||
*
|
||||
* Platform codes must call this helper in their final_init() after fdt_fixups()
|
||||
* if the OS should not map the PMP protected reserved regions.
|
||||
*
|
||||
* @param fdt: device tree blob
|
||||
* @return zero on success and -ve on failure
|
||||
*/
|
||||
int fdt_reserved_memory_nomap_fixup(void *fdt);
|
||||
|
||||
/**
|
||||
* General device tree fix-up
|
||||
*
|
||||
* This routine do all required device tree fix-ups for a typical platform.
|
||||
* It fixes up the PLIC node and the reserved memory node in the device tree
|
||||
* by calling the corresponding helper routines to accomplish the task.
|
||||
*
|
||||
* It is recommended that platform codes call this helper in their final_init()
|
||||
*
|
||||
* @param fdt: device tree blob
|
||||
*/
|
||||
void fdt_fixups(void *fdt);
|
||||
|
||||
#endif /* __FDT_FIXUP_H__ */
|
||||
|
68
include/sbi_utils/fdt/fdt_helper.h
Normal file
68
include/sbi_utils/fdt/fdt_helper.h
Normal file
@@ -0,0 +1,68 @@
|
||||
// SPDX-License-Identifier: BSD-2-Clause
|
||||
/*
|
||||
* fdt_helper.h - Flat Device Tree parsing helper routines
|
||||
* Implement helper routines to parse FDT nodes on top of
|
||||
* libfdt for OpenSBI usage
|
||||
*
|
||||
* Copyright (C) 2020 Bin Meng <bmeng.cn@gmail.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_HELPER_H__
|
||||
#define __FDT_HELPER_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct fdt_match {
|
||||
const char *compatible;
|
||||
void *data;
|
||||
};
|
||||
|
||||
struct platform_uart_data {
|
||||
unsigned long addr;
|
||||
unsigned long freq;
|
||||
unsigned long baud;
|
||||
unsigned long reg_shift;
|
||||
unsigned long reg_io_width;
|
||||
};
|
||||
|
||||
const struct fdt_match *fdt_match_node(void *fdt, int nodeoff,
|
||||
const struct fdt_match *match_table);
|
||||
|
||||
int fdt_find_match(void *fdt, int startoff,
|
||||
const struct fdt_match *match_table,
|
||||
const struct fdt_match **out_match);
|
||||
|
||||
int fdt_get_node_addr_size(void *fdt, int node, unsigned long *addr,
|
||||
unsigned long *size);
|
||||
|
||||
int fdt_parse_hart_id(void *fdt, int cpu_offset, u32 *hartid);
|
||||
|
||||
int fdt_parse_max_hart_id(void *fdt, u32 *max_hartid);
|
||||
|
||||
int fdt_parse_shakti_uart_node(void *fdt, int nodeoffset,
|
||||
struct platform_uart_data *uart);
|
||||
|
||||
int fdt_parse_sifive_uart_node(void *fdt, int nodeoffset,
|
||||
struct platform_uart_data *uart);
|
||||
|
||||
int fdt_parse_uart8250_node(void *fdt, int nodeoffset,
|
||||
struct platform_uart_data *uart);
|
||||
|
||||
int fdt_parse_uart8250(void *fdt, struct platform_uart_data *uart,
|
||||
const char *compatible);
|
||||
|
||||
struct plic_data;
|
||||
|
||||
int fdt_parse_plic_node(void *fdt, int nodeoffset, struct plic_data *plic);
|
||||
|
||||
int fdt_parse_plic(void *fdt, struct plic_data *plic, const char *compat);
|
||||
|
||||
struct clint_data;
|
||||
|
||||
int fdt_parse_clint_node(void *fdt, int nodeoffset, bool for_timer,
|
||||
struct clint_data *clint);
|
||||
|
||||
int fdt_parse_compat_addr(void *fdt, unsigned long *addr,
|
||||
const char *compatible);
|
||||
|
||||
#endif /* __FDT_HELPER_H__ */
|
32
include/sbi_utils/ipi/fdt_ipi.h
Normal file
32
include/sbi_utils/ipi/fdt_ipi.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_IPI_H__
|
||||
#define __FDT_IPI_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct fdt_ipi {
|
||||
const struct fdt_match *match_table;
|
||||
int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
|
||||
int (*warm_init)(void);
|
||||
void (*exit)(void);
|
||||
void (*send)(u32 target_hart);
|
||||
void (*clear)(u32 target_hart);
|
||||
};
|
||||
|
||||
void fdt_ipi_send(u32 target_hart);
|
||||
|
||||
void fdt_ipi_clear(u32 target_hart);
|
||||
|
||||
void fdt_ipi_exit(void);
|
||||
|
||||
int fdt_ipi_init(bool cold_boot);
|
||||
|
||||
#endif
|
26
include/sbi_utils/irqchip/fdt_irqchip.h
Normal file
26
include/sbi_utils/irqchip/fdt_irqchip.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_IRQCHIP_H__
|
||||
#define __FDT_IRQCHIP_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct fdt_irqchip {
|
||||
const struct fdt_match *match_table;
|
||||
int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
|
||||
int (*warm_init)(void);
|
||||
void (*exit)(void);
|
||||
};
|
||||
|
||||
void fdt_irqchip_exit(void);
|
||||
|
||||
int fdt_irqchip_init(bool cold_boot);
|
||||
|
||||
#endif
|
@@ -12,14 +12,18 @@
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
void plic_fdt_fixup(void *fdt, const char *compat);
|
||||
struct plic_data {
|
||||
unsigned long addr;
|
||||
unsigned long num_src;
|
||||
};
|
||||
|
||||
int plic_warm_irqchip_init(u32 target_hart, int m_cntx_id, int s_cntx_id);
|
||||
int plic_warm_irqchip_init(struct plic_data *plic,
|
||||
int m_cntx_id, int s_cntx_id);
|
||||
|
||||
int plic_cold_irqchip_init(unsigned long base, u32 num_sources, u32 hart_count);
|
||||
int plic_cold_irqchip_init(struct plic_data *plic);
|
||||
|
||||
void plic_set_thresh(u32 cntxid, u32 val);
|
||||
void plic_set_thresh(struct plic_data *plic, u32 cntxid, u32 val);
|
||||
|
||||
void plic_set_ie(u32 cntxid, u32 word_index, u32 val);
|
||||
void plic_set_ie(struct plic_data *plic, u32 cntxid, u32 word_index, u32 val);
|
||||
|
||||
#endif
|
||||
|
28
include/sbi_utils/reset/fdt_reset.h
Normal file
28
include/sbi_utils/reset/fdt_reset.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_RESET_H__
|
||||
#define __FDT_RESET_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct fdt_reset {
|
||||
const struct fdt_match *match_table;
|
||||
int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
|
||||
int (*system_reset_check)(u32 reset_type, u32 reset_reason);
|
||||
void (*system_reset)(u32 reset_type, u32 reset_reason);
|
||||
};
|
||||
|
||||
int fdt_system_reset_check(u32 reset_type, u32 reset_reason);
|
||||
|
||||
void fdt_system_reset(u32 reset_type, u32 reset_reason);
|
||||
|
||||
int fdt_reset_init(void);
|
||||
|
||||
#endif
|
28
include/sbi_utils/serial/fdt_serial.h
Normal file
28
include/sbi_utils/serial/fdt_serial.h
Normal file
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_SERIAL_H__
|
||||
#define __FDT_SERIAL_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct fdt_serial {
|
||||
const struct fdt_match *match_table;
|
||||
int (*init)(void *fdt, int nodeoff, const struct fdt_match *match);
|
||||
void (*putc)(char ch);
|
||||
int (*getc)(void);
|
||||
};
|
||||
|
||||
void fdt_serial_putc(char ch);
|
||||
|
||||
int fdt_serial_getc(void);
|
||||
|
||||
int fdt_serial_init(void);
|
||||
|
||||
#endif
|
18
include/sbi_utils/serial/shakti-uart.h
Normal file
18
include/sbi_utils/serial/shakti-uart.h
Normal file
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Vijai Kumar K <vijai@behindbytes.com>
|
||||
*/
|
||||
|
||||
#ifndef __SERIAL_SHAKTI_UART_H__
|
||||
#define __SERIAL_SHAKTI_UART_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
void shakti_uart_putc(char ch);
|
||||
|
||||
int shakti_uart_getc(void);
|
||||
|
||||
int shakti_uart_init(unsigned long base, u32 in_freq, u32 baudrate);
|
||||
|
||||
#endif
|
@@ -12,15 +12,30 @@
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
void clint_ipi_send(u32 target_hart);
|
||||
struct clint_data {
|
||||
/* Public details */
|
||||
unsigned long addr;
|
||||
u32 first_hartid;
|
||||
u32 hart_count;
|
||||
bool has_64bit_mmio;
|
||||
/* Private details (initialized and used by CLINT library)*/
|
||||
u32 *ipi;
|
||||
struct clint_data *time_delta_reference;
|
||||
unsigned long time_delta_computed;
|
||||
u64 time_delta;
|
||||
u64 *time_val;
|
||||
u64 *time_cmp;
|
||||
u64 (*time_rd)(volatile u64 *addr);
|
||||
void (*time_wr)(u64 value, volatile u64 *addr);
|
||||
};
|
||||
|
||||
void clint_ipi_sync(u32 target_hart);
|
||||
void clint_ipi_send(u32 target_hart);
|
||||
|
||||
void clint_ipi_clear(u32 target_hart);
|
||||
|
||||
int clint_warm_ipi_init(void);
|
||||
|
||||
int clint_cold_ipi_init(unsigned long base, u32 hart_count);
|
||||
int clint_cold_ipi_init(struct clint_data *clint);
|
||||
|
||||
u64 clint_timer_value(void);
|
||||
|
||||
@@ -30,7 +45,7 @@ void clint_timer_event_start(u64 next_event);
|
||||
|
||||
int clint_warm_timer_init(void);
|
||||
|
||||
int clint_cold_timer_init(unsigned long base, u32 hart_count,
|
||||
bool has_64bit_mmio);
|
||||
int clint_cold_timer_init(struct clint_data *clint,
|
||||
struct clint_data *reference);
|
||||
|
||||
#endif
|
||||
|
@@ -14,6 +14,8 @@ void htif_putc(char ch);
|
||||
|
||||
int htif_getc(void);
|
||||
|
||||
int htif_system_down(u32 type);
|
||||
int htif_system_reset_check(u32 type, u32 reason);
|
||||
|
||||
void htif_system_reset(u32 type, u32 reason);
|
||||
|
||||
#endif
|
||||
|
21
include/sbi_utils/sys/sifive_test.h
Normal file
21
include/sbi_utils/sys/sifive_test.h
Normal file
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __SYS_SIFIVE_TEST_H__
|
||||
#define __SYS_SIFIVE_TEST_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
int sifive_test_system_reset_check(u32 type, u32 reason);
|
||||
|
||||
void sifive_test_system_reset(u32 type, u32 reason);
|
||||
|
||||
int sifive_test_init(unsigned long base);
|
||||
|
||||
#endif
|
35
include/sbi_utils/timer/fdt_timer.h
Normal file
35
include/sbi_utils/timer/fdt_timer.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#ifndef __FDT_TIMER_H__
|
||||
#define __FDT_TIMER_H__
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
|
||||
struct fdt_timer {
|
||||
const struct fdt_match *match_table;
|
||||
int (*cold_init)(void *fdt, int nodeoff, const struct fdt_match *match);
|
||||
int (*warm_init)(void);
|
||||
void (*exit)(void);
|
||||
u64 (*value)(void);
|
||||
void (*event_stop)(void);
|
||||
void (*event_start)(u64 next_event);
|
||||
};
|
||||
|
||||
u64 fdt_timer_value(void);
|
||||
|
||||
void fdt_timer_event_stop(void);
|
||||
|
||||
void fdt_timer_event_start(u64 next_event);
|
||||
|
||||
void fdt_timer_exit(void);
|
||||
|
||||
int fdt_timer_init(bool cold_boot);
|
||||
|
||||
#endif
|
@@ -12,24 +12,32 @@ libsbi-objs-y += riscv_atomic.o
|
||||
libsbi-objs-y += riscv_hardfp.o
|
||||
libsbi-objs-y += riscv_locks.o
|
||||
|
||||
libsbi-objs-y += sbi_bitmap.o
|
||||
libsbi-objs-y += sbi_bitops.o
|
||||
libsbi-objs-y += sbi_console.o
|
||||
libsbi-objs-y += sbi_domain.o
|
||||
libsbi-objs-y += sbi_ecall.o
|
||||
libsbi-objs-y += sbi_ecall_base.o
|
||||
libsbi-objs-y += sbi_ecall_hsm.o
|
||||
libsbi-objs-y += sbi_ecall_legacy.o
|
||||
libsbi-objs-y += sbi_ecall_replace.o
|
||||
libsbi-objs-y += sbi_ecall_vendor.o
|
||||
libsbi-objs-y += sbi_emulate_csr.o
|
||||
libsbi-objs-y += sbi_fifo.o
|
||||
libsbi-objs-y += sbi_hfence.o
|
||||
libsbi-objs-y += sbi_hart.o
|
||||
libsbi-objs-y += sbi_math.o
|
||||
libsbi-objs-y += sbi_hfence.o
|
||||
libsbi-objs-y += sbi_hsm.o
|
||||
libsbi-objs-y += sbi_illegal_insn.o
|
||||
libsbi-objs-y += sbi_init.o
|
||||
libsbi-objs-y += sbi_ipi.o
|
||||
libsbi-objs-y += sbi_misaligned_ldst.o
|
||||
libsbi-objs-y += sbi_platform.o
|
||||
libsbi-objs-y += sbi_scratch.o
|
||||
libsbi-objs-y += sbi_string.o
|
||||
libsbi-objs-y += sbi_system.o
|
||||
libsbi-objs-y += sbi_timer.o
|
||||
libsbi-objs-y += sbi_tlb.o
|
||||
libsbi-objs-y += sbi_trap.o
|
||||
libsbi-objs-y += sbi_string.o
|
||||
libsbi-objs-y += sbi_unpriv.o
|
||||
libsbi-objs-y += sbi_expected_trap.o
|
||||
|
@@ -17,8 +17,13 @@ int misa_extension_imp(char ext)
|
||||
{
|
||||
unsigned long misa = csr_read(CSR_MISA);
|
||||
|
||||
if (misa)
|
||||
return misa & (1 << (ext - 'A'));
|
||||
if (misa) {
|
||||
if ('A' <= ext && ext <= 'Z')
|
||||
return misa & (1 << (ext - 'A'));
|
||||
if ('a' <= ext && ext <= 'z')
|
||||
return misa & (1 << (ext - 'a'));
|
||||
return 0;
|
||||
}
|
||||
|
||||
return sbi_platform_misa_extension(sbi_platform_thishart_ptr(), ext);
|
||||
}
|
||||
@@ -44,144 +49,129 @@ int misa_xlen(void)
|
||||
return r ? r : -1;
|
||||
}
|
||||
|
||||
void misa_string(int xlen, char *out, unsigned int out_sz)
|
||||
{
|
||||
unsigned int i, pos = 0;
|
||||
const char valid_isa_order[] = "iemafdqclbjtpvnsuhkorwxyzg";
|
||||
|
||||
if (!out)
|
||||
return;
|
||||
|
||||
if (5 <= (out_sz - pos)) {
|
||||
out[pos++] = 'r';
|
||||
out[pos++] = 'v';
|
||||
switch (xlen) {
|
||||
case 1:
|
||||
out[pos++] = '3';
|
||||
out[pos++] = '2';
|
||||
break;
|
||||
case 2:
|
||||
out[pos++] = '6';
|
||||
out[pos++] = '4';
|
||||
break;
|
||||
case 3:
|
||||
out[pos++] = '1';
|
||||
out[pos++] = '2';
|
||||
out[pos++] = '8';
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < array_size(valid_isa_order) && (pos < out_sz); i++) {
|
||||
if (misa_extension_imp(valid_isa_order[i]))
|
||||
out[pos++] = valid_isa_order[i];
|
||||
}
|
||||
|
||||
if (pos < out_sz)
|
||||
out[pos++] = '\0';
|
||||
}
|
||||
|
||||
unsigned long csr_read_num(int csr_num)
|
||||
{
|
||||
#define switchcase_csr_read(__csr_num, __val) \
|
||||
case __csr_num: \
|
||||
__val = csr_read(__csr_num); \
|
||||
break;
|
||||
#define switchcase_csr_read_2(__csr_num, __val) \
|
||||
switchcase_csr_read(__csr_num + 0, __val) \
|
||||
switchcase_csr_read(__csr_num + 1, __val)
|
||||
#define switchcase_csr_read_4(__csr_num, __val) \
|
||||
switchcase_csr_read_2(__csr_num + 0, __val) \
|
||||
switchcase_csr_read_2(__csr_num + 2, __val)
|
||||
#define switchcase_csr_read_8(__csr_num, __val) \
|
||||
switchcase_csr_read_4(__csr_num + 0, __val) \
|
||||
switchcase_csr_read_4(__csr_num + 4, __val)
|
||||
#define switchcase_csr_read_16(__csr_num, __val) \
|
||||
switchcase_csr_read_8(__csr_num + 0, __val) \
|
||||
switchcase_csr_read_8(__csr_num + 8, __val)
|
||||
#define switchcase_csr_read_32(__csr_num, __val) \
|
||||
switchcase_csr_read_16(__csr_num + 0, __val) \
|
||||
switchcase_csr_read_16(__csr_num + 16, __val)
|
||||
#define switchcase_csr_read_64(__csr_num, __val) \
|
||||
switchcase_csr_read_32(__csr_num + 0, __val) \
|
||||
switchcase_csr_read_32(__csr_num + 32, __val)
|
||||
|
||||
unsigned long ret = 0;
|
||||
|
||||
switch (csr_num) {
|
||||
case CSR_PMPCFG0:
|
||||
ret = csr_read(CSR_PMPCFG0);
|
||||
break;
|
||||
case CSR_PMPCFG1:
|
||||
ret = csr_read(CSR_PMPCFG1);
|
||||
break;
|
||||
case CSR_PMPCFG2:
|
||||
ret = csr_read(CSR_PMPCFG2);
|
||||
break;
|
||||
case CSR_PMPCFG3:
|
||||
ret = csr_read(CSR_PMPCFG3);
|
||||
break;
|
||||
case CSR_PMPADDR0:
|
||||
ret = csr_read(CSR_PMPADDR0);
|
||||
break;
|
||||
case CSR_PMPADDR1:
|
||||
ret = csr_read(CSR_PMPADDR1);
|
||||
break;
|
||||
case CSR_PMPADDR2:
|
||||
ret = csr_read(CSR_PMPADDR2);
|
||||
break;
|
||||
case CSR_PMPADDR3:
|
||||
ret = csr_read(CSR_PMPADDR3);
|
||||
break;
|
||||
case CSR_PMPADDR4:
|
||||
ret = csr_read(CSR_PMPADDR4);
|
||||
break;
|
||||
case CSR_PMPADDR5:
|
||||
ret = csr_read(CSR_PMPADDR5);
|
||||
break;
|
||||
case CSR_PMPADDR6:
|
||||
ret = csr_read(CSR_PMPADDR6);
|
||||
break;
|
||||
case CSR_PMPADDR7:
|
||||
ret = csr_read(CSR_PMPADDR7);
|
||||
break;
|
||||
case CSR_PMPADDR8:
|
||||
ret = csr_read(CSR_PMPADDR8);
|
||||
break;
|
||||
case CSR_PMPADDR9:
|
||||
ret = csr_read(CSR_PMPADDR9);
|
||||
break;
|
||||
case CSR_PMPADDR10:
|
||||
ret = csr_read(CSR_PMPADDR10);
|
||||
break;
|
||||
case CSR_PMPADDR11:
|
||||
ret = csr_read(CSR_PMPADDR11);
|
||||
break;
|
||||
case CSR_PMPADDR12:
|
||||
ret = csr_read(CSR_PMPADDR12);
|
||||
break;
|
||||
case CSR_PMPADDR13:
|
||||
ret = csr_read(CSR_PMPADDR13);
|
||||
break;
|
||||
case CSR_PMPADDR14:
|
||||
ret = csr_read(CSR_PMPADDR14);
|
||||
break;
|
||||
case CSR_PMPADDR15:
|
||||
ret = csr_read(CSR_PMPADDR15);
|
||||
break;
|
||||
switchcase_csr_read_16(CSR_PMPCFG0, ret)
|
||||
switchcase_csr_read_64(CSR_PMPADDR0, ret)
|
||||
default:
|
||||
break;
|
||||
};
|
||||
|
||||
return ret;
|
||||
|
||||
#undef switchcase_csr_read_64
|
||||
#undef switchcase_csr_read_32
|
||||
#undef switchcase_csr_read_16
|
||||
#undef switchcase_csr_read_8
|
||||
#undef switchcase_csr_read_4
|
||||
#undef switchcase_csr_read_2
|
||||
#undef switchcase_csr_read
|
||||
}
|
||||
|
||||
void csr_write_num(int csr_num, unsigned long val)
|
||||
{
|
||||
#define switchcase_csr_write(__csr_num, __val) \
|
||||
case __csr_num: \
|
||||
csr_write(__csr_num, __val); \
|
||||
break;
|
||||
#define switchcase_csr_write_2(__csr_num, __val) \
|
||||
switchcase_csr_write(__csr_num + 0, __val) \
|
||||
switchcase_csr_write(__csr_num + 1, __val)
|
||||
#define switchcase_csr_write_4(__csr_num, __val) \
|
||||
switchcase_csr_write_2(__csr_num + 0, __val) \
|
||||
switchcase_csr_write_2(__csr_num + 2, __val)
|
||||
#define switchcase_csr_write_8(__csr_num, __val) \
|
||||
switchcase_csr_write_4(__csr_num + 0, __val) \
|
||||
switchcase_csr_write_4(__csr_num + 4, __val)
|
||||
#define switchcase_csr_write_16(__csr_num, __val) \
|
||||
switchcase_csr_write_8(__csr_num + 0, __val) \
|
||||
switchcase_csr_write_8(__csr_num + 8, __val)
|
||||
#define switchcase_csr_write_32(__csr_num, __val) \
|
||||
switchcase_csr_write_16(__csr_num + 0, __val) \
|
||||
switchcase_csr_write_16(__csr_num + 16, __val)
|
||||
#define switchcase_csr_write_64(__csr_num, __val) \
|
||||
switchcase_csr_write_32(__csr_num + 0, __val) \
|
||||
switchcase_csr_write_32(__csr_num + 32, __val)
|
||||
|
||||
switch (csr_num) {
|
||||
case CSR_PMPCFG0:
|
||||
csr_write(CSR_PMPCFG0, val);
|
||||
break;
|
||||
case CSR_PMPCFG1:
|
||||
csr_write(CSR_PMPCFG1, val);
|
||||
break;
|
||||
case CSR_PMPCFG2:
|
||||
csr_write(CSR_PMPCFG2, val);
|
||||
break;
|
||||
case CSR_PMPCFG3:
|
||||
csr_write(CSR_PMPCFG3, val);
|
||||
break;
|
||||
case CSR_PMPADDR0:
|
||||
csr_write(CSR_PMPADDR0, val);
|
||||
break;
|
||||
case CSR_PMPADDR1:
|
||||
csr_write(CSR_PMPADDR1, val);
|
||||
break;
|
||||
case CSR_PMPADDR2:
|
||||
csr_write(CSR_PMPADDR2, val);
|
||||
break;
|
||||
case CSR_PMPADDR3:
|
||||
csr_write(CSR_PMPADDR3, val);
|
||||
break;
|
||||
case CSR_PMPADDR4:
|
||||
csr_write(CSR_PMPADDR4, val);
|
||||
break;
|
||||
case CSR_PMPADDR5:
|
||||
csr_write(CSR_PMPADDR5, val);
|
||||
break;
|
||||
case CSR_PMPADDR6:
|
||||
csr_write(CSR_PMPADDR6, val);
|
||||
break;
|
||||
case CSR_PMPADDR7:
|
||||
csr_write(CSR_PMPADDR7, val);
|
||||
break;
|
||||
case CSR_PMPADDR8:
|
||||
csr_write(CSR_PMPADDR8, val);
|
||||
break;
|
||||
case CSR_PMPADDR9:
|
||||
csr_write(CSR_PMPADDR9, val);
|
||||
break;
|
||||
case CSR_PMPADDR10:
|
||||
csr_write(CSR_PMPADDR10, val);
|
||||
break;
|
||||
case CSR_PMPADDR11:
|
||||
csr_write(CSR_PMPADDR11, val);
|
||||
break;
|
||||
case CSR_PMPADDR12:
|
||||
csr_write(CSR_PMPADDR12, val);
|
||||
break;
|
||||
case CSR_PMPADDR13:
|
||||
csr_write(CSR_PMPADDR13, val);
|
||||
break;
|
||||
case CSR_PMPADDR14:
|
||||
csr_write(CSR_PMPADDR14, val);
|
||||
break;
|
||||
case CSR_PMPADDR15:
|
||||
csr_write(CSR_PMPADDR15, val);
|
||||
break;
|
||||
switchcase_csr_write_16(CSR_PMPCFG0, val)
|
||||
switchcase_csr_write_64(CSR_PMPADDR0, val)
|
||||
default:
|
||||
break;
|
||||
};
|
||||
|
||||
#undef switchcase_csr_write_64
|
||||
#undef switchcase_csr_write_32
|
||||
#undef switchcase_csr_write_16
|
||||
#undef switchcase_csr_write_8
|
||||
#undef switchcase_csr_write_4
|
||||
#undef switchcase_csr_write_2
|
||||
#undef switchcase_csr_write
|
||||
}
|
||||
|
||||
static unsigned long ctz(unsigned long x)
|
||||
@@ -207,7 +197,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
|
||||
if (n >= PMP_COUNT || log2len > __riscv_xlen || log2len < PMP_SHIFT)
|
||||
return SBI_EINVAL;
|
||||
|
||||
/* calculate PMP register and offset */
|
||||
/* calculate PMP register and offset */
|
||||
#if __riscv_xlen == 32
|
||||
pmpcfg_csr = CSR_PMPCFG0 + (n >> 2);
|
||||
pmpcfg_shift = (n & 3) << 3;
|
||||
@@ -224,7 +214,7 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
|
||||
|
||||
/* encode PMP config */
|
||||
prot |= (log2len == PMP_SHIFT) ? PMP_A_NA4 : PMP_A_NAPOT;
|
||||
cfgmask = ~(0xff << pmpcfg_shift);
|
||||
cfgmask = ~(0xffUL << pmpcfg_shift);
|
||||
pmpcfg = (csr_read_num(pmpcfg_csr) & cfgmask);
|
||||
pmpcfg |= ((prot << pmpcfg_shift) & ~cfgmask);
|
||||
|
||||
@@ -249,16 +239,16 @@ int pmp_set(unsigned int n, unsigned long prot, unsigned long addr,
|
||||
}
|
||||
|
||||
int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
|
||||
unsigned long *log2len_out)
|
||||
unsigned long *log2len)
|
||||
{
|
||||
int pmpcfg_csr, pmpcfg_shift, pmpaddr_csr;
|
||||
unsigned long cfgmask, pmpcfg, prot;
|
||||
unsigned long t1, addr, log2len;
|
||||
unsigned long t1, addr, len;
|
||||
|
||||
/* check parameters */
|
||||
if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len_out)
|
||||
if (n >= PMP_COUNT || !prot_out || !addr_out || !log2len)
|
||||
return SBI_EINVAL;
|
||||
*prot_out = *addr_out = *log2len_out = 0;
|
||||
*prot_out = *addr_out = *log2len = 0;
|
||||
|
||||
/* calculate PMP register and offset */
|
||||
#if __riscv_xlen == 32
|
||||
@@ -276,7 +266,7 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
|
||||
return SBI_ENOTSUPP;
|
||||
|
||||
/* decode PMP config */
|
||||
cfgmask = (0xff << pmpcfg_shift);
|
||||
cfgmask = (0xffUL << pmpcfg_shift);
|
||||
pmpcfg = csr_read_num(pmpcfg_csr) & cfgmask;
|
||||
prot = pmpcfg >> pmpcfg_shift;
|
||||
|
||||
@@ -285,21 +275,21 @@ int pmp_get(unsigned int n, unsigned long *prot_out, unsigned long *addr_out,
|
||||
addr = csr_read_num(pmpaddr_csr);
|
||||
if (addr == -1UL) {
|
||||
addr = 0;
|
||||
log2len = __riscv_xlen;
|
||||
len = __riscv_xlen;
|
||||
} else {
|
||||
t1 = ctz(~addr);
|
||||
addr = (addr & ~((1UL << t1) - 1)) << PMP_SHIFT;
|
||||
log2len = (t1 + PMP_SHIFT + 1);
|
||||
len = (t1 + PMP_SHIFT + 1);
|
||||
}
|
||||
} else {
|
||||
addr = csr_read_num(pmpaddr_csr) << PMP_SHIFT;
|
||||
log2len = PMP_SHIFT;
|
||||
len = PMP_SHIFT;
|
||||
}
|
||||
|
||||
/* return details */
|
||||
*prot_out = prot;
|
||||
*addr_out = addr;
|
||||
*log2len_out = log2len;
|
||||
*log2len = len;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@@ -7,11 +7,10 @@
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/sbi_types.h>
|
||||
#include <sbi/sbi_bitops.h>
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/riscv_atomic.h>
|
||||
#include <sbi/riscv_barrier.h>
|
||||
#include <sbi/sbi_bits.h>
|
||||
|
||||
long atomic_read(atomic_t *atom)
|
||||
{
|
||||
@@ -50,7 +49,7 @@ long atomic_sub_return(atomic_t *atom, long value)
|
||||
return ret - value;
|
||||
}
|
||||
|
||||
#define __axchg(ptr, new, size) \
|
||||
#define __axchg(ptr, new, size) \
|
||||
({ \
|
||||
__typeof__(ptr) __ptr = (ptr); \
|
||||
__typeof__(new) __new = (new); \
|
||||
@@ -71,12 +70,12 @@ long atomic_sub_return(atomic_t *atom, long value)
|
||||
: "memory"); \
|
||||
break; \
|
||||
default: \
|
||||
break; \
|
||||
break; \
|
||||
} \
|
||||
__ret; \
|
||||
})
|
||||
|
||||
#define axchg(ptr, x) \
|
||||
#define axchg(ptr, x) \
|
||||
({ \
|
||||
__typeof__(*(ptr)) _x_ = (x); \
|
||||
(__typeof__(*(ptr))) __axchg((ptr), _x_, sizeof(*(ptr))); \
|
||||
@@ -91,20 +90,20 @@ long atomic_sub_return(atomic_t *atom, long value)
|
||||
register unsigned int __rc; \
|
||||
switch (size) { \
|
||||
case 4: \
|
||||
__asm__ __volatile__("0: lr.w %0, %2\n" \
|
||||
" sc.w.rl %1, %z3, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
__asm__ __volatile__("0: lr.w %0, %2\n" \
|
||||
" sc.w.rl %1, %z3, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
: "=&r"(__ret), "=&r"(__rc), \
|
||||
"+A"(*__ptr) \
|
||||
: "rJ"(__new) \
|
||||
: "memory"); \
|
||||
break; \
|
||||
case 8: \
|
||||
__asm__ __volatile__("0: lr.d %0, %2\n" \
|
||||
" sc.d.rl %1, %z3, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
__asm__ __volatile__("0: lr.d %0, %2\n" \
|
||||
" sc.d.rl %1, %z3, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
: "=&r"(__ret), "=&r"(__rc), \
|
||||
"+A"(*__ptr) \
|
||||
: "rJ"(__new) \
|
||||
@@ -131,11 +130,11 @@ long atomic_sub_return(atomic_t *atom, long value)
|
||||
register unsigned int __rc; \
|
||||
switch (size) { \
|
||||
case 4: \
|
||||
__asm__ __volatile__("0: lr.w %0, %2\n" \
|
||||
" bne %0, %z3, 1f\n" \
|
||||
" sc.w.rl %1, %z4, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
__asm__ __volatile__("0: lr.w %0, %2\n" \
|
||||
" bne %0, %z3, 1f\n" \
|
||||
" sc.w.rl %1, %z4, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
"1:\n" \
|
||||
: "=&r"(__ret), "=&r"(__rc), \
|
||||
"+A"(*__ptr) \
|
||||
@@ -143,11 +142,11 @@ long atomic_sub_return(atomic_t *atom, long value)
|
||||
: "memory"); \
|
||||
break; \
|
||||
case 8: \
|
||||
__asm__ __volatile__("0: lr.d %0, %2\n" \
|
||||
" bne %0, %z3, 1f\n" \
|
||||
" sc.d.rl %1, %z4, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
__asm__ __volatile__("0: lr.d %0, %2\n" \
|
||||
" bne %0, %z3, 1f\n" \
|
||||
" sc.d.rl %1, %z4, %2\n" \
|
||||
" bnez %1, 0b\n" \
|
||||
" fence rw, rw\n" \
|
||||
"1:\n" \
|
||||
: "=&r"(__ret), "=&r"(__rc), \
|
||||
"+A"(*__ptr) \
|
||||
@@ -168,7 +167,7 @@ long atomic_sub_return(atomic_t *atom, long value)
|
||||
__cmpxchg((ptr), _o_, _n_, sizeof(*(ptr))); \
|
||||
})
|
||||
|
||||
long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
|
||||
long atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
|
||||
{
|
||||
#ifdef __riscv_atomic
|
||||
return __sync_val_compare_and_swap(&atom->counter, oldval, newval);
|
||||
@@ -177,7 +176,7 @@ long arch_atomic_cmpxchg(atomic_t *atom, long oldval, long newval)
|
||||
#endif
|
||||
}
|
||||
|
||||
long arch_atomic_xchg(atomic_t *atom, long newval)
|
||||
long atomic_xchg(atomic_t *atom, long newval)
|
||||
{
|
||||
/* Atomically set new value and return old value. */
|
||||
#ifdef __riscv_atomic
|
||||
@@ -209,12 +208,12 @@ unsigned long atomic_raw_xchg_ulong(volatile unsigned long *ptr,
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (BITS_PER_LONG == 64)
|
||||
#if (__SIZEOF_POINTER__ == 8)
|
||||
#define __AMO(op) "amo" #op ".d"
|
||||
#elif (BITS_PER_LONG == 32)
|
||||
#elif (__SIZEOF_POINTER__ == 4)
|
||||
#define __AMO(op) "amo" #op ".w"
|
||||
#else
|
||||
#error "Unexpected BITS_PER_LONG"
|
||||
#error "Unexpected __SIZEOF_POINTER__"
|
||||
#endif
|
||||
|
||||
#define __atomic_op_bit_ord(op, mod, nr, addr, ord) \
|
||||
|
40
lib/sbi/sbi_bitmap.c
Normal file
40
lib/sbi/sbi_bitmap.c
Normal file
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/sbi_bitmap.h>
|
||||
|
||||
void __bitmap_and(unsigned long *dst, const unsigned long *bitmap1,
|
||||
const unsigned long *bitmap2, int bits)
|
||||
{
|
||||
int k;
|
||||
int nr = BITS_TO_LONGS(bits);
|
||||
|
||||
for (k = 0; k < nr; k++)
|
||||
dst[k] = bitmap1[k] & bitmap2[k];
|
||||
}
|
||||
|
||||
void __bitmap_or(unsigned long *dst, const unsigned long *bitmap1,
|
||||
const unsigned long *bitmap2, int bits)
|
||||
{
|
||||
int k;
|
||||
int nr = BITS_TO_LONGS(bits);
|
||||
|
||||
for (k = 0; k < nr; k++)
|
||||
dst[k] = bitmap1[k] | bitmap2[k];
|
||||
}
|
||||
|
||||
void __bitmap_xor(unsigned long *dst, const unsigned long *bitmap1,
|
||||
const unsigned long *bitmap2, int bits)
|
||||
{
|
||||
int k;
|
||||
int nr = BITS_TO_LONGS(bits);
|
||||
|
||||
for (k = 0; k < nr; k++)
|
||||
dst[k] = bitmap1[k] ^ bitmap2[k];
|
||||
}
|
200
lib/sbi/sbi_bitops.c
Normal file
200
lib/sbi/sbi_bitops.c
Normal file
@@ -0,0 +1,200 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/sbi_bitops.h>
|
||||
|
||||
#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
|
||||
|
||||
/**
|
||||
* find_first_bit - find the first set bit in a memory region
|
||||
* @addr: The address to start the search at
|
||||
* @size: The maximum size to search
|
||||
*
|
||||
* Returns the bit number of the first set bit.
|
||||
*/
|
||||
unsigned long find_first_bit(const unsigned long *addr,
|
||||
unsigned long size)
|
||||
{
|
||||
const unsigned long *p = addr;
|
||||
unsigned long result = 0;
|
||||
unsigned long tmp;
|
||||
|
||||
while (size & ~(BITS_PER_LONG-1)) {
|
||||
if ((tmp = *(p++)))
|
||||
goto found;
|
||||
result += BITS_PER_LONG;
|
||||
size -= BITS_PER_LONG;
|
||||
}
|
||||
if (!size)
|
||||
return result;
|
||||
|
||||
tmp = (*p) & (~0UL >> (BITS_PER_LONG - size));
|
||||
if (tmp == 0UL) /* Are any bits set? */
|
||||
return result + size; /* Nope. */
|
||||
found:
|
||||
return result + __ffs(tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* find_first_zero_bit - find the first cleared bit in a memory region
|
||||
* @addr: The address to start the search at
|
||||
* @size: The maximum size to search
|
||||
*
|
||||
* Returns the bit number of the first cleared bit.
|
||||
*/
|
||||
unsigned long find_first_zero_bit(const unsigned long *addr,
|
||||
unsigned long size)
|
||||
{
|
||||
const unsigned long *p = addr;
|
||||
unsigned long result = 0;
|
||||
unsigned long tmp;
|
||||
|
||||
while (size & ~(BITS_PER_LONG-1)) {
|
||||
if (~(tmp = *(p++)))
|
||||
goto found;
|
||||
result += BITS_PER_LONG;
|
||||
size -= BITS_PER_LONG;
|
||||
}
|
||||
if (!size)
|
||||
return result;
|
||||
|
||||
tmp = (*p) | (~0UL << size);
|
||||
if (tmp == ~0UL) /* Are any bits zero? */
|
||||
return result + size; /* Nope. */
|
||||
found:
|
||||
return result + ffz(tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* find_last_bit - find the last set bit in a memory region
|
||||
* @addr: The address to start the search at
|
||||
* @size: The maximum size to search
|
||||
*
|
||||
* Returns the bit number of the first set bit, or size.
|
||||
*/
|
||||
unsigned long find_last_bit(const unsigned long *addr,
|
||||
unsigned long size)
|
||||
{
|
||||
unsigned long words;
|
||||
unsigned long tmp;
|
||||
|
||||
/* Start at final word. */
|
||||
words = size / BITS_PER_LONG;
|
||||
|
||||
/* Partial final word? */
|
||||
if (size & (BITS_PER_LONG-1)) {
|
||||
tmp = (addr[words] & (~0UL >> (BITS_PER_LONG
|
||||
- (size & (BITS_PER_LONG-1)))));
|
||||
if (tmp)
|
||||
goto found;
|
||||
}
|
||||
|
||||
while (words) {
|
||||
tmp = addr[--words];
|
||||
if (tmp) {
|
||||
found:
|
||||
return words * BITS_PER_LONG + __fls(tmp);
|
||||
}
|
||||
}
|
||||
|
||||
/* Not found */
|
||||
return size;
|
||||
}
|
||||
|
||||
/**
|
||||
* find_next_bit - find the next set bit in a memory region
|
||||
* @addr: The address to base the search on
|
||||
* @offset: The bitnumber to start searching at
|
||||
* @size: The bitmap size in bits
|
||||
*/
|
||||
unsigned long find_next_bit(const unsigned long *addr,
|
||||
unsigned long size, unsigned long offset)
|
||||
{
|
||||
const unsigned long *p = addr + BITOP_WORD(offset);
|
||||
unsigned long result = offset & ~(BITS_PER_LONG-1);
|
||||
unsigned long tmp;
|
||||
|
||||
if (offset >= size)
|
||||
return size;
|
||||
size -= result;
|
||||
offset %= BITS_PER_LONG;
|
||||
if (offset) {
|
||||
tmp = *(p++);
|
||||
tmp &= (~0UL << offset);
|
||||
if (size < BITS_PER_LONG)
|
||||
goto found_first;
|
||||
if (tmp)
|
||||
goto found_middle;
|
||||
size -= BITS_PER_LONG;
|
||||
result += BITS_PER_LONG;
|
||||
}
|
||||
while (size & ~(BITS_PER_LONG-1)) {
|
||||
if ((tmp = *(p++)))
|
||||
goto found_middle;
|
||||
result += BITS_PER_LONG;
|
||||
size -= BITS_PER_LONG;
|
||||
}
|
||||
if (!size)
|
||||
return result;
|
||||
tmp = *p;
|
||||
|
||||
found_first:
|
||||
tmp &= (~0UL >> (BITS_PER_LONG - size));
|
||||
if (tmp == 0UL) /* Are any bits set? */
|
||||
return result + size; /* Nope. */
|
||||
found_middle:
|
||||
return result + __ffs(tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* find_next_zero_bit - find the next cleared bit in a memory region
|
||||
* @addr: The address to base the search on
|
||||
* @offset: The bitnumber to start searching at
|
||||
* @size: The bitmap size in bits
|
||||
*/
|
||||
unsigned long find_next_zero_bit(const unsigned long *addr,
|
||||
unsigned long size,
|
||||
unsigned long offset)
|
||||
{
|
||||
const unsigned long *p = addr + BITOP_WORD(offset);
|
||||
unsigned long result = offset & ~(BITS_PER_LONG-1);
|
||||
unsigned long tmp;
|
||||
|
||||
if (offset >= size)
|
||||
return size;
|
||||
size -= result;
|
||||
offset %= BITS_PER_LONG;
|
||||
if (offset) {
|
||||
tmp = *(p++);
|
||||
tmp |= ~0UL >> (BITS_PER_LONG - offset);
|
||||
if (size < BITS_PER_LONG)
|
||||
goto found_first;
|
||||
if (~tmp)
|
||||
goto found_middle;
|
||||
size -= BITS_PER_LONG;
|
||||
result += BITS_PER_LONG;
|
||||
}
|
||||
while (size & ~(BITS_PER_LONG-1)) {
|
||||
if (~(tmp = *(p++)))
|
||||
goto found_middle;
|
||||
result += BITS_PER_LONG;
|
||||
size -= BITS_PER_LONG;
|
||||
}
|
||||
if (!size)
|
||||
return result;
|
||||
tmp = *p;
|
||||
|
||||
found_first:
|
||||
tmp |= ~0UL << size;
|
||||
if (tmp == ~0UL) /* Are any bits zero? */
|
||||
return result + size; /* Nope. */
|
||||
found_middle:
|
||||
return result + ffz(tmp);
|
||||
}
|
@@ -7,9 +7,10 @@
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/riscv_locks.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_scratch.h>
|
||||
|
||||
static const struct sbi_platform *console_plat = NULL;
|
||||
static spinlock_t console_out_lock = SPIN_LOCK_INITIALIZER;
|
||||
@@ -375,10 +376,11 @@ int sbi_printf(const char *format, ...)
|
||||
return retval;
|
||||
}
|
||||
|
||||
int sbi_dprintf(struct sbi_scratch *scratch, const char *format, ...)
|
||||
int sbi_dprintf(const char *format, ...)
|
||||
{
|
||||
va_list args;
|
||||
int retval = 0;
|
||||
struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
|
||||
|
||||
va_start(args, format);
|
||||
if (scratch->options & SBI_SCRATCH_DEBUG_PRINTS)
|
||||
|
539
lib/sbi/sbi_domain.c
Normal file
539
lib/sbi/sbi_domain.c
Normal file
@@ -0,0 +1,539 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_hartmask.h>
|
||||
#include <sbi/sbi_hsm.h>
|
||||
#include <sbi/sbi_math.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_scratch.h>
|
||||
#include <sbi/sbi_string.h>
|
||||
|
||||
struct sbi_domain *hartid_to_domain_table[SBI_HARTMASK_MAX_BITS] = { 0 };
|
||||
struct sbi_domain *domidx_to_domain_table[SBI_DOMAIN_MAX_INDEX] = { 0 };
|
||||
|
||||
static u32 domain_count = 0;
|
||||
|
||||
static struct sbi_hartmask root_hmask = { 0 };
|
||||
|
||||
#define ROOT_FW_REGION 0
|
||||
#define ROOT_ALL_REGION 1
|
||||
#define ROOT_END_REGION 2
|
||||
static struct sbi_domain_memregion root_memregs[ROOT_END_REGION + 1] = { 0 };
|
||||
|
||||
static struct sbi_domain root = {
|
||||
.name = "root",
|
||||
.possible_harts = &root_hmask,
|
||||
.regions = root_memregs,
|
||||
.system_reset_allowed = TRUE,
|
||||
};
|
||||
|
||||
bool sbi_domain_is_assigned_hart(const struct sbi_domain *dom, u32 hartid)
|
||||
{
|
||||
if (dom)
|
||||
return sbi_hartmask_test_hart(hartid, &dom->assigned_harts);
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
ulong sbi_domain_get_assigned_hartmask(const struct sbi_domain *dom,
|
||||
ulong hbase)
|
||||
{
|
||||
ulong ret, bword, boff;
|
||||
|
||||
if (!dom)
|
||||
return 0;
|
||||
|
||||
bword = BIT_WORD(hbase);
|
||||
boff = BIT_WORD_OFFSET(hbase);
|
||||
|
||||
ret = sbi_hartmask_bits(&dom->assigned_harts)[bword++] >> boff;
|
||||
if (boff && bword < BIT_WORD(SBI_HARTMASK_MAX_BITS)) {
|
||||
ret |= (sbi_hartmask_bits(&dom->assigned_harts)[bword] &
|
||||
(BIT(boff) - 1UL)) << (BITS_PER_LONG - boff);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void sbi_domain_memregion_initfw(struct sbi_domain_memregion *reg)
|
||||
{
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
sbi_memcpy(reg, &root_memregs[ROOT_FW_REGION], sizeof(*reg));
|
||||
}
|
||||
|
||||
bool sbi_domain_check_addr(const struct sbi_domain *dom,
|
||||
unsigned long addr, unsigned long mode,
|
||||
unsigned long access_flags)
|
||||
{
|
||||
bool mmio = FALSE;
|
||||
struct sbi_domain_memregion *reg;
|
||||
unsigned long rstart, rend, rflags, rwx = 0;
|
||||
|
||||
if (!dom)
|
||||
return FALSE;
|
||||
|
||||
if (access_flags & SBI_DOMAIN_READ)
|
||||
rwx |= SBI_DOMAIN_MEMREGION_READABLE;
|
||||
if (access_flags & SBI_DOMAIN_WRITE)
|
||||
rwx |= SBI_DOMAIN_MEMREGION_WRITEABLE;
|
||||
if (access_flags & SBI_DOMAIN_EXECUTE)
|
||||
rwx |= SBI_DOMAIN_MEMREGION_EXECUTABLE;
|
||||
if (access_flags & SBI_DOMAIN_MMIO)
|
||||
mmio = TRUE;
|
||||
|
||||
sbi_domain_for_each_memregion(dom, reg) {
|
||||
rflags = reg->flags;
|
||||
if (mode == PRV_M && !(rflags & SBI_DOMAIN_MEMREGION_MMODE))
|
||||
continue;
|
||||
|
||||
rstart = reg->base;
|
||||
rend = (reg->order < __riscv_xlen) ?
|
||||
rstart + ((1UL << reg->order) - 1) : -1UL;
|
||||
if (rstart <= addr && addr <= rend) {
|
||||
if ((mmio && !(rflags & SBI_DOMAIN_MEMREGION_MMIO)) ||
|
||||
(!mmio && (rflags & SBI_DOMAIN_MEMREGION_MMIO)))
|
||||
return FALSE;
|
||||
return ((rflags & rwx) == rwx) ? TRUE : FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
return (mode == PRV_M) ? TRUE : FALSE;
|
||||
}
|
||||
|
||||
/* Check if region complies with constraints */
|
||||
static bool is_region_valid(const struct sbi_domain_memregion *reg)
|
||||
{
|
||||
if (reg->order < 3 || __riscv_xlen < reg->order)
|
||||
return FALSE;
|
||||
|
||||
if (reg->base & (BIT(reg->order) - 1))
|
||||
return FALSE;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/** Check if regionA is sub-region of regionB */
|
||||
static bool is_region_subset(const struct sbi_domain_memregion *regA,
|
||||
const struct sbi_domain_memregion *regB)
|
||||
{
|
||||
ulong regA_start = regA->base;
|
||||
ulong regA_end = regA->base + (BIT(regA->order) - 1);
|
||||
ulong regB_start = regB->base;
|
||||
ulong regB_end = regB->base + (BIT(regA->order) - 1);
|
||||
|
||||
if ((regB_start <= regA_start) &&
|
||||
(regA_start < regB_end) &&
|
||||
(regB_start < regA_end) &&
|
||||
(regA_end <= regB_end))
|
||||
return TRUE;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/** Check if regionA conflicts regionB */
|
||||
static bool is_region_conflict(const struct sbi_domain_memregion *regA,
|
||||
const struct sbi_domain_memregion *regB)
|
||||
{
|
||||
if ((is_region_subset(regA, regB) || is_region_subset(regB, regA)) &&
|
||||
regA->flags == regB->flags)
|
||||
return TRUE;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/** Check if regionA should be placed before regionB */
|
||||
static bool is_region_before(const struct sbi_domain_memregion *regA,
|
||||
const struct sbi_domain_memregion *regB)
|
||||
{
|
||||
if (regA->order < regB->order)
|
||||
return TRUE;
|
||||
|
||||
if ((regA->order == regB->order) &&
|
||||
(regA->base < regB->base))
|
||||
return TRUE;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
static int sanitize_domain(const struct sbi_platform *plat,
|
||||
struct sbi_domain *dom)
|
||||
{
|
||||
u32 i, j, count;
|
||||
bool have_fw_reg;
|
||||
struct sbi_domain_memregion treg, *reg, *reg1;
|
||||
|
||||
/* Check possible HARTs */
|
||||
if (!dom->possible_harts) {
|
||||
sbi_printf("%s: %s possible HART mask is NULL\n",
|
||||
__func__, dom->name);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
sbi_hartmask_for_each_hart(i, dom->possible_harts) {
|
||||
if (sbi_platform_hart_invalid(plat, i)) {
|
||||
sbi_printf("%s: %s possible HART mask has invalid "
|
||||
"hart %d\n", __func__, dom->name, i);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
};
|
||||
|
||||
/* Check memory regions */
|
||||
if (!dom->regions) {
|
||||
sbi_printf("%s: %s regions is NULL\n",
|
||||
__func__, dom->name);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
sbi_domain_for_each_memregion(dom, reg) {
|
||||
if (!is_region_valid(reg)) {
|
||||
sbi_printf("%s: %s has invalid region base=0x%lx "
|
||||
"order=%lu flags=0x%lx\n", __func__,
|
||||
dom->name, reg->base, reg->order,
|
||||
reg->flags);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
/* Count memory regions and check presence of firmware region */
|
||||
count = 0;
|
||||
have_fw_reg = FALSE;
|
||||
sbi_domain_for_each_memregion(dom, reg) {
|
||||
if (reg->order == root_memregs[ROOT_FW_REGION].order &&
|
||||
reg->base == root_memregs[ROOT_FW_REGION].base &&
|
||||
reg->flags == root_memregs[ROOT_FW_REGION].flags)
|
||||
have_fw_reg = TRUE;
|
||||
count++;
|
||||
}
|
||||
if (!have_fw_reg) {
|
||||
sbi_printf("%s: %s does not have firmware region\n",
|
||||
__func__, dom->name);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
|
||||
/* Sort the memory regions */
|
||||
for (i = 0; i < (count - 1); i++) {
|
||||
reg = &dom->regions[i];
|
||||
for (j = i + 1; j < count; j++) {
|
||||
reg1 = &dom->regions[j];
|
||||
|
||||
if (is_region_conflict(reg1, reg)) {
|
||||
sbi_printf("%s: %s conflict between regions "
|
||||
"(base=0x%lx order=%lu flags=0x%lx) and "
|
||||
"(base=0x%lx order=%lu flags=0x%lx)\n",
|
||||
__func__, dom->name,
|
||||
reg->base, reg->order, reg->flags,
|
||||
reg1->base, reg1->order, reg1->flags);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
|
||||
if (!is_region_before(reg1, reg))
|
||||
continue;
|
||||
|
||||
sbi_memcpy(&treg, reg1, sizeof(treg));
|
||||
sbi_memcpy(reg1, reg, sizeof(treg));
|
||||
sbi_memcpy(reg, &treg, sizeof(treg));
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* We don't need to check boot HART id of domain because if boot
|
||||
* HART id is not possible/assigned to this domain then it won't
|
||||
* be started at boot-time by sbi_domain_finalize().
|
||||
*/
|
||||
|
||||
/*
|
||||
* Check next mode
|
||||
*
|
||||
* We only allow next mode to be S-mode or U-mode.so that we can
|
||||
* protect M-mode context and enforce checks on memory accesses.
|
||||
*/
|
||||
if (dom->next_mode != PRV_S &&
|
||||
dom->next_mode != PRV_U) {
|
||||
sbi_printf("%s: %s invalid next booting stage mode 0x%lx\n",
|
||||
__func__, dom->name, dom->next_mode);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
|
||||
/* Check next address and next mode*/
|
||||
if (!sbi_domain_check_addr(dom, dom->next_addr, dom->next_mode,
|
||||
SBI_DOMAIN_EXECUTE)) {
|
||||
sbi_printf("%s: %s next booting stage addres 0x%lx can't "
|
||||
"execute\n", __func__, dom->name, dom->next_addr);
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sbi_domain_dump(const struct sbi_domain *dom, const char *suffix)
|
||||
{
|
||||
u32 i, k;
|
||||
unsigned long rstart, rend;
|
||||
struct sbi_domain_memregion *reg;
|
||||
|
||||
sbi_printf("Domain%d Name %s: %s\n",
|
||||
dom->index, suffix, dom->name);
|
||||
|
||||
sbi_printf("Domain%d Boot HART %s: %d\n",
|
||||
dom->index, suffix, dom->boot_hartid);
|
||||
|
||||
k = 0;
|
||||
sbi_printf("Domain%d HARTs %s: ", dom->index, suffix);
|
||||
sbi_hartmask_for_each_hart(i, dom->possible_harts)
|
||||
sbi_printf("%s%d%s", (k++) ? "," : "",
|
||||
i, sbi_domain_is_assigned_hart(dom, i) ? "*" : "");
|
||||
sbi_printf("\n");
|
||||
|
||||
i = 0;
|
||||
sbi_domain_for_each_memregion(dom, reg) {
|
||||
rstart = reg->base;
|
||||
rend = (reg->order < __riscv_xlen) ?
|
||||
rstart + ((1UL << reg->order) - 1) : -1UL;
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
sbi_printf("Domain%d Region%02d %s: 0x%08lx-0x%08lx ",
|
||||
#else
|
||||
sbi_printf("Domain%d Region%02d %s: 0x%016lx-0x%016lx ",
|
||||
#endif
|
||||
dom->index, i, suffix, rstart, rend);
|
||||
|
||||
k = 0;
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_MMODE)
|
||||
sbi_printf("%cM", (k++) ? ',' : '(');
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_MMIO)
|
||||
sbi_printf("%cI", (k++) ? ',' : '(');
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_READABLE)
|
||||
sbi_printf("%cR", (k++) ? ',' : '(');
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_WRITEABLE)
|
||||
sbi_printf("%cW", (k++) ? ',' : '(');
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_EXECUTABLE)
|
||||
sbi_printf("%cX", (k++) ? ',' : '(');
|
||||
sbi_printf("%s\n", (k++) ? ")" : "()");
|
||||
|
||||
i++;
|
||||
}
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
sbi_printf("Domain%d Next Address%s: 0x%08lx\n",
|
||||
#else
|
||||
sbi_printf("Domain%d Next Address%s: 0x%016lx\n",
|
||||
#endif
|
||||
dom->index, suffix, dom->next_addr);
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
sbi_printf("Domain%d Next Arg1 %s: 0x%08lx\n",
|
||||
#else
|
||||
sbi_printf("Domain%d Next Arg1 %s: 0x%016lx\n",
|
||||
#endif
|
||||
dom->index, suffix, dom->next_arg1);
|
||||
|
||||
sbi_printf("Domain%d Next Mode %s: ", dom->index, suffix);
|
||||
switch (dom->next_mode) {
|
||||
case PRV_M:
|
||||
sbi_printf("M-mode\n");
|
||||
break;
|
||||
case PRV_S:
|
||||
sbi_printf("S-mode\n");
|
||||
break;
|
||||
case PRV_U:
|
||||
sbi_printf("U-mode\n");
|
||||
break;
|
||||
default:
|
||||
sbi_printf("Unknown\n");
|
||||
break;
|
||||
};
|
||||
|
||||
sbi_printf("Domain%d SysReset %s: %s\n",
|
||||
dom->index, suffix, (dom->system_reset_allowed) ? "yes" : "no");
|
||||
}
|
||||
|
||||
void sbi_domain_dump_all(const char *suffix)
|
||||
{
|
||||
u32 i;
|
||||
const struct sbi_domain *dom;
|
||||
|
||||
sbi_domain_for_each(i, dom) {
|
||||
sbi_domain_dump(dom, suffix);
|
||||
sbi_printf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
int sbi_domain_register(struct sbi_domain *dom,
|
||||
const struct sbi_hartmask *assign_mask)
|
||||
{
|
||||
u32 i;
|
||||
int rc;
|
||||
struct sbi_domain *tdom;
|
||||
u32 cold_hartid = current_hartid();
|
||||
const struct sbi_platform *plat = sbi_platform_thishart_ptr();
|
||||
|
||||
if (!dom || !assign_mask)
|
||||
return SBI_EINVAL;
|
||||
|
||||
/* Check if domain already discovered */
|
||||
sbi_domain_for_each(i, tdom) {
|
||||
if (tdom == dom)
|
||||
return SBI_EALREADY;
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that we have room for Domain Index to
|
||||
* HART ID mapping
|
||||
*/
|
||||
if (SBI_DOMAIN_MAX_INDEX <= domain_count) {
|
||||
sbi_printf("%s: No room for %s\n",
|
||||
__func__, dom->name);
|
||||
return SBI_ENOSPC;
|
||||
}
|
||||
|
||||
/* Sanitize discovered domain */
|
||||
rc = sanitize_domain(plat, dom);
|
||||
if (rc) {
|
||||
sbi_printf("%s: sanity checks failed for"
|
||||
" %s (error %d)\n", __func__,
|
||||
dom->name, rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Assign index to domain */
|
||||
dom->index = domain_count++;
|
||||
domidx_to_domain_table[dom->index] = dom;
|
||||
|
||||
/* Clear assigned HARTs of domain */
|
||||
sbi_hartmask_clear_all(&dom->assigned_harts);
|
||||
|
||||
/* Assign domain to HART if HART is a possible HART */
|
||||
sbi_hartmask_for_each_hart(i, assign_mask) {
|
||||
if (!sbi_hartmask_test_hart(i, dom->possible_harts))
|
||||
continue;
|
||||
|
||||
tdom = hartid_to_domain_table[i];
|
||||
if (tdom)
|
||||
sbi_hartmask_clear_hart(i,
|
||||
&tdom->assigned_harts);
|
||||
hartid_to_domain_table[i] = dom;
|
||||
sbi_hartmask_set_hart(i, &dom->assigned_harts);
|
||||
|
||||
/*
|
||||
* If cold boot HART is assigned to this domain then
|
||||
* override boot HART of this domain.
|
||||
*/
|
||||
if (i == cold_hartid &&
|
||||
dom->boot_hartid != cold_hartid) {
|
||||
sbi_printf("Domain%d Boot HARTID forced to"
|
||||
" %d\n", dom->index, cold_hartid);
|
||||
dom->boot_hartid = cold_hartid;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sbi_domain_finalize(struct sbi_scratch *scratch, u32 cold_hartid)
|
||||
{
|
||||
int rc;
|
||||
u32 i, dhart;
|
||||
struct sbi_domain *dom;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
/* Initialize and populate domains for the platform */
|
||||
rc = sbi_platform_domains_init(plat);
|
||||
if (rc) {
|
||||
sbi_printf("%s: platform domains_init() failed (error %d)\n",
|
||||
__func__, rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* Startup boot HART of domains */
|
||||
sbi_domain_for_each(i, dom) {
|
||||
/* Domain boot HART */
|
||||
dhart = dom->boot_hartid;
|
||||
|
||||
/* Ignore of boot HART is off limits */
|
||||
if (SBI_HARTMASK_MAX_BITS <= dhart)
|
||||
continue;
|
||||
|
||||
/* Ignore if boot HART not possible for this domain */
|
||||
if (!sbi_hartmask_test_hart(dhart, dom->possible_harts))
|
||||
continue;
|
||||
|
||||
/* Ignore if boot HART assigned different domain */
|
||||
if (sbi_hartid_to_domain(dhart) != dom ||
|
||||
!sbi_hartmask_test_hart(dhart, &dom->assigned_harts))
|
||||
continue;
|
||||
|
||||
/* Startup boot HART of domain */
|
||||
if (dhart == cold_hartid) {
|
||||
scratch->next_addr = dom->next_addr;
|
||||
scratch->next_mode = dom->next_mode;
|
||||
scratch->next_arg1 = dom->next_arg1;
|
||||
} else {
|
||||
rc = sbi_hsm_hart_start(scratch, NULL, dhart,
|
||||
dom->next_addr,
|
||||
dom->next_mode,
|
||||
dom->next_arg1);
|
||||
if (rc) {
|
||||
sbi_printf("%s: failed to start boot HART %d"
|
||||
" for %s (error %d)\n", __func__,
|
||||
dhart, dom->name, rc);
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sbi_domain_init(struct sbi_scratch *scratch, u32 cold_hartid)
|
||||
{
|
||||
u32 i;
|
||||
struct sbi_domain_memregion *memregs;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
/* Root domain firmware memory region */
|
||||
root_memregs[ROOT_FW_REGION].order = log2roundup(scratch->fw_size);
|
||||
root_memregs[ROOT_FW_REGION].base = scratch->fw_start &
|
||||
~((1UL << root_memregs[0].order) - 1UL);
|
||||
root_memregs[ROOT_FW_REGION].flags = 0;
|
||||
|
||||
/* Root domain allow everything memory region */
|
||||
root_memregs[ROOT_ALL_REGION].order = __riscv_xlen;
|
||||
root_memregs[ROOT_ALL_REGION].base = 0;
|
||||
root_memregs[ROOT_ALL_REGION].flags = (SBI_DOMAIN_MEMREGION_READABLE |
|
||||
SBI_DOMAIN_MEMREGION_WRITEABLE |
|
||||
SBI_DOMAIN_MEMREGION_EXECUTABLE);
|
||||
|
||||
/* Root domain memory region end */
|
||||
root_memregs[ROOT_END_REGION].order = 0;
|
||||
|
||||
/* Use platform specific root memory regions when available */
|
||||
memregs = sbi_platform_domains_root_regions(plat);
|
||||
if (memregs)
|
||||
root.regions = memregs;
|
||||
|
||||
/* Root domain boot HART id is same as coldboot HART id */
|
||||
root.boot_hartid = cold_hartid;
|
||||
|
||||
/* Root domain next booting stage details */
|
||||
root.next_arg1 = scratch->next_arg1;
|
||||
root.next_addr = scratch->next_addr;
|
||||
root.next_mode = scratch->next_mode;
|
||||
|
||||
/* Root domain possible and assigned HARTs */
|
||||
for (i = 0; i < SBI_HARTMASK_MAX_BITS; i++) {
|
||||
if (sbi_platform_hart_invalid(plat, i))
|
||||
continue;
|
||||
sbi_hartmask_set_hart(i, &root_hmask);
|
||||
}
|
||||
|
||||
return sbi_domain_register(&root, &root_hmask);
|
||||
}
|
@@ -7,6 +7,7 @@
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_ecall.h>
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
@@ -22,6 +23,18 @@ u16 sbi_ecall_version_minor(void)
|
||||
return SBI_ECALL_VERSION_MINOR;
|
||||
}
|
||||
|
||||
static unsigned long ecall_impid = SBI_OPENSBI_IMPID;
|
||||
|
||||
unsigned long sbi_ecall_get_impid(void)
|
||||
{
|
||||
return ecall_impid;
|
||||
}
|
||||
|
||||
void sbi_ecall_set_impid(unsigned long impid)
|
||||
{
|
||||
ecall_impid = impid;
|
||||
}
|
||||
|
||||
static SBI_LIST_HEAD(ecall_exts_list);
|
||||
|
||||
struct sbi_ecall_extension *sbi_ecall_find_extension(unsigned long extid)
|
||||
@@ -40,11 +53,19 @@ struct sbi_ecall_extension *sbi_ecall_find_extension(unsigned long extid)
|
||||
|
||||
int sbi_ecall_register_extension(struct sbi_ecall_extension *ext)
|
||||
{
|
||||
struct sbi_ecall_extension *t;
|
||||
|
||||
if (!ext || (ext->extid_end < ext->extid_start) || !ext->handle)
|
||||
return SBI_EINVAL;
|
||||
if (sbi_ecall_find_extension(ext->extid_start) ||
|
||||
sbi_ecall_find_extension(ext->extid_end))
|
||||
return SBI_EINVAL;
|
||||
|
||||
sbi_list_for_each_entry(t, &ecall_exts_list, head) {
|
||||
unsigned long start = t->extid_start;
|
||||
unsigned long end = t->extid_end;
|
||||
if (end < ext->extid_start || ext->extid_end < start)
|
||||
/* no overlap */;
|
||||
else
|
||||
return SBI_EINVAL;
|
||||
}
|
||||
|
||||
SBI_INIT_LIST_HEAD(&ext->head);
|
||||
sbi_list_add_tail(&ext->head, &ecall_exts_list);
|
||||
@@ -71,8 +92,7 @@ void sbi_ecall_unregister_extension(struct sbi_ecall_extension *ext)
|
||||
sbi_list_del_init(&ext->head);
|
||||
}
|
||||
|
||||
int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch)
|
||||
int sbi_ecall_handler(struct sbi_trap_regs *regs)
|
||||
{
|
||||
int ret = 0;
|
||||
struct sbi_ecall_extension *ext;
|
||||
@@ -81,19 +101,11 @@ int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
|
||||
struct sbi_trap_info trap = {0};
|
||||
unsigned long out_val = 0;
|
||||
bool is_0_1_spec = 0;
|
||||
unsigned long args[6];
|
||||
|
||||
args[0] = regs->a0;
|
||||
args[1] = regs->a1;
|
||||
args[2] = regs->a2;
|
||||
args[3] = regs->a3;
|
||||
args[4] = regs->a4;
|
||||
args[5] = regs->a5;
|
||||
|
||||
ext = sbi_ecall_find_extension(extension_id);
|
||||
if (ext && ext->handle) {
|
||||
ret = ext->handle(scratch, extension_id, func_id,
|
||||
args, &out_val, &trap);
|
||||
ret = ext->handle(extension_id, func_id,
|
||||
regs, &out_val, &trap);
|
||||
if (extension_id >= SBI_EXT_0_1_SET_TIMER &&
|
||||
extension_id <= SBI_EXT_0_1_SHUTDOWN)
|
||||
is_0_1_spec = 1;
|
||||
@@ -103,9 +115,17 @@ int sbi_ecall_handler(u32 hartid, ulong mcause, struct sbi_trap_regs *regs,
|
||||
|
||||
if (ret == SBI_ETRAP) {
|
||||
trap.epc = regs->mepc;
|
||||
sbi_trap_redirect(regs, &trap, scratch);
|
||||
sbi_trap_redirect(regs, &trap);
|
||||
} else {
|
||||
/* This function should return non-zero value only in case of
|
||||
if (ret < SBI_LAST_ERR) {
|
||||
sbi_printf("%s: Invalid error %d for ext=0x%lx "
|
||||
"func=0x%lx\n", __func__, ret,
|
||||
extension_id, func_id);
|
||||
ret = SBI_ERR_FAILED;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function should return non-zero value only in case of
|
||||
* fatal error. However, there is no good way to distinguish
|
||||
* between a fatal and non-fatal errors yet. That's why we treat
|
||||
* every return value except ETRAP as non-fatal and just return
|
||||
@@ -136,6 +156,12 @@ int sbi_ecall_init(void)
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = sbi_ecall_register_extension(&ecall_base);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = sbi_ecall_register_extension(&ecall_hsm);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = sbi_ecall_register_extension(&ecall_srst);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = sbi_ecall_register_extension(&ecall_legacy);
|
||||
|
@@ -11,12 +11,11 @@
|
||||
#include <sbi/sbi_ecall.h>
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
#include <sbi/sbi_version.h>
|
||||
#include <sbi/riscv_asm.h>
|
||||
|
||||
static int sbi_ecall_base_probe(struct sbi_scratch *scratch,
|
||||
unsigned long extid,
|
||||
unsigned long *out_val)
|
||||
static int sbi_ecall_base_probe(unsigned long extid, unsigned long *out_val)
|
||||
{
|
||||
struct sbi_ecall_extension *ext;
|
||||
|
||||
@@ -27,15 +26,15 @@ static int sbi_ecall_base_probe(struct sbi_scratch *scratch,
|
||||
}
|
||||
|
||||
if (ext->probe)
|
||||
return ext->probe(scratch, extid, out_val);
|
||||
return ext->probe(extid, out_val);
|
||||
|
||||
*out_val = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sbi_ecall_base_handler(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long funcid,
|
||||
unsigned long *args, unsigned long *out_val,
|
||||
static int sbi_ecall_base_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
int ret = 0;
|
||||
@@ -49,7 +48,7 @@ static int sbi_ecall_base_handler(struct sbi_scratch *scratch,
|
||||
*out_val = *out_val | SBI_ECALL_VERSION_MINOR;
|
||||
break;
|
||||
case SBI_EXT_BASE_GET_IMP_ID:
|
||||
*out_val = SBI_OPENSBI_IMPID;
|
||||
*out_val = sbi_ecall_get_impid();
|
||||
break;
|
||||
case SBI_EXT_BASE_GET_IMP_VERSION:
|
||||
*out_val = OPENSBI_VERSION;
|
||||
@@ -64,7 +63,7 @@ static int sbi_ecall_base_handler(struct sbi_scratch *scratch,
|
||||
*out_val = csr_read(CSR_MIMPID);
|
||||
break;
|
||||
case SBI_EXT_BASE_PROBE_EXT:
|
||||
ret = sbi_ecall_base_probe(scratch, args[0], out_val);
|
||||
ret = sbi_ecall_base_probe(regs->a0, out_val);
|
||||
break;
|
||||
default:
|
||||
ret = SBI_ENOTSUPP;
|
||||
|
59
lib/sbi/sbi_ecall_hsm.c
Normal file
59
lib/sbi/sbi_ecall_hsm.c
Normal file
@@ -0,0 +1,59 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_ecall.h>
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
#include <sbi/sbi_version.h>
|
||||
#include <sbi/sbi_hsm.h>
|
||||
#include <sbi/sbi_scratch.h>
|
||||
#include <sbi/riscv_asm.h>
|
||||
|
||||
static int sbi_ecall_hsm_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
ulong smode;
|
||||
int ret = 0, hstate;
|
||||
struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
|
||||
|
||||
switch (funcid) {
|
||||
case SBI_EXT_HSM_HART_START:
|
||||
smode = csr_read(CSR_MSTATUS);
|
||||
smode = (smode & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
|
||||
ret = sbi_hsm_hart_start(scratch, sbi_domain_thishart_ptr(),
|
||||
regs->a0, regs->a1, smode, regs->a2);
|
||||
break;
|
||||
case SBI_EXT_HSM_HART_STOP:
|
||||
ret = sbi_hsm_hart_stop(scratch, TRUE);
|
||||
break;
|
||||
case SBI_EXT_HSM_HART_GET_STATUS:
|
||||
hstate = sbi_hsm_hart_get_state(sbi_domain_thishart_ptr(),
|
||||
regs->a0);
|
||||
ret = sbi_hsm_hart_state_to_status(hstate);
|
||||
break;
|
||||
default:
|
||||
ret = SBI_ENOTSUPP;
|
||||
};
|
||||
if (ret >= 0) {
|
||||
*out_val = ret;
|
||||
ret = 0;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct sbi_ecall_extension ecall_hsm = {
|
||||
.extid_start = SBI_EXT_HSM,
|
||||
.extid_end = SBI_EXT_HSM,
|
||||
.handle = sbi_ecall_hsm_handler,
|
||||
};
|
@@ -8,11 +8,15 @@
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_ecall.h>
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_hsm.h>
|
||||
#include <sbi/sbi_ipi.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_system.h>
|
||||
#include <sbi/sbi_timer.h>
|
||||
#include <sbi/sbi_tlb.h>
|
||||
@@ -20,90 +24,91 @@
|
||||
#include <sbi/sbi_unpriv.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
|
||||
static int sbi_load_hart_mask_unpriv(struct sbi_scratch *scratch,
|
||||
ulong *pmask, ulong *hmask,
|
||||
static int sbi_load_hart_mask_unpriv(ulong *pmask, ulong *hmask,
|
||||
struct sbi_trap_info *uptrap)
|
||||
{
|
||||
ulong mask = 0;
|
||||
|
||||
if (pmask) {
|
||||
mask = sbi_load_ulong(pmask, scratch, uptrap);
|
||||
mask = sbi_load_ulong(pmask, uptrap);
|
||||
if (uptrap->cause)
|
||||
return SBI_ETRAP;
|
||||
} else {
|
||||
mask = sbi_hart_available_mask();
|
||||
sbi_hsm_hart_started_mask(sbi_domain_thishart_ptr(),
|
||||
0, &mask);
|
||||
}
|
||||
*hmask = mask;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sbi_ecall_legacy_handler(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long funcid,
|
||||
unsigned long *args, unsigned long *out_val,
|
||||
static int sbi_ecall_legacy_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
int ret = 0;
|
||||
struct sbi_tlb_info tlb_info;
|
||||
u32 source_hart = sbi_current_hartid();
|
||||
u32 source_hart = current_hartid();
|
||||
ulong hmask = 0;
|
||||
|
||||
switch (extid) {
|
||||
case SBI_EXT_0_1_SET_TIMER:
|
||||
#if __riscv_xlen == 32
|
||||
sbi_timer_event_start(scratch,
|
||||
(((u64)args[1] << 32) | (u64)args[0]));
|
||||
sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
|
||||
#else
|
||||
sbi_timer_event_start(scratch, (u64)args[0]);
|
||||
sbi_timer_event_start((u64)regs->a0);
|
||||
#endif
|
||||
break;
|
||||
case SBI_EXT_0_1_CONSOLE_PUTCHAR:
|
||||
sbi_putc(args[0]);
|
||||
sbi_putc(regs->a0);
|
||||
break;
|
||||
case SBI_EXT_0_1_CONSOLE_GETCHAR:
|
||||
ret = sbi_getc();
|
||||
break;
|
||||
case SBI_EXT_0_1_CLEAR_IPI:
|
||||
sbi_ipi_clear_smode(scratch);
|
||||
sbi_ipi_clear_smode();
|
||||
break;
|
||||
case SBI_EXT_0_1_SEND_IPI:
|
||||
ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
|
||||
ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
|
||||
&hmask, out_trap);
|
||||
if (ret != SBI_ETRAP)
|
||||
ret = sbi_ipi_send_smode(scratch, hmask, 0);
|
||||
ret = sbi_ipi_send_smode(hmask, 0);
|
||||
break;
|
||||
case SBI_EXT_0_1_REMOTE_FENCE_I:
|
||||
tlb_info.start = 0;
|
||||
tlb_info.size = 0;
|
||||
tlb_info.type = SBI_ITLB_FLUSH;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
|
||||
ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
|
||||
&hmask, out_trap);
|
||||
if (ret != SBI_ETRAP)
|
||||
ret = sbi_tlb_request(scratch, hmask, 0, &tlb_info);
|
||||
if (ret != SBI_ETRAP) {
|
||||
SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0, 0,
|
||||
sbi_tlb_local_fence_i,
|
||||
source_hart);
|
||||
ret = sbi_tlb_request(hmask, 0, &tlb_info);
|
||||
}
|
||||
break;
|
||||
case SBI_EXT_0_1_REMOTE_SFENCE_VMA:
|
||||
tlb_info.start = (unsigned long)args[1];
|
||||
tlb_info.size = (unsigned long)args[2];
|
||||
tlb_info.type = SBI_TLB_FLUSH_VMA;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
|
||||
ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
|
||||
&hmask, out_trap);
|
||||
if (ret != SBI_ETRAP)
|
||||
ret = sbi_tlb_request(scratch, hmask, 0, &tlb_info);
|
||||
if (ret != SBI_ETRAP) {
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a1, regs->a2, 0, 0,
|
||||
sbi_tlb_local_sfence_vma,
|
||||
source_hart);
|
||||
ret = sbi_tlb_request(hmask, 0, &tlb_info);
|
||||
}
|
||||
break;
|
||||
case SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID:
|
||||
tlb_info.start = (unsigned long)args[1];
|
||||
tlb_info.size = (unsigned long)args[2];
|
||||
tlb_info.asid = (unsigned long)args[3];
|
||||
tlb_info.type = SBI_TLB_FLUSH_VMA_ASID;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_load_hart_mask_unpriv(scratch, (ulong *)args[0],
|
||||
ret = sbi_load_hart_mask_unpriv((ulong *)regs->a0,
|
||||
&hmask, out_trap);
|
||||
if (ret != SBI_ETRAP)
|
||||
ret = sbi_tlb_request(scratch, hmask, 0, &tlb_info);
|
||||
if (ret != SBI_ETRAP) {
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a1,
|
||||
regs->a2, regs->a3, 0,
|
||||
sbi_tlb_local_sfence_vma_asid,
|
||||
source_hart);
|
||||
ret = sbi_tlb_request(hmask, 0, &tlb_info);
|
||||
}
|
||||
break;
|
||||
case SBI_EXT_0_1_SHUTDOWN:
|
||||
sbi_system_shutdown(scratch, 0);
|
||||
sbi_system_reset(SBI_SRST_RESET_TYPE_SHUTDOWN,
|
||||
SBI_SRST_RESET_REASON_NONE);
|
||||
break;
|
||||
default:
|
||||
ret = SBI_ENOTSUPP;
|
||||
|
@@ -8,28 +8,29 @@
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/sbi_ecall.h>
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_ipi.h>
|
||||
#include <sbi/sbi_system.h>
|
||||
#include <sbi/sbi_timer.h>
|
||||
#include <sbi/sbi_tlb.h>
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
|
||||
static int sbi_ecall_time_handler(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long funcid,
|
||||
unsigned long *args, unsigned long *out_val,
|
||||
static int sbi_ecall_time_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (funcid == SBI_EXT_TIME_SET_TIMER) {
|
||||
#if __riscv_xlen == 32
|
||||
sbi_timer_event_start(scratch,
|
||||
(((u64)args[1] << 32) | (u64)args[0]));
|
||||
sbi_timer_event_start((((u64)regs->a1 << 32) | (u64)regs->a0));
|
||||
#else
|
||||
sbi_timer_event_start(scratch, (u64)args[0]);
|
||||
sbi_timer_event_start((u64)regs->a0);
|
||||
#endif
|
||||
} else
|
||||
ret = SBI_ENOTSUPP;
|
||||
@@ -43,14 +44,15 @@ struct sbi_ecall_extension ecall_time = {
|
||||
.handle = sbi_ecall_time_handler,
|
||||
};
|
||||
|
||||
static int sbi_ecall_rfence_handler(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long funcid,
|
||||
unsigned long *args, unsigned long *out_val,
|
||||
static int sbi_ecall_rfence_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
int ret = 0;
|
||||
unsigned long vmid;
|
||||
struct sbi_tlb_info tlb_info;
|
||||
u32 source_hart = sbi_current_hartid();
|
||||
u32 source_hart = current_hartid();
|
||||
|
||||
if (funcid >= SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA &&
|
||||
funcid <= SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID)
|
||||
@@ -59,58 +61,46 @@ static int sbi_ecall_rfence_handler(struct sbi_scratch *scratch,
|
||||
|
||||
switch (funcid) {
|
||||
case SBI_EXT_RFENCE_REMOTE_FENCE_I:
|
||||
tlb_info.start = 0;
|
||||
tlb_info.size = 0;
|
||||
tlb_info.type = SBI_ITLB_FLUSH;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
|
||||
SBI_TLB_INFO_INIT(&tlb_info, 0, 0, 0, 0,
|
||||
sbi_tlb_local_fence_i, source_hart);
|
||||
ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
|
||||
break;
|
||||
case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA:
|
||||
tlb_info.start = (unsigned long)args[2];
|
||||
tlb_info.size = (unsigned long)args[3];
|
||||
tlb_info.type = SBI_TLB_FLUSH_GVMA;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, 0,
|
||||
sbi_tlb_local_hfence_gvma, source_hart);
|
||||
ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
|
||||
break;
|
||||
case SBI_EXT_RFENCE_REMOTE_HFENCE_GVMA_VMID:
|
||||
tlb_info.start = (unsigned long)args[2];
|
||||
tlb_info.size = (unsigned long)args[3];
|
||||
tlb_info.asid = (unsigned long)args[4];
|
||||
tlb_info.type = SBI_TLB_FLUSH_GVMA_VMID;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, regs->a4,
|
||||
sbi_tlb_local_hfence_gvma_vmid,
|
||||
source_hart);
|
||||
ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
|
||||
break;
|
||||
case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA:
|
||||
tlb_info.start = (unsigned long)args[2];
|
||||
tlb_info.size = (unsigned long)args[3];
|
||||
tlb_info.type = SBI_TLB_FLUSH_VVMA;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
|
||||
vmid = (csr_read(CSR_HGATP) & HGATP_VMID_MASK);
|
||||
vmid = vmid >> HGATP_VMID_SHIFT;
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, vmid,
|
||||
sbi_tlb_local_hfence_vvma, source_hart);
|
||||
ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
|
||||
break;
|
||||
case SBI_EXT_RFENCE_REMOTE_HFENCE_VVMA_ASID:
|
||||
tlb_info.start = (unsigned long)args[2];
|
||||
tlb_info.size = (unsigned long)args[3];
|
||||
tlb_info.asid = (unsigned long)args[4];
|
||||
tlb_info.type = SBI_TLB_FLUSH_VVMA_ASID;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
|
||||
vmid = (csr_read(CSR_HGATP) & HGATP_VMID_MASK);
|
||||
vmid = vmid >> HGATP_VMID_SHIFT;
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, regs->a4,
|
||||
vmid, sbi_tlb_local_hfence_vvma_asid,
|
||||
source_hart);
|
||||
ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
|
||||
break;
|
||||
case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA:
|
||||
tlb_info.start = (unsigned long)args[2];
|
||||
tlb_info.size = (unsigned long)args[3];
|
||||
tlb_info.type = SBI_TLB_FLUSH_VMA;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, 0, 0,
|
||||
sbi_tlb_local_sfence_vma, source_hart);
|
||||
ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
|
||||
break;
|
||||
case SBI_EXT_RFENCE_REMOTE_SFENCE_VMA_ASID:
|
||||
tlb_info.start = (unsigned long)args[2];
|
||||
tlb_info.size = (unsigned long)args[3];
|
||||
tlb_info.asid = (unsigned long)args[4];
|
||||
tlb_info.type = SBI_TLB_FLUSH_VMA_ASID;
|
||||
tlb_info.shart_mask = 1UL << source_hart;
|
||||
ret = sbi_tlb_request(scratch, args[0], args[1], &tlb_info);
|
||||
SBI_TLB_INFO_INIT(&tlb_info, regs->a2, regs->a3, regs->a4, 0,
|
||||
sbi_tlb_local_sfence_vma_asid, source_hart);
|
||||
ret = sbi_tlb_request(regs->a0, regs->a1, &tlb_info);
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = SBI_ENOTSUPP;
|
||||
};
|
||||
@@ -124,15 +114,15 @@ struct sbi_ecall_extension ecall_rfence = {
|
||||
.handle = sbi_ecall_rfence_handler,
|
||||
};
|
||||
|
||||
static int sbi_ecall_ipi_handler(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long funcid,
|
||||
unsigned long *args, unsigned long *out_val,
|
||||
static int sbi_ecall_ipi_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
if (funcid == SBI_EXT_IPI_SEND_IPI)
|
||||
ret = sbi_ipi_send_smode(scratch, args[0], args[1]);
|
||||
ret = sbi_ipi_send_smode(regs->a0, regs->a1);
|
||||
else
|
||||
ret = SBI_ENOTSUPP;
|
||||
|
||||
@@ -144,3 +134,63 @@ struct sbi_ecall_extension ecall_ipi = {
|
||||
.extid_end = SBI_EXT_IPI,
|
||||
.handle = sbi_ecall_ipi_handler,
|
||||
};
|
||||
|
||||
static int sbi_ecall_srst_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
if (funcid == SBI_EXT_SRST_RESET) {
|
||||
if ((((u32)-1U) <= ((u64)regs->a0)) ||
|
||||
(((u32)-1U) <= ((u64)regs->a1)))
|
||||
return SBI_EINVAL;
|
||||
|
||||
switch (regs->a0) {
|
||||
case SBI_SRST_RESET_TYPE_SHUTDOWN:
|
||||
case SBI_SRST_RESET_TYPE_COLD_REBOOT:
|
||||
case SBI_SRST_RESET_TYPE_WARM_REBOOT:
|
||||
break;
|
||||
default:
|
||||
return SBI_ENOTSUPP;
|
||||
}
|
||||
|
||||
switch (regs->a1) {
|
||||
case SBI_SRST_RESET_REASON_NONE:
|
||||
case SBI_SRST_RESET_REASON_SYSFAIL:
|
||||
break;
|
||||
default:
|
||||
return SBI_ENOTSUPP;
|
||||
}
|
||||
|
||||
if (sbi_system_reset_supported(regs->a0, regs->a1))
|
||||
sbi_system_reset(regs->a0, regs->a1);
|
||||
}
|
||||
|
||||
return SBI_ENOTSUPP;
|
||||
}
|
||||
|
||||
static int sbi_ecall_srst_probe(unsigned long extid, unsigned long *out_val)
|
||||
{
|
||||
u32 type, count = 0;
|
||||
|
||||
/*
|
||||
* At least one standard reset types should be supported by
|
||||
* the platform for SBI SRST extension to be usable.
|
||||
*/
|
||||
|
||||
for (type = 0; type <= SBI_SRST_RESET_TYPE_LAST; type++) {
|
||||
if (sbi_system_reset_supported(type,
|
||||
SBI_SRST_RESET_REASON_NONE))
|
||||
count++;
|
||||
}
|
||||
|
||||
*out_val = (count) ? 1 : 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct sbi_ecall_extension ecall_srst = {
|
||||
.extid_start = SBI_EXT_SRST,
|
||||
.extid_end = SBI_EXT_SRST,
|
||||
.handle = sbi_ecall_srst_handler,
|
||||
.probe = sbi_ecall_srst_probe,
|
||||
};
|
||||
|
@@ -12,23 +12,23 @@
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
|
||||
static int sbi_ecall_vendor_probe(struct sbi_scratch *scratch,
|
||||
unsigned long extid,
|
||||
static int sbi_ecall_vendor_probe(unsigned long extid,
|
||||
unsigned long *out_val)
|
||||
{
|
||||
*out_val = sbi_platform_vendor_ext_check(sbi_platform_ptr(scratch),
|
||||
*out_val = sbi_platform_vendor_ext_check(sbi_platform_thishart_ptr(),
|
||||
extid);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sbi_ecall_vendor_handler(struct sbi_scratch *scratch,
|
||||
unsigned long extid, unsigned long funcid,
|
||||
unsigned long *args, unsigned long *out_val,
|
||||
static int sbi_ecall_vendor_handler(unsigned long extid, unsigned long funcid,
|
||||
const struct sbi_trap_regs *regs,
|
||||
unsigned long *out_val,
|
||||
struct sbi_trap_info *out_trap)
|
||||
{
|
||||
return sbi_platform_vendor_ext_provider(sbi_platform_ptr(scratch),
|
||||
extid, funcid, args,
|
||||
return sbi_platform_vendor_ext_provider(sbi_platform_thishart_ptr(),
|
||||
extid, funcid, regs,
|
||||
out_val, out_trap);
|
||||
}
|
||||
|
||||
|
@@ -9,18 +9,35 @@
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/riscv_encoding.h>
|
||||
#include <sbi/sbi_bits.h>
|
||||
#include <sbi/sbi_bitops.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_emulate_csr.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_scratch.h>
|
||||
#include <sbi/sbi_timer.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
|
||||
int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch, ulong *csr_val)
|
||||
static bool hpm_allowed(int hpm_num, ulong prev_mode, bool virt)
|
||||
{
|
||||
ulong cen = -1UL;
|
||||
|
||||
if (prev_mode <= PRV_S) {
|
||||
cen &= csr_read(CSR_MCOUNTEREN);
|
||||
if (virt)
|
||||
cen &= csr_read(CSR_HCOUNTEREN);
|
||||
}
|
||||
if (prev_mode == PRV_U)
|
||||
cen &= csr_read(CSR_SCOUNTEREN);
|
||||
|
||||
return ((cen >> hpm_num) & 1) ? TRUE : FALSE;
|
||||
}
|
||||
|
||||
int sbi_emulate_csr_read(int csr_num, struct sbi_trap_regs *regs,
|
||||
ulong *csr_val)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong cen = -1UL;
|
||||
struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
|
||||
ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
|
||||
#if __riscv_xlen == 32
|
||||
bool virt = (regs->mstatusH & MSTATUSH_MPV) ? TRUE : FALSE;
|
||||
@@ -28,96 +45,112 @@ int sbi_emulate_csr_read(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
|
||||
bool virt = (regs->mstatus & MSTATUS_MPV) ? TRUE : FALSE;
|
||||
#endif
|
||||
|
||||
if (prev_mode == PRV_U)
|
||||
cen = csr_read(CSR_SCOUNTEREN);
|
||||
|
||||
switch (csr_num) {
|
||||
case CSR_HTIMEDELTA:
|
||||
if (prev_mode == PRV_S && !virt)
|
||||
*csr_val = sbi_timer_get_delta(scratch);
|
||||
*csr_val = sbi_timer_get_delta();
|
||||
else
|
||||
ret = SBI_ENOTSUPP;
|
||||
break;
|
||||
case CSR_CYCLE:
|
||||
if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
|
||||
return -1;
|
||||
if (!hpm_allowed(csr_num - CSR_CYCLE, prev_mode, virt))
|
||||
return SBI_ENOTSUPP;
|
||||
*csr_val = csr_read(CSR_MCYCLE);
|
||||
break;
|
||||
case CSR_TIME:
|
||||
if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
|
||||
return -1;
|
||||
*csr_val = (virt) ? sbi_timer_virt_value(scratch):
|
||||
sbi_timer_value(scratch);
|
||||
/*
|
||||
* We emulate TIME CSR for both Host (HS/U-mode) and
|
||||
* Guest (VS/VU-mode).
|
||||
*
|
||||
* Faster TIME CSR reads are critical for good performance
|
||||
* in S-mode software so we don't check CSR permissions.
|
||||
*/
|
||||
*csr_val = (virt) ? sbi_timer_virt_value():
|
||||
sbi_timer_value();
|
||||
break;
|
||||
case CSR_INSTRET:
|
||||
if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
|
||||
return -1;
|
||||
if (!hpm_allowed(csr_num - CSR_CYCLE, prev_mode, virt))
|
||||
return SBI_ENOTSUPP;
|
||||
*csr_val = csr_read(CSR_MINSTRET);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER3:
|
||||
if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
|
||||
return -1;
|
||||
*csr_val = csr_read(CSR_MHPMCOUNTER3);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER4:
|
||||
if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
|
||||
return -1;
|
||||
*csr_val = csr_read(CSR_MHPMCOUNTER4);
|
||||
break;
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
case CSR_HTIMEDELTAH:
|
||||
if (prev_mode == PRV_S && !virt)
|
||||
*csr_val = sbi_timer_get_delta(scratch) >> 32;
|
||||
*csr_val = sbi_timer_get_delta() >> 32;
|
||||
else
|
||||
ret = SBI_ENOTSUPP;
|
||||
break;
|
||||
case CSR_CYCLEH:
|
||||
if (!((cen >> (CSR_CYCLE - CSR_CYCLE)) & 1))
|
||||
return -1;
|
||||
if (!hpm_allowed(csr_num - CSR_CYCLEH, prev_mode, virt))
|
||||
return SBI_ENOTSUPP;
|
||||
*csr_val = csr_read(CSR_MCYCLEH);
|
||||
break;
|
||||
case CSR_TIMEH:
|
||||
if (!((cen >> (CSR_TIME - CSR_CYCLE)) & 1))
|
||||
return -1;
|
||||
*csr_val = (virt) ? sbi_timer_virt_value(scratch) >> 32:
|
||||
sbi_timer_value(scratch) >> 32;
|
||||
/* Refer comments on TIME CSR above. */
|
||||
*csr_val = (virt) ? sbi_timer_virt_value() >> 32:
|
||||
sbi_timer_value() >> 32;
|
||||
break;
|
||||
case CSR_INSTRETH:
|
||||
if (!((cen >> (CSR_INSTRET - CSR_CYCLE)) & 1))
|
||||
return -1;
|
||||
if (!hpm_allowed(csr_num - CSR_CYCLEH, prev_mode, virt))
|
||||
return SBI_ENOTSUPP;
|
||||
*csr_val = csr_read(CSR_MINSTRETH);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER3H:
|
||||
if (!((cen >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1))
|
||||
return -1;
|
||||
*csr_val = csr_read(CSR_MHPMCOUNTER3H);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER4H:
|
||||
if (!((cen >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1))
|
||||
return -1;
|
||||
*csr_val = csr_read(CSR_MHPMCOUNTER4H);
|
||||
break;
|
||||
#endif
|
||||
case CSR_MHPMEVENT3:
|
||||
*csr_val = csr_read(CSR_MHPMEVENT3);
|
||||
break;
|
||||
case CSR_MHPMEVENT4:
|
||||
*csr_val = csr_read(CSR_MHPMEVENT4);
|
||||
|
||||
#define switchcase_hpm(__uref, __mref, __csr) \
|
||||
case __csr: \
|
||||
if ((sbi_hart_mhpm_count(scratch) + 3) <= (__csr - __uref))\
|
||||
return SBI_ENOTSUPP; \
|
||||
if (!hpm_allowed(__csr - __uref, prev_mode, virt)) \
|
||||
return SBI_ENOTSUPP; \
|
||||
*csr_val = csr_read(__mref + __csr - __uref); \
|
||||
break;
|
||||
#define switchcase_hpm_2(__uref, __mref, __csr) \
|
||||
switchcase_hpm(__uref, __mref, __csr + 0) \
|
||||
switchcase_hpm(__uref, __mref, __csr + 1)
|
||||
#define switchcase_hpm_4(__uref, __mref, __csr) \
|
||||
switchcase_hpm_2(__uref, __mref, __csr + 0) \
|
||||
switchcase_hpm_2(__uref, __mref, __csr + 2)
|
||||
#define switchcase_hpm_8(__uref, __mref, __csr) \
|
||||
switchcase_hpm_4(__uref, __mref, __csr + 0) \
|
||||
switchcase_hpm_4(__uref, __mref, __csr + 4)
|
||||
#define switchcase_hpm_16(__uref, __mref, __csr) \
|
||||
switchcase_hpm_8(__uref, __mref, __csr + 0) \
|
||||
switchcase_hpm_8(__uref, __mref, __csr + 8)
|
||||
|
||||
switchcase_hpm(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER3)
|
||||
switchcase_hpm_4(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER4)
|
||||
switchcase_hpm_8(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER8)
|
||||
switchcase_hpm_16(CSR_CYCLE, CSR_MCYCLE, CSR_HPMCOUNTER16)
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
switchcase_hpm(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER3H)
|
||||
switchcase_hpm_4(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER4H)
|
||||
switchcase_hpm_8(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER8H)
|
||||
switchcase_hpm_16(CSR_CYCLEH, CSR_MCYCLEH, CSR_HPMCOUNTER16H)
|
||||
#endif
|
||||
|
||||
#undef switchcase_hpm_16
|
||||
#undef switchcase_hpm_8
|
||||
#undef switchcase_hpm_4
|
||||
#undef switchcase_hpm_2
|
||||
#undef switchcase_hpm
|
||||
|
||||
default:
|
||||
ret = SBI_ENOTSUPP;
|
||||
break;
|
||||
};
|
||||
|
||||
if (ret)
|
||||
sbi_dprintf(scratch, "%s: hartid%d: invalid csr_num=0x%x\n",
|
||||
__func__, hartid, csr_num);
|
||||
sbi_dprintf("%s: hartid%d: invalid csr_num=0x%x\n",
|
||||
__func__, current_hartid(), csr_num);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch, ulong csr_val)
|
||||
int sbi_emulate_csr_write(int csr_num, struct sbi_trap_regs *regs,
|
||||
ulong csr_val)
|
||||
{
|
||||
int ret = 0;
|
||||
ulong prev_mode = (regs->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT;
|
||||
@@ -130,56 +163,26 @@ int sbi_emulate_csr_write(int csr_num, u32 hartid, struct sbi_trap_regs *regs,
|
||||
switch (csr_num) {
|
||||
case CSR_HTIMEDELTA:
|
||||
if (prev_mode == PRV_S && !virt)
|
||||
sbi_timer_set_delta(scratch, csr_val);
|
||||
sbi_timer_set_delta(csr_val);
|
||||
else
|
||||
ret = SBI_ENOTSUPP;
|
||||
break;
|
||||
case CSR_CYCLE:
|
||||
csr_write(CSR_MCYCLE, csr_val);
|
||||
break;
|
||||
case CSR_INSTRET:
|
||||
csr_write(CSR_MINSTRET, csr_val);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER3:
|
||||
csr_write(CSR_MHPMCOUNTER3, csr_val);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER4:
|
||||
csr_write(CSR_MHPMCOUNTER4, csr_val);
|
||||
break;
|
||||
#if __riscv_xlen == 32
|
||||
case CSR_HTIMEDELTAH:
|
||||
if (prev_mode == PRV_S && !virt)
|
||||
sbi_timer_set_delta_upper(scratch, csr_val);
|
||||
sbi_timer_set_delta_upper(csr_val);
|
||||
else
|
||||
ret = SBI_ENOTSUPP;
|
||||
break;
|
||||
case CSR_CYCLEH:
|
||||
csr_write(CSR_MCYCLEH, csr_val);
|
||||
break;
|
||||
case CSR_INSTRETH:
|
||||
csr_write(CSR_MINSTRETH, csr_val);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER3H:
|
||||
csr_write(CSR_MHPMCOUNTER3H, csr_val);
|
||||
break;
|
||||
case CSR_MHPMCOUNTER4H:
|
||||
csr_write(CSR_MHPMCOUNTER4H, csr_val);
|
||||
break;
|
||||
#endif
|
||||
case CSR_MHPMEVENT3:
|
||||
csr_write(CSR_MHPMEVENT3, csr_val);
|
||||
break;
|
||||
case CSR_MHPMEVENT4:
|
||||
csr_write(CSR_MHPMEVENT4, csr_val);
|
||||
break;
|
||||
default:
|
||||
ret = SBI_ENOTSUPP;
|
||||
break;
|
||||
};
|
||||
|
||||
if (ret)
|
||||
sbi_dprintf(scratch, "%s: hartid%d: invalid csr_num=0x%x\n",
|
||||
__func__, hartid, csr_num);
|
||||
sbi_dprintf("%s: hartid%d: invalid csr_num=0x%x\n",
|
||||
__func__, current_hartid(), csr_num);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
56
lib/sbi/sbi_expected_trap.S
Normal file
56
lib/sbi/sbi_expected_trap.S
Normal file
@@ -0,0 +1,56 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Anup Patel <anup.patel@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
|
||||
/*
|
||||
* We assume that faulting instruction is is 4-byte long and blindly
|
||||
* increment SEPC by 4.
|
||||
*
|
||||
* The trap info will be saved as follows:
|
||||
* A3 <- pointer struct sbi_trap_info
|
||||
* A4 <- temporary
|
||||
*/
|
||||
|
||||
.align 3
|
||||
.global __sbi_expected_trap
|
||||
__sbi_expected_trap:
|
||||
/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
|
||||
csrr a4, CSR_MEPC
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
|
||||
csrr a4, CSR_MCAUSE
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
|
||||
csrr a4, CSR_MTVAL
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
|
||||
REG_S zero, SBI_TRAP_INFO_OFFSET(tval2)(a3)
|
||||
REG_S zero, SBI_TRAP_INFO_OFFSET(tinst)(a3)
|
||||
csrr a4, CSR_MEPC
|
||||
addi a4, a4, 4
|
||||
csrw CSR_MEPC, a4
|
||||
mret
|
||||
|
||||
.align 3
|
||||
.global __sbi_expected_trap_hext
|
||||
__sbi_expected_trap_hext:
|
||||
/* With H-extension so, MTVAL2 and MTINST CSRs available */
|
||||
csrr a4, CSR_MEPC
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
|
||||
csrr a4, CSR_MCAUSE
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(cause)(a3)
|
||||
csrr a4, CSR_MTVAL
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(tval)(a3)
|
||||
csrr a4, CSR_MTVAL2
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(tval2)(a3)
|
||||
csrr a4, CSR_MTINST
|
||||
REG_S a4, SBI_TRAP_INFO_OFFSET(tinst)(a3)
|
||||
csrr a4, CSR_MEPC
|
||||
addi a4, a4, 4
|
||||
csrw CSR_MEPC, a4
|
||||
mret
|
@@ -11,33 +11,50 @@
|
||||
#include <sbi/riscv_barrier.h>
|
||||
#include <sbi/riscv_encoding.h>
|
||||
#include <sbi/riscv_fp.h>
|
||||
#include <sbi/riscv_locks.h>
|
||||
#include <sbi/sbi_bits.h>
|
||||
#include <sbi/sbi_bitops.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_csr_detect.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_math.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_string.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
|
||||
/**
|
||||
* Return HART ID of the caller.
|
||||
*/
|
||||
unsigned int sbi_current_hartid()
|
||||
{
|
||||
return (u32)csr_read(CSR_MHARTID);
|
||||
}
|
||||
extern void __sbi_expected_trap(void);
|
||||
extern void __sbi_expected_trap_hext(void);
|
||||
|
||||
static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
|
||||
void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
|
||||
|
||||
struct hart_features {
|
||||
unsigned long features;
|
||||
unsigned int pmp_count;
|
||||
unsigned int pmp_addr_bits;
|
||||
unsigned long pmp_gran;
|
||||
unsigned int mhpm_count;
|
||||
};
|
||||
static unsigned long hart_features_offset;
|
||||
|
||||
static void mstatus_init(struct sbi_scratch *scratch)
|
||||
{
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
unsigned long mstatus_val = 0;
|
||||
|
||||
/* Enable FPU */
|
||||
if (misa_extension('D') || misa_extension('F'))
|
||||
csr_write(CSR_MSTATUS, MSTATUS_FS);
|
||||
mstatus_val |= MSTATUS_FS;
|
||||
|
||||
/* Enable Vector context */
|
||||
if (misa_extension('V'))
|
||||
mstatus_val |= MSTATUS_VS;
|
||||
|
||||
csr_write(CSR_MSTATUS, mstatus_val);
|
||||
|
||||
/* Enable user/supervisor use of perf counters */
|
||||
if (misa_extension('S') && sbi_platform_has_scounteren(plat))
|
||||
if (misa_extension('S') &&
|
||||
sbi_hart_has_feature(scratch, SBI_HART_HAS_SCOUNTEREN))
|
||||
csr_write(CSR_SCOUNTEREN, -1);
|
||||
if (sbi_platform_has_mcounteren(plat))
|
||||
if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MCOUNTEREN))
|
||||
csr_write(CSR_MCOUNTEREN, -1);
|
||||
|
||||
/* Disable all interrupts */
|
||||
@@ -48,7 +65,7 @@ static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
|
||||
csr_write(CSR_SATP, 0);
|
||||
}
|
||||
|
||||
static int fp_init(u32 hartid)
|
||||
static int fp_init(struct sbi_scratch *scratch)
|
||||
{
|
||||
#ifdef __riscv_flen
|
||||
int i;
|
||||
@@ -69,13 +86,13 @@ static int fp_init(u32 hartid)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
|
||||
static int delegate_traps(struct sbi_scratch *scratch)
|
||||
{
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
unsigned long interrupts, exceptions;
|
||||
|
||||
if (!misa_extension('S'))
|
||||
/* No delegation possible as mideleg does not exist*/
|
||||
/* No delegation possible as mideleg does not exist */
|
||||
return 0;
|
||||
|
||||
/* Send M-mode interrupts and most exceptions to S-mode */
|
||||
@@ -95,9 +112,10 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
|
||||
* from VS-mode), Guest page faults and Virtual interrupts.
|
||||
*/
|
||||
if (misa_extension('H')) {
|
||||
exceptions |= (1U << CAUSE_SUPERVISOR_ECALL);
|
||||
exceptions |= (1U << CAUSE_VIRTUAL_SUPERVISOR_ECALL);
|
||||
exceptions |= (1U << CAUSE_FETCH_GUEST_PAGE_FAULT);
|
||||
exceptions |= (1U << CAUSE_LOAD_GUEST_PAGE_FAULT);
|
||||
exceptions |= (1U << CAUSE_VIRTUAL_INST_FAULT);
|
||||
exceptions |= (1U << CAUSE_STORE_GUEST_PAGE_FAULT);
|
||||
}
|
||||
|
||||
@@ -107,141 +125,339 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sbi_hart_delegation_dump(struct sbi_scratch *scratch)
|
||||
void sbi_hart_delegation_dump(struct sbi_scratch *scratch,
|
||||
const char *prefix, const char *suffix)
|
||||
{
|
||||
#if __riscv_xlen == 32
|
||||
sbi_printf("MIDELEG : 0x%08lx\n", csr_read(CSR_MIDELEG));
|
||||
sbi_printf("MEDELEG : 0x%08lx\n", csr_read(CSR_MEDELEG));
|
||||
#else
|
||||
sbi_printf("MIDELEG : 0x%016lx\n", csr_read(CSR_MIDELEG));
|
||||
sbi_printf("MEDELEG : 0x%016lx\n", csr_read(CSR_MEDELEG));
|
||||
#endif
|
||||
}
|
||||
|
||||
unsigned long log2roundup(unsigned long x)
|
||||
{
|
||||
unsigned long ret = 0;
|
||||
|
||||
while (ret < __riscv_xlen) {
|
||||
if (x <= (1UL << ret))
|
||||
break;
|
||||
ret++;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void sbi_hart_pmp_dump(struct sbi_scratch *scratch)
|
||||
{
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
unsigned long prot, addr, size, l2l;
|
||||
unsigned int i;
|
||||
|
||||
if (!sbi_platform_has_pmp(plat))
|
||||
if (!misa_extension('S'))
|
||||
/* No delegation possible as mideleg does not exist*/
|
||||
return;
|
||||
|
||||
for (i = 0; i < PMP_COUNT; i++) {
|
||||
pmp_get(i, &prot, &addr, &l2l);
|
||||
if (!(prot & PMP_A))
|
||||
continue;
|
||||
if (l2l < __riscv_xlen)
|
||||
size = (1UL << l2l);
|
||||
else
|
||||
size = 0;
|
||||
#if __riscv_xlen == 32
|
||||
sbi_printf("PMP%d : 0x%08lx-0x%08lx (A",
|
||||
sbi_printf("%sMIDELEG%s: 0x%08lx\n",
|
||||
prefix, suffix, csr_read(CSR_MIDELEG));
|
||||
sbi_printf("%sMEDELEG%s: 0x%08lx\n",
|
||||
prefix, suffix, csr_read(CSR_MEDELEG));
|
||||
#else
|
||||
sbi_printf("PMP%d : 0x%016lx-0x%016lx (A",
|
||||
sbi_printf("%sMIDELEG%s: 0x%016lx\n",
|
||||
prefix, suffix, csr_read(CSR_MIDELEG));
|
||||
sbi_printf("%sMEDELEG%s: 0x%016lx\n",
|
||||
prefix, suffix, csr_read(CSR_MEDELEG));
|
||||
#endif
|
||||
i, addr, addr + size - 1);
|
||||
if (prot & PMP_L)
|
||||
sbi_printf(",L");
|
||||
if (prot & PMP_R)
|
||||
sbi_printf(",R");
|
||||
if (prot & PMP_W)
|
||||
sbi_printf(",W");
|
||||
if (prot & PMP_X)
|
||||
sbi_printf(",X");
|
||||
sbi_printf(")\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int pmp_init(struct sbi_scratch *scratch, u32 hartid)
|
||||
unsigned int sbi_hart_mhpm_count(struct sbi_scratch *scratch)
|
||||
{
|
||||
u32 i, count;
|
||||
unsigned long fw_start, fw_size_log2;
|
||||
ulong prot, addr, log2size;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
struct hart_features *hfeatures =
|
||||
sbi_scratch_offset_ptr(scratch, hart_features_offset);
|
||||
|
||||
if (!sbi_platform_has_pmp(plat))
|
||||
return hfeatures->mhpm_count;
|
||||
}
|
||||
|
||||
unsigned int sbi_hart_pmp_count(struct sbi_scratch *scratch)
|
||||
{
|
||||
struct hart_features *hfeatures =
|
||||
sbi_scratch_offset_ptr(scratch, hart_features_offset);
|
||||
|
||||
return hfeatures->pmp_count;
|
||||
}
|
||||
|
||||
unsigned long sbi_hart_pmp_granularity(struct sbi_scratch *scratch)
|
||||
{
|
||||
struct hart_features *hfeatures =
|
||||
sbi_scratch_offset_ptr(scratch, hart_features_offset);
|
||||
|
||||
return hfeatures->pmp_gran;
|
||||
}
|
||||
|
||||
unsigned int sbi_hart_pmp_addrbits(struct sbi_scratch *scratch)
|
||||
{
|
||||
struct hart_features *hfeatures =
|
||||
sbi_scratch_offset_ptr(scratch, hart_features_offset);
|
||||
|
||||
return hfeatures->pmp_addr_bits;
|
||||
}
|
||||
|
||||
int sbi_hart_pmp_configure(struct sbi_scratch *scratch)
|
||||
{
|
||||
struct sbi_domain_memregion *reg;
|
||||
struct sbi_domain *dom = sbi_domain_thishart_ptr();
|
||||
unsigned int pmp_idx = 0, pmp_flags, pmp_bits, pmp_gran_log2;
|
||||
unsigned int pmp_count = sbi_hart_pmp_count(scratch);
|
||||
unsigned long pmp_addr = 0, pmp_addr_max = 0;
|
||||
|
||||
if (!pmp_count)
|
||||
return 0;
|
||||
|
||||
fw_size_log2 = log2roundup(scratch->fw_size);
|
||||
fw_start = scratch->fw_start & ~((1UL << fw_size_log2) - 1UL);
|
||||
pmp_gran_log2 = log2roundup(sbi_hart_pmp_granularity(scratch));
|
||||
pmp_bits = sbi_hart_pmp_addrbits(scratch) - 1;
|
||||
pmp_addr_max = (1UL << pmp_bits) | ((1UL << pmp_bits) - 1);
|
||||
|
||||
pmp_set(0, 0, fw_start, fw_size_log2);
|
||||
sbi_domain_for_each_memregion(dom, reg) {
|
||||
if (pmp_count <= pmp_idx)
|
||||
break;
|
||||
|
||||
count = sbi_platform_pmp_region_count(plat, hartid);
|
||||
if ((PMP_COUNT - 1) < count)
|
||||
count = (PMP_COUNT - 1);
|
||||
pmp_flags = 0;
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_READABLE)
|
||||
pmp_flags |= PMP_R;
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_WRITEABLE)
|
||||
pmp_flags |= PMP_W;
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_EXECUTABLE)
|
||||
pmp_flags |= PMP_X;
|
||||
if (reg->flags & SBI_DOMAIN_MEMREGION_MMODE)
|
||||
pmp_flags |= PMP_L;
|
||||
|
||||
for (i = 0; i < count; i++) {
|
||||
if (sbi_platform_pmp_region_info(plat, hartid, i, &prot, &addr,
|
||||
&log2size))
|
||||
continue;
|
||||
pmp_set(i + 1, prot, addr, log2size);
|
||||
pmp_addr = reg->base >> PMP_SHIFT;
|
||||
if (pmp_gran_log2 <= reg->order && pmp_addr < pmp_addr_max)
|
||||
pmp_set(pmp_idx++, pmp_flags, reg->base, reg->order);
|
||||
else {
|
||||
sbi_printf("Can not configure pmp for domain %s", dom->name);
|
||||
sbi_printf("because memory region address %lx or size %lx is not in range\n",
|
||||
reg->base, reg->order);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long trap_info_offset;
|
||||
/**
|
||||
* Check whether a particular hart feature is available
|
||||
*
|
||||
* @param scratch pointer to the HART scratch space
|
||||
* @param feature the feature to check
|
||||
* @returns true (feature available) or false (feature not available)
|
||||
*/
|
||||
bool sbi_hart_has_feature(struct sbi_scratch *scratch, unsigned long feature)
|
||||
{
|
||||
struct hart_features *hfeatures =
|
||||
sbi_scratch_offset_ptr(scratch, hart_features_offset);
|
||||
|
||||
int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
|
||||
if (hfeatures->features & feature)
|
||||
return true;
|
||||
else
|
||||
return false;
|
||||
}
|
||||
|
||||
static unsigned long hart_get_features(struct sbi_scratch *scratch)
|
||||
{
|
||||
struct hart_features *hfeatures =
|
||||
sbi_scratch_offset_ptr(scratch, hart_features_offset);
|
||||
|
||||
return hfeatures->features;
|
||||
}
|
||||
|
||||
static inline char *sbi_hart_feature_id2string(unsigned long feature)
|
||||
{
|
||||
char *fstr = NULL;
|
||||
|
||||
if (!feature)
|
||||
return NULL;
|
||||
|
||||
switch (feature) {
|
||||
case SBI_HART_HAS_SCOUNTEREN:
|
||||
fstr = "scounteren";
|
||||
break;
|
||||
case SBI_HART_HAS_MCOUNTEREN:
|
||||
fstr = "mcounteren";
|
||||
break;
|
||||
case SBI_HART_HAS_TIME:
|
||||
fstr = "time";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return fstr;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the hart features in string format
|
||||
*
|
||||
* @param scratch pointer to the HART scratch space
|
||||
* @param features_str pointer to a char array where the features string will be
|
||||
* updated
|
||||
* @param nfstr length of the features_str. The feature string will be truncated
|
||||
* if nfstr is not long enough.
|
||||
*/
|
||||
void sbi_hart_get_features_str(struct sbi_scratch *scratch,
|
||||
char *features_str, int nfstr)
|
||||
{
|
||||
unsigned long features, feat = 1UL;
|
||||
char *temp;
|
||||
int offset = 0;
|
||||
|
||||
if (!features_str || nfstr <= 0)
|
||||
return;
|
||||
sbi_memset(features_str, 0, nfstr);
|
||||
|
||||
features = hart_get_features(scratch);
|
||||
if (!features)
|
||||
goto done;
|
||||
|
||||
do {
|
||||
if (features & feat) {
|
||||
temp = sbi_hart_feature_id2string(feat);
|
||||
if (temp) {
|
||||
sbi_snprintf(features_str + offset, nfstr,
|
||||
"%s,", temp);
|
||||
offset = offset + sbi_strlen(temp) + 1;
|
||||
}
|
||||
}
|
||||
feat = feat << 1;
|
||||
} while (feat <= SBI_HART_HAS_LAST_FEATURE);
|
||||
|
||||
done:
|
||||
if (offset)
|
||||
features_str[offset - 1] = '\0';
|
||||
else
|
||||
sbi_strncpy(features_str, "none", nfstr);
|
||||
}
|
||||
|
||||
static unsigned long hart_pmp_get_allowed_addr(void)
|
||||
{
|
||||
unsigned long val = 0;
|
||||
struct sbi_trap_info trap = {0};
|
||||
|
||||
csr_write_allowed(CSR_PMPADDR0, (ulong)&trap, PMP_ADDR_MASK); \
|
||||
if (!trap.cause) {
|
||||
val = csr_read_allowed(CSR_PMPADDR0, (ulong)&trap);
|
||||
if (trap.cause)
|
||||
val = 0;
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static void hart_detect_features(struct sbi_scratch *scratch)
|
||||
{
|
||||
struct sbi_trap_info trap = {0};
|
||||
struct hart_features *hfeatures;
|
||||
unsigned long val;
|
||||
|
||||
/* Reset hart features */
|
||||
hfeatures = sbi_scratch_offset_ptr(scratch, hart_features_offset);
|
||||
hfeatures->features = 0;
|
||||
hfeatures->pmp_count = 0;
|
||||
hfeatures->mhpm_count = 0;
|
||||
|
||||
#define __check_csr(__csr, __rdonly, __wrval, __field, __skip) \
|
||||
val = csr_read_allowed(__csr, (ulong)&trap); \
|
||||
if (!trap.cause) { \
|
||||
if (__rdonly) { \
|
||||
(hfeatures->__field)++; \
|
||||
} else { \
|
||||
csr_write_allowed(__csr, (ulong)&trap, __wrval);\
|
||||
if (!trap.cause) { \
|
||||
if (csr_swap(__csr, val) == __wrval) \
|
||||
(hfeatures->__field)++; \
|
||||
else \
|
||||
goto __skip; \
|
||||
} else { \
|
||||
goto __skip; \
|
||||
} \
|
||||
} \
|
||||
} else { \
|
||||
goto __skip; \
|
||||
}
|
||||
#define __check_csr_2(__csr, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr(__csr + 0, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr(__csr + 1, __rdonly, __wrval, __field, __skip)
|
||||
#define __check_csr_4(__csr, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_2(__csr + 0, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_2(__csr + 2, __rdonly, __wrval, __field, __skip)
|
||||
#define __check_csr_8(__csr, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_4(__csr + 0, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_4(__csr + 4, __rdonly, __wrval, __field, __skip)
|
||||
#define __check_csr_16(__csr, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_8(__csr + 0, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_8(__csr + 8, __rdonly, __wrval, __field, __skip)
|
||||
#define __check_csr_32(__csr, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_16(__csr + 0, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_16(__csr + 16, __rdonly, __wrval, __field, __skip)
|
||||
#define __check_csr_64(__csr, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_32(__csr + 0, __rdonly, __wrval, __field, __skip) \
|
||||
__check_csr_32(__csr + 32, __rdonly, __wrval, __field, __skip)
|
||||
|
||||
/**
|
||||
* Detect the allowed address bits & granularity. At least PMPADDR0
|
||||
* should be implemented.
|
||||
*/
|
||||
val = hart_pmp_get_allowed_addr();
|
||||
if (val) {
|
||||
hfeatures->pmp_gran = 1 << (__ffs(val) + 2);
|
||||
hfeatures->pmp_addr_bits = __fls(val) + 1;
|
||||
/* Detect number of PMP regions. At least PMPADDR0 should be implemented*/
|
||||
__check_csr_64(CSR_PMPADDR0, 0, val, pmp_count, __pmp_skip);
|
||||
}
|
||||
__pmp_skip:
|
||||
|
||||
/* Detect number of MHPM counters */
|
||||
__check_csr(CSR_MHPMCOUNTER3, 0, 1UL, mhpm_count, __mhpm_skip);
|
||||
__check_csr_4(CSR_MHPMCOUNTER4, 0, 1UL, mhpm_count, __mhpm_skip);
|
||||
__check_csr_8(CSR_MHPMCOUNTER8, 0, 1UL, mhpm_count, __mhpm_skip);
|
||||
__check_csr_16(CSR_MHPMCOUNTER16, 0, 1UL, mhpm_count, __mhpm_skip);
|
||||
__mhpm_skip:
|
||||
|
||||
#undef __check_csr_64
|
||||
#undef __check_csr_32
|
||||
#undef __check_csr_16
|
||||
#undef __check_csr_8
|
||||
#undef __check_csr_4
|
||||
#undef __check_csr_2
|
||||
#undef __check_csr
|
||||
|
||||
/* Detect if hart supports SCOUNTEREN feature */
|
||||
trap.cause = 0;
|
||||
val = csr_read_allowed(CSR_SCOUNTEREN, (unsigned long)&trap);
|
||||
if (!trap.cause) {
|
||||
csr_write_allowed(CSR_SCOUNTEREN, (unsigned long)&trap, val);
|
||||
if (!trap.cause)
|
||||
hfeatures->features |= SBI_HART_HAS_SCOUNTEREN;
|
||||
}
|
||||
|
||||
/* Detect if hart supports MCOUNTEREN feature */
|
||||
trap.cause = 0;
|
||||
val = csr_read_allowed(CSR_MCOUNTEREN, (unsigned long)&trap);
|
||||
if (!trap.cause) {
|
||||
csr_write_allowed(CSR_MCOUNTEREN, (unsigned long)&trap, val);
|
||||
if (!trap.cause)
|
||||
hfeatures->features |= SBI_HART_HAS_MCOUNTEREN;
|
||||
}
|
||||
|
||||
/* Detect if hart supports time CSR */
|
||||
trap.cause = 0;
|
||||
csr_read_allowed(CSR_TIME, (unsigned long)&trap);
|
||||
if (!trap.cause)
|
||||
hfeatures->features |= SBI_HART_HAS_TIME;
|
||||
}
|
||||
|
||||
int sbi_hart_init(struct sbi_scratch *scratch, bool cold_boot)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (cold_boot) {
|
||||
trap_info_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
|
||||
"HART_TRAP_INFO");
|
||||
if (!trap_info_offset)
|
||||
if (misa_extension('H'))
|
||||
sbi_hart_expected_trap = &__sbi_expected_trap_hext;
|
||||
|
||||
hart_features_offset = sbi_scratch_alloc_offset(
|
||||
sizeof(struct hart_features),
|
||||
"HART_FEATURES");
|
||||
if (!hart_features_offset)
|
||||
return SBI_ENOMEM;
|
||||
}
|
||||
|
||||
mstatus_init(scratch, hartid);
|
||||
hart_detect_features(scratch);
|
||||
|
||||
rc = fp_init(hartid);
|
||||
mstatus_init(scratch);
|
||||
|
||||
rc = fp_init(scratch);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
rc = delegate_traps(scratch, hartid);
|
||||
rc = delegate_traps(scratch);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
return pmp_init(scratch, hartid);
|
||||
}
|
||||
|
||||
void *sbi_hart_get_trap_info(struct sbi_scratch *scratch)
|
||||
{
|
||||
unsigned long *trap_info;
|
||||
|
||||
if (!trap_info_offset)
|
||||
return NULL;
|
||||
|
||||
trap_info = sbi_scratch_offset_ptr(scratch, trap_info_offset);
|
||||
|
||||
return (void *)(*trap_info);
|
||||
}
|
||||
|
||||
void sbi_hart_set_trap_info(struct sbi_scratch *scratch, void *data)
|
||||
{
|
||||
unsigned long *trap_info;
|
||||
|
||||
if (!trap_info_offset)
|
||||
return;
|
||||
|
||||
trap_info = sbi_scratch_offset_ptr(scratch, trap_info_offset);
|
||||
*trap_info = (unsigned long)data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __attribute__((noreturn)) sbi_hart_hang(void)
|
||||
@@ -306,9 +522,11 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
|
||||
csr_write(CSR_SIE, 0);
|
||||
csr_write(CSR_SATP, 0);
|
||||
} else if (next_mode == PRV_U) {
|
||||
csr_write(CSR_UTVEC, next_addr);
|
||||
csr_write(CSR_USCRATCH, 0);
|
||||
csr_write(CSR_UIE, 0);
|
||||
if (misa_extension('N')) {
|
||||
csr_write(CSR_UTVEC, next_addr);
|
||||
csr_write(CSR_USCRATCH, 0);
|
||||
csr_write(CSR_UIE, 0);
|
||||
}
|
||||
}
|
||||
|
||||
register unsigned long a0 asm("a0") = arg0;
|
||||
@@ -316,106 +534,3 @@ sbi_hart_switch_mode(unsigned long arg0, unsigned long arg1,
|
||||
__asm__ __volatile__("mret" : : "r"(a0), "r"(a1));
|
||||
__builtin_unreachable();
|
||||
}
|
||||
|
||||
static spinlock_t avail_hart_mask_lock = SPIN_LOCK_INITIALIZER;
|
||||
static volatile unsigned long avail_hart_mask = 0;
|
||||
|
||||
void sbi_hart_mark_available(u32 hartid)
|
||||
{
|
||||
spin_lock(&avail_hart_mask_lock);
|
||||
avail_hart_mask |= (1UL << hartid);
|
||||
spin_unlock(&avail_hart_mask_lock);
|
||||
}
|
||||
|
||||
void sbi_hart_unmark_available(u32 hartid)
|
||||
{
|
||||
spin_lock(&avail_hart_mask_lock);
|
||||
avail_hart_mask &= ~(1UL << hartid);
|
||||
spin_unlock(&avail_hart_mask_lock);
|
||||
}
|
||||
|
||||
ulong sbi_hart_available_mask(void)
|
||||
{
|
||||
ulong ret;
|
||||
|
||||
spin_lock(&avail_hart_mask_lock);
|
||||
ret = avail_hart_mask;
|
||||
spin_unlock(&avail_hart_mask_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
typedef struct sbi_scratch *(*h2s)(ulong hartid);
|
||||
|
||||
struct sbi_scratch *sbi_hart_id_to_scratch(struct sbi_scratch *scratch,
|
||||
u32 hartid)
|
||||
{
|
||||
return ((h2s)scratch->hartid_to_scratch)(hartid);
|
||||
}
|
||||
|
||||
#define COLDBOOT_WAIT_BITMAP_SIZE __riscv_xlen
|
||||
static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
|
||||
static unsigned long coldboot_done = 0;
|
||||
static unsigned long coldboot_wait_bitmap = 0;
|
||||
|
||||
void sbi_hart_wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
|
||||
{
|
||||
unsigned long saved_mie;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
if ((sbi_platform_hart_count(plat) <= hartid) ||
|
||||
(COLDBOOT_WAIT_BITMAP_SIZE <= hartid))
|
||||
sbi_hart_hang();
|
||||
|
||||
/* Save MIE CSR */
|
||||
saved_mie = csr_read(CSR_MIE);
|
||||
|
||||
/* Set MSIE bit to receive IPI */
|
||||
csr_set(CSR_MIE, MIP_MSIP);
|
||||
|
||||
/* Acquire coldboot lock */
|
||||
spin_lock(&coldboot_lock);
|
||||
|
||||
/* Mark current HART as waiting */
|
||||
coldboot_wait_bitmap |= (1UL << hartid);
|
||||
|
||||
/* Wait for coldboot to finish using WFI */
|
||||
while (!coldboot_done) {
|
||||
spin_unlock(&coldboot_lock);
|
||||
wfi();
|
||||
spin_lock(&coldboot_lock);
|
||||
};
|
||||
|
||||
/* Unmark current HART as waiting */
|
||||
coldboot_wait_bitmap &= ~(1UL << hartid);
|
||||
|
||||
/* Release coldboot lock */
|
||||
spin_unlock(&coldboot_lock);
|
||||
|
||||
/* Restore MIE CSR */
|
||||
csr_write(CSR_MIE, saved_mie);
|
||||
|
||||
/* Clear current HART IPI */
|
||||
sbi_platform_ipi_clear(plat, hartid);
|
||||
}
|
||||
|
||||
void sbi_hart_wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
|
||||
{
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
int max_hart = sbi_platform_hart_count(plat);
|
||||
|
||||
/* Acquire coldboot lock */
|
||||
spin_lock(&coldboot_lock);
|
||||
|
||||
/* Mark coldboot done */
|
||||
coldboot_done = 1;
|
||||
|
||||
/* Send an IPI to all HARTs waiting for coldboot */
|
||||
for (int i = 0; i < max_hart; i++) {
|
||||
if ((i != hartid) && (coldboot_wait_bitmap & (1UL << i)))
|
||||
sbi_platform_ipi_send(plat, i);
|
||||
}
|
||||
|
||||
/* Release coldboot lock */
|
||||
spin_unlock(&coldboot_lock);
|
||||
}
|
||||
|
@@ -9,67 +9,127 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* Instruction encoding of hfence.gvma is:
|
||||
* HFENCE.GVMA rs1, rs2
|
||||
* HFENCE.GVMA zero, rs2
|
||||
* HFENCE.GVMA rs1
|
||||
* HFENCE.GVMA
|
||||
*
|
||||
* rs1!=zero and rs2!=zero ==> HFENCE.GVMA rs1, rs2
|
||||
* rs1==zero and rs2!=zero ==> HFENCE.GVMA zero, rs2
|
||||
* rs1!=zero and rs2==zero ==> HFENCE.GVMA rs1
|
||||
* rs1==zero and rs2==zero ==> HFENCE.GVMA
|
||||
*
|
||||
* Instruction encoding of HFENCE.GVMA is:
|
||||
* 0110001 rs2(5) rs1(5) 000 00000 1110011
|
||||
*/
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_gvma_vmid_gpa
|
||||
__sbi_hfence_gvma_vmid_gpa:
|
||||
/* hfence.gvma a1, a0 */
|
||||
.word 0x62a60073
|
||||
/*
|
||||
* rs1 = a0 (GPA)
|
||||
* rs2 = a1 (VMID)
|
||||
* HFENCE.GVMA a0, a1
|
||||
* 0110001 01011 01010 000 00000 1110011
|
||||
*/
|
||||
.word 0x62b50073
|
||||
ret
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_gvma_vmid
|
||||
__sbi_hfence_gvma_vmid:
|
||||
/* hfence.gvma zero, a0 */
|
||||
/*
|
||||
* rs1 = zero
|
||||
* rs2 = a0 (VMID)
|
||||
* HFENCE.GVMA zero, a0
|
||||
* 0110001 01010 00000 000 00000 1110011
|
||||
*/
|
||||
.word 0x62a00073
|
||||
ret
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_gvma_gpa
|
||||
__sbi_hfence_gvma_gpa:
|
||||
/* hfence.gvma a0 */
|
||||
/*
|
||||
* rs1 = a0 (GPA)
|
||||
* rs2 = zero
|
||||
* HFENCE.GVMA a0
|
||||
* 0110001 00000 01010 000 00000 1110011
|
||||
*/
|
||||
.word 0x62050073
|
||||
ret
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_gvma_all
|
||||
__sbi_hfence_gvma_all:
|
||||
/* hfence.gvma */
|
||||
/*
|
||||
* rs1 = zero
|
||||
* rs2 = zero
|
||||
* HFENCE.GVMA
|
||||
* 0110001 00000 00000 000 00000 1110011
|
||||
*/
|
||||
.word 0x62000073
|
||||
ret
|
||||
|
||||
/*
|
||||
* Instruction encoding of hfence.bvma is:
|
||||
* HFENCE.VVMA rs1, rs2
|
||||
* HFENCE.VVMA zero, rs2
|
||||
* HFENCE.VVMA rs1
|
||||
* HFENCE.VVMA
|
||||
*
|
||||
* rs1!=zero and rs2!=zero ==> HFENCE.VVMA rs1, rs2
|
||||
* rs1==zero and rs2!=zero ==> HFENCE.VVMA zero, rs2
|
||||
* rs1!=zero and rs2==zero ==> HFENCE.VVMA rs1
|
||||
* rs1==zero and rs2==zero ==> HFENCE.vVMA
|
||||
*
|
||||
* Instruction encoding of HFENCE.VVMA is:
|
||||
* 0010001 rs2(5) rs1(5) 000 00000 1110011
|
||||
*/
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_vvma_asid_va
|
||||
__sbi_hfence_vvma_asid_va:
|
||||
/* hfence.bvma a1, a0 */
|
||||
.word 0x22a60073
|
||||
/*
|
||||
* rs1 = a0 (VA)
|
||||
* rs2 = a1 (ASID)
|
||||
* HFENCE.VVMA a0, a1
|
||||
* 0010001 01011 01010 000 00000 1110011
|
||||
*/
|
||||
.word 0x22b50073
|
||||
ret
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_vvma_asid
|
||||
__sbi_hfence_vvma_asid:
|
||||
/* hfence.bvma zero, a0 */
|
||||
/*
|
||||
* rs1 = zero
|
||||
* rs2 = a0 (ASID)
|
||||
* HFENCE.VVMA zero, a0
|
||||
* 0010001 01010 00000 000 00000 1110011
|
||||
*/
|
||||
.word 0x22a00073
|
||||
ret
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_vvma_va
|
||||
__sbi_hfence_vvma_va:
|
||||
/* hfence.bvma a0 */
|
||||
/*
|
||||
* rs1 = a0 (VA)
|
||||
* rs2 = zero
|
||||
* HFENCE.VVMA zero, a0
|
||||
* 0010001 00000 01010 000 00000 1110011
|
||||
*/
|
||||
.word 0x22050073
|
||||
ret
|
||||
|
||||
.align 3
|
||||
.global __sbi_hfence_vvma_all
|
||||
__sbi_hfence_vvma_all:
|
||||
/* hfence.bvma */
|
||||
/*
|
||||
* rs1 = zero
|
||||
* rs2 = zero
|
||||
* HFENCE.VVMA
|
||||
* 0010001 00000 00000 000 00000 1110011
|
||||
*/
|
||||
.word 0x22000073
|
||||
ret
|
||||
|
291
lib/sbi/sbi_hsm.c
Normal file
291
lib/sbi/sbi_hsm.c
Normal file
@@ -0,0 +1,291 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/riscv_barrier.h>
|
||||
#include <sbi/riscv_encoding.h>
|
||||
#include <sbi/riscv_atomic.h>
|
||||
#include <sbi/sbi_bitops.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_ecall_interface.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_hartmask.h>
|
||||
#include <sbi/sbi_hsm.h>
|
||||
#include <sbi/sbi_init.h>
|
||||
#include <sbi/sbi_ipi.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_system.h>
|
||||
#include <sbi/sbi_timer.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
|
||||
static unsigned long hart_data_offset;
|
||||
|
||||
/** Per hart specific data to manage state transition **/
|
||||
struct sbi_hsm_data {
|
||||
atomic_t state;
|
||||
};
|
||||
|
||||
int sbi_hsm_hart_state_to_status(int state)
|
||||
{
|
||||
int ret;
|
||||
|
||||
switch (state) {
|
||||
case SBI_HART_STOPPED:
|
||||
ret = SBI_HSM_HART_STATUS_STOPPED;
|
||||
break;
|
||||
case SBI_HART_STOPPING:
|
||||
ret = SBI_HSM_HART_STATUS_STOP_PENDING;
|
||||
break;
|
||||
case SBI_HART_STARTING:
|
||||
ret = SBI_HSM_HART_STATUS_START_PENDING;
|
||||
break;
|
||||
case SBI_HART_STARTED:
|
||||
ret = SBI_HSM_HART_STATUS_STARTED;
|
||||
break;
|
||||
default:
|
||||
ret = SBI_EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int __sbi_hsm_hart_get_state(u32 hartid)
|
||||
{
|
||||
struct sbi_hsm_data *hdata;
|
||||
struct sbi_scratch *scratch;
|
||||
|
||||
scratch = sbi_hartid_to_scratch(hartid);
|
||||
if (!scratch)
|
||||
return SBI_HART_UNKNOWN;
|
||||
|
||||
hdata = sbi_scratch_offset_ptr(scratch, hart_data_offset);
|
||||
return atomic_read(&hdata->state);
|
||||
}
|
||||
|
||||
int sbi_hsm_hart_get_state(const struct sbi_domain *dom, u32 hartid)
|
||||
{
|
||||
if (!sbi_domain_is_assigned_hart(dom, hartid))
|
||||
return SBI_HART_UNKNOWN;
|
||||
|
||||
return __sbi_hsm_hart_get_state(hartid);
|
||||
}
|
||||
|
||||
static bool sbi_hsm_hart_started(const struct sbi_domain *dom, u32 hartid)
|
||||
{
|
||||
if (sbi_hsm_hart_get_state(dom, hartid) == SBI_HART_STARTED)
|
||||
return TRUE;
|
||||
else
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/**
|
||||
* Get ulong HART mask for given HART base ID
|
||||
* @param dom the domain to be used for output HART mask
|
||||
* @param hbase the HART base ID
|
||||
* @param out_hmask the output ulong HART mask
|
||||
* @return 0 on success and SBI_Exxx (< 0) on failure
|
||||
* Note: the output HART mask will be set to zero on failure as well.
|
||||
*/
|
||||
int sbi_hsm_hart_started_mask(const struct sbi_domain *dom,
|
||||
ulong hbase, ulong *out_hmask)
|
||||
{
|
||||
ulong i, hmask, dmask;
|
||||
ulong hend = sbi_scratch_last_hartid() + 1;
|
||||
|
||||
*out_hmask = 0;
|
||||
if (hend <= hbase)
|
||||
return SBI_EINVAL;
|
||||
if (BITS_PER_LONG < (hend - hbase))
|
||||
hend = hbase + BITS_PER_LONG;
|
||||
|
||||
dmask = sbi_domain_get_assigned_hartmask(dom, hbase);
|
||||
for (i = hbase; i < hend; i++) {
|
||||
hmask = 1UL << (i - hbase);
|
||||
if ((dmask & hmask) &&
|
||||
(__sbi_hsm_hart_get_state(i) == SBI_HART_STARTED))
|
||||
*out_hmask |= hmask;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sbi_hsm_prepare_next_jump(struct sbi_scratch *scratch, u32 hartid)
|
||||
{
|
||||
u32 oldstate;
|
||||
struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
|
||||
hart_data_offset);
|
||||
|
||||
oldstate = atomic_cmpxchg(&hdata->state, SBI_HART_STARTING,
|
||||
SBI_HART_STARTED);
|
||||
if (oldstate != SBI_HART_STARTING)
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
static void sbi_hsm_hart_wait(struct sbi_scratch *scratch, u32 hartid)
|
||||
{
|
||||
unsigned long saved_mie;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
|
||||
hart_data_offset);
|
||||
/* Save MIE CSR */
|
||||
saved_mie = csr_read(CSR_MIE);
|
||||
|
||||
/* Set MSIE bit to receive IPI */
|
||||
csr_set(CSR_MIE, MIP_MSIP);
|
||||
|
||||
/* Wait for hart_add call*/
|
||||
while (atomic_read(&hdata->state) != SBI_HART_STARTING) {
|
||||
wfi();
|
||||
};
|
||||
|
||||
/* Restore MIE CSR */
|
||||
csr_write(CSR_MIE, saved_mie);
|
||||
|
||||
/* Clear current HART IPI */
|
||||
sbi_platform_ipi_clear(plat, hartid);
|
||||
}
|
||||
|
||||
int sbi_hsm_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot)
|
||||
{
|
||||
u32 i;
|
||||
struct sbi_scratch *rscratch;
|
||||
struct sbi_hsm_data *hdata;
|
||||
|
||||
if (cold_boot) {
|
||||
hart_data_offset = sbi_scratch_alloc_offset(sizeof(*hdata),
|
||||
"HART_DATA");
|
||||
if (!hart_data_offset)
|
||||
return SBI_ENOMEM;
|
||||
|
||||
/* Initialize hart state data for every hart */
|
||||
for (i = 0; i <= sbi_scratch_last_hartid(); i++) {
|
||||
rscratch = sbi_hartid_to_scratch(i);
|
||||
if (!rscratch)
|
||||
continue;
|
||||
|
||||
hdata = sbi_scratch_offset_ptr(rscratch,
|
||||
hart_data_offset);
|
||||
ATOMIC_INIT(&hdata->state,
|
||||
(i == hartid) ? SBI_HART_STARTING : SBI_HART_STOPPED);
|
||||
}
|
||||
} else {
|
||||
sbi_hsm_hart_wait(scratch, hartid);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void __noreturn sbi_hsm_exit(struct sbi_scratch *scratch)
|
||||
{
|
||||
u32 hstate;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
|
||||
hart_data_offset);
|
||||
void (*jump_warmboot)(void) = (void (*)(void))scratch->warmboot_addr;
|
||||
|
||||
hstate = atomic_cmpxchg(&hdata->state, SBI_HART_STOPPING,
|
||||
SBI_HART_STOPPED);
|
||||
if (hstate != SBI_HART_STOPPING)
|
||||
goto fail_exit;
|
||||
|
||||
if (sbi_platform_has_hart_hotplug(plat)) {
|
||||
sbi_platform_hart_stop(plat);
|
||||
/* It should never reach here */
|
||||
goto fail_exit;
|
||||
}
|
||||
|
||||
/**
|
||||
* As platform is lacking support for hotplug, directly jump to warmboot
|
||||
* and wait for interrupts in warmboot. We do it preemptively in order
|
||||
* preserve the hart states and reuse the code path for hotplug.
|
||||
*/
|
||||
jump_warmboot();
|
||||
|
||||
fail_exit:
|
||||
/* It should never reach here */
|
||||
sbi_printf("ERR: Failed stop hart [%u]\n", current_hartid());
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
int sbi_hsm_hart_start(struct sbi_scratch *scratch,
|
||||
const struct sbi_domain *dom,
|
||||
u32 hartid, ulong saddr, ulong smode, ulong priv)
|
||||
{
|
||||
unsigned long init_count;
|
||||
unsigned int hstate;
|
||||
struct sbi_scratch *rscratch;
|
||||
struct sbi_hsm_data *hdata;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
/* For now, we only allow start mode to be S-mode or U-mode. */
|
||||
if (smode != PRV_S && smode != PRV_U)
|
||||
return SBI_EINVAL;
|
||||
if (dom && !sbi_domain_is_assigned_hart(dom, hartid))
|
||||
return SBI_EINVAL;
|
||||
if (dom && !sbi_domain_check_addr(dom, saddr, smode,
|
||||
SBI_DOMAIN_EXECUTE))
|
||||
return SBI_EINVAL;
|
||||
|
||||
rscratch = sbi_hartid_to_scratch(hartid);
|
||||
if (!rscratch)
|
||||
return SBI_EINVAL;
|
||||
hdata = sbi_scratch_offset_ptr(rscratch, hart_data_offset);
|
||||
hstate = atomic_cmpxchg(&hdata->state, SBI_HART_STOPPED,
|
||||
SBI_HART_STARTING);
|
||||
if (hstate == SBI_HART_STARTED)
|
||||
return SBI_EALREADY;
|
||||
|
||||
/**
|
||||
* if a hart is already transition to start or stop, another start call
|
||||
* is considered as invalid request.
|
||||
*/
|
||||
if (hstate != SBI_HART_STOPPED)
|
||||
return SBI_EINVAL;
|
||||
|
||||
init_count = sbi_init_count(hartid);
|
||||
rscratch->next_arg1 = priv;
|
||||
rscratch->next_addr = saddr;
|
||||
rscratch->next_mode = smode;
|
||||
|
||||
if (sbi_platform_has_hart_hotplug(plat) ||
|
||||
(sbi_platform_has_hart_secondary_boot(plat) && !init_count)) {
|
||||
return sbi_platform_hart_start(plat, hartid,
|
||||
scratch->warmboot_addr);
|
||||
} else {
|
||||
sbi_platform_ipi_send(plat, hartid);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sbi_hsm_hart_stop(struct sbi_scratch *scratch, bool exitnow)
|
||||
{
|
||||
int oldstate;
|
||||
u32 hartid = current_hartid();
|
||||
struct sbi_hsm_data *hdata = sbi_scratch_offset_ptr(scratch,
|
||||
hart_data_offset);
|
||||
|
||||
if (!sbi_hsm_hart_started(sbi_domain_thishart_ptr(), hartid))
|
||||
return SBI_EINVAL;
|
||||
|
||||
oldstate = atomic_cmpxchg(&hdata->state, SBI_HART_STARTED,
|
||||
SBI_HART_STOPPING);
|
||||
if (oldstate != SBI_HART_STARTED) {
|
||||
sbi_printf("%s: ERR: The hart is in invalid state [%u]\n",
|
||||
__func__, oldstate);
|
||||
return SBI_EDENIED;
|
||||
}
|
||||
|
||||
if (exitnow)
|
||||
sbi_exit(scratch);
|
||||
|
||||
return 0;
|
||||
}
|
@@ -9,57 +9,39 @@
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/riscv_encoding.h>
|
||||
#include <sbi/sbi_bits.h>
|
||||
#include <sbi/sbi_bitops.h>
|
||||
#include <sbi/sbi_emulate_csr.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_illegal_insn.h>
|
||||
#include <sbi/sbi_trap.h>
|
||||
#include <sbi/sbi_unpriv.h>
|
||||
|
||||
typedef int (*illegal_insn_func)(ulong insn, u32 hartid, ulong mcause,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch);
|
||||
typedef int (*illegal_insn_func)(ulong insn, struct sbi_trap_regs *regs);
|
||||
|
||||
static int truly_illegal_insn(ulong insn, u32 hartid, ulong mcause,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch)
|
||||
static int truly_illegal_insn(ulong insn, struct sbi_trap_regs *regs)
|
||||
{
|
||||
struct sbi_trap_info trap;
|
||||
|
||||
trap.epc = regs->mepc;
|
||||
trap.cause = mcause;
|
||||
trap.cause = CAUSE_ILLEGAL_INSTRUCTION;
|
||||
trap.tval = insn;
|
||||
trap.tval2 = 0;
|
||||
trap.tinst = 0;
|
||||
|
||||
return sbi_trap_redirect(regs, &trap, scratch);
|
||||
return sbi_trap_redirect(regs, &trap);
|
||||
}
|
||||
|
||||
static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch)
|
||||
static int system_opcode_insn(ulong insn, struct sbi_trap_regs *regs)
|
||||
{
|
||||
int do_write, rs1_num = (insn >> 15) & 0x1f;
|
||||
ulong rs1_val = GET_RS1(insn, regs);
|
||||
int csr_num = (u32)insn >> 20;
|
||||
ulong csr_val, new_csr_val;
|
||||
|
||||
/*
|
||||
* WFI always traps as illegal instruction when executed from
|
||||
* VS/VU mode so we just forward it to HS-mode.
|
||||
*/
|
||||
#if __riscv_xlen == 32
|
||||
if ((regs->mstatusH & MSTATUSH_MPV) &&
|
||||
#else
|
||||
if ((regs->mstatus & MSTATUS_MPV) &&
|
||||
#endif
|
||||
(insn & INSN_MASK_WFI) == INSN_MATCH_WFI)
|
||||
return truly_illegal_insn(insn, hartid, mcause,
|
||||
regs, scratch);
|
||||
/* TODO: Ensure that we got CSR read/write instruction */
|
||||
|
||||
if (sbi_emulate_csr_read(csr_num, hartid, regs, scratch, &csr_val))
|
||||
return truly_illegal_insn(insn, hartid, mcause,
|
||||
regs, scratch);
|
||||
if (sbi_emulate_csr_read(csr_num, regs, &csr_val))
|
||||
return truly_illegal_insn(insn, regs);
|
||||
|
||||
do_write = rs1_num;
|
||||
switch (GET_RM(insn)) {
|
||||
@@ -84,12 +66,11 @@ static int system_opcode_insn(ulong insn, u32 hartid, ulong mcause,
|
||||
new_csr_val = csr_val & ~rs1_num;
|
||||
break;
|
||||
default:
|
||||
return truly_illegal_insn(insn, hartid, mcause, regs, scratch);
|
||||
return truly_illegal_insn(insn, regs);
|
||||
};
|
||||
|
||||
if (do_write && sbi_emulate_csr_write(csr_num, hartid, regs,
|
||||
scratch, new_csr_val))
|
||||
return truly_illegal_insn(insn, hartid, mcause, regs, scratch);
|
||||
if (do_write && sbi_emulate_csr_write(csr_num, regs, new_csr_val))
|
||||
return truly_illegal_insn(insn, regs);
|
||||
|
||||
SET_RD(insn, regs, csr_val);
|
||||
|
||||
@@ -133,26 +114,30 @@ static illegal_insn_func illegal_insn_table[32] = {
|
||||
truly_illegal_insn /* 31 */
|
||||
};
|
||||
|
||||
int sbi_illegal_insn_handler(u32 hartid, ulong mcause, ulong insn,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch)
|
||||
int sbi_illegal_insn_handler(ulong insn, struct sbi_trap_regs *regs)
|
||||
{
|
||||
struct sbi_trap_info uptrap;
|
||||
|
||||
/*
|
||||
* We only deal with 32-bit (or longer) illegal instructions. If we
|
||||
* see instruction is zero OR instruction is 16-bit then we fetch and
|
||||
* check the instruction encoding using unprivilege access.
|
||||
*
|
||||
* The program counter (PC) in RISC-V world is always 2-byte aligned
|
||||
* so handling only 32-bit (or longer) illegal instructions also help
|
||||
* the case where MTVAL CSR contains instruction address for illegal
|
||||
* instruction trap.
|
||||
*/
|
||||
|
||||
if (unlikely((insn & 3) != 3)) {
|
||||
if (insn == 0) {
|
||||
insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
|
||||
if (uptrap.cause) {
|
||||
uptrap.epc = regs->mepc;
|
||||
return sbi_trap_redirect(regs, &uptrap,
|
||||
scratch);
|
||||
}
|
||||
insn = sbi_get_insn(regs->mepc, &uptrap);
|
||||
if (uptrap.cause) {
|
||||
uptrap.epc = regs->mepc;
|
||||
return sbi_trap_redirect(regs, &uptrap);
|
||||
}
|
||||
if ((insn & 3) != 3)
|
||||
return truly_illegal_insn(insn, hartid, mcause, regs,
|
||||
scratch);
|
||||
return truly_illegal_insn(insn, regs);
|
||||
}
|
||||
|
||||
return illegal_insn_table[(insn & 0x7c) >> 2](insn, hartid, mcause,
|
||||
regs, scratch);
|
||||
return illegal_insn_table[(insn & 0x7c) >> 2](insn, regs);
|
||||
}
|
||||
|
@@ -9,12 +9,18 @@
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/riscv_atomic.h>
|
||||
#include <sbi/riscv_barrier.h>
|
||||
#include <sbi/riscv_locks.h>
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_ecall.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_hartmask.h>
|
||||
#include <sbi/sbi_hsm.h>
|
||||
#include <sbi/sbi_ipi.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_system.h>
|
||||
#include <sbi/sbi_string.h>
|
||||
#include <sbi/sbi_timer.h>
|
||||
#include <sbi/sbi_tlb.h>
|
||||
#include <sbi/sbi_version.h>
|
||||
@@ -29,11 +35,10 @@
|
||||
" | |\n" \
|
||||
" |_|\n\n"
|
||||
|
||||
static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
|
||||
static void sbi_boot_print_banner(struct sbi_scratch *scratch)
|
||||
{
|
||||
int xlen;
|
||||
char str[64];
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
|
||||
return;
|
||||
|
||||
#ifdef OPENSBI_VERSION_GIT
|
||||
sbi_printf("\nOpenSBI %s\n", OPENSBI_VERSION_GIT);
|
||||
@@ -43,6 +48,52 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
|
||||
#endif
|
||||
|
||||
sbi_printf(BANNER);
|
||||
}
|
||||
|
||||
static void sbi_boot_print_general(struct sbi_scratch *scratch)
|
||||
{
|
||||
char str[128];
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
|
||||
return;
|
||||
|
||||
/* Platform details */
|
||||
sbi_printf("Platform Name : %s\n",
|
||||
sbi_platform_name(plat));
|
||||
sbi_platform_get_features_str(plat, str, sizeof(str));
|
||||
sbi_printf("Platform Features : %s\n", str);
|
||||
sbi_printf("Platform HART Count : %u\n",
|
||||
sbi_platform_hart_count(plat));
|
||||
|
||||
/* Firmware details */
|
||||
sbi_printf("Firmware Base : 0x%lx\n", scratch->fw_start);
|
||||
sbi_printf("Firmware Size : %d KB\n",
|
||||
(u32)(scratch->fw_size / 1024));
|
||||
|
||||
/* SBI details */
|
||||
sbi_printf("Runtime SBI Version : %d.%d\n",
|
||||
sbi_ecall_version_major(), sbi_ecall_version_minor());
|
||||
sbi_printf("\n");
|
||||
}
|
||||
|
||||
static void sbi_boot_print_domains(struct sbi_scratch *scratch)
|
||||
{
|
||||
if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
|
||||
return;
|
||||
|
||||
/* Domain details */
|
||||
sbi_domain_dump_all(" ");
|
||||
}
|
||||
|
||||
static void sbi_boot_print_hart(struct sbi_scratch *scratch, u32 hartid)
|
||||
{
|
||||
int xlen;
|
||||
char str[128];
|
||||
const struct sbi_domain *dom = sbi_domain_thishart_ptr();
|
||||
|
||||
if (scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS)
|
||||
return;
|
||||
|
||||
/* Determine MISA XLEN and MISA string */
|
||||
xlen = misa_xlen();
|
||||
@@ -50,26 +101,95 @@ static void sbi_boot_prints(struct sbi_scratch *scratch, u32 hartid)
|
||||
sbi_printf("Error %d getting MISA XLEN\n", xlen);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
xlen = 16 * (1 << xlen);
|
||||
misa_string(str, sizeof(str));
|
||||
|
||||
/* Platform details */
|
||||
sbi_printf("Platform Name : %s\n", sbi_platform_name(plat));
|
||||
sbi_printf("Platform HART Features : RV%d%s\n", xlen, str);
|
||||
sbi_printf("Platform Max HARTs : %d\n",
|
||||
sbi_platform_hart_count(plat));
|
||||
sbi_printf("Current Hart : %u\n", hartid);
|
||||
/* Firmware details */
|
||||
sbi_printf("Firmware Base : 0x%lx\n", scratch->fw_start);
|
||||
sbi_printf("Firmware Size : %d KB\n",
|
||||
(u32)(scratch->fw_size / 1024));
|
||||
/* Generic details */
|
||||
sbi_printf("Runtime SBI Version : %d.%d\n",
|
||||
sbi_ecall_version_major(), sbi_ecall_version_minor());
|
||||
sbi_printf("\n");
|
||||
/* Boot HART details */
|
||||
sbi_printf("Boot HART ID : %u\n", hartid);
|
||||
sbi_printf("Boot HART Domain : %s\n", dom->name);
|
||||
misa_string(xlen, str, sizeof(str));
|
||||
sbi_printf("Boot HART ISA : %s\n", str);
|
||||
sbi_hart_get_features_str(scratch, str, sizeof(str));
|
||||
sbi_printf("Boot HART Features : %s\n", str);
|
||||
sbi_printf("Boot HART PMP Count : %d\n",
|
||||
sbi_hart_pmp_count(scratch));
|
||||
sbi_printf("Boot HART PMP Granularity : %lu\n",
|
||||
sbi_hart_pmp_granularity(scratch));
|
||||
sbi_printf("Boot HART PMP Address Bits: %d\n",
|
||||
sbi_hart_pmp_addrbits(scratch));
|
||||
sbi_printf("Boot HART MHPM Count : %d\n",
|
||||
sbi_hart_mhpm_count(scratch));
|
||||
sbi_printf("Boot HART MHPM Count : %d\n",
|
||||
sbi_hart_mhpm_count(scratch));
|
||||
sbi_hart_delegation_dump(scratch, "Boot HART ", " ");
|
||||
}
|
||||
|
||||
sbi_hart_delegation_dump(scratch);
|
||||
sbi_hart_pmp_dump(scratch);
|
||||
static spinlock_t coldboot_lock = SPIN_LOCK_INITIALIZER;
|
||||
static struct sbi_hartmask coldboot_wait_hmask = { 0 };
|
||||
|
||||
static unsigned long coldboot_done;
|
||||
|
||||
static void wait_for_coldboot(struct sbi_scratch *scratch, u32 hartid)
|
||||
{
|
||||
unsigned long saved_mie, cmip;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
/* Save MIE CSR */
|
||||
saved_mie = csr_read(CSR_MIE);
|
||||
|
||||
/* Set MSIE bit to receive IPI */
|
||||
csr_set(CSR_MIE, MIP_MSIP);
|
||||
|
||||
/* Acquire coldboot lock */
|
||||
spin_lock(&coldboot_lock);
|
||||
|
||||
/* Mark current HART as waiting */
|
||||
sbi_hartmask_set_hart(hartid, &coldboot_wait_hmask);
|
||||
|
||||
/* Release coldboot lock */
|
||||
spin_unlock(&coldboot_lock);
|
||||
|
||||
/* Wait for coldboot to finish using WFI */
|
||||
while (!__smp_load_acquire(&coldboot_done)) {
|
||||
do {
|
||||
wfi();
|
||||
cmip = csr_read(CSR_MIP);
|
||||
} while (!(cmip & MIP_MSIP));
|
||||
};
|
||||
|
||||
/* Acquire coldboot lock */
|
||||
spin_lock(&coldboot_lock);
|
||||
|
||||
/* Unmark current HART as waiting */
|
||||
sbi_hartmask_clear_hart(hartid, &coldboot_wait_hmask);
|
||||
|
||||
/* Release coldboot lock */
|
||||
spin_unlock(&coldboot_lock);
|
||||
|
||||
/* Restore MIE CSR */
|
||||
csr_write(CSR_MIE, saved_mie);
|
||||
|
||||
/* Clear current HART IPI */
|
||||
sbi_platform_ipi_clear(plat, hartid);
|
||||
}
|
||||
|
||||
static void wake_coldboot_harts(struct sbi_scratch *scratch, u32 hartid)
|
||||
{
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
/* Mark coldboot done */
|
||||
__smp_store_release(&coldboot_done, 1);
|
||||
|
||||
/* Acquire coldboot lock */
|
||||
spin_lock(&coldboot_lock);
|
||||
|
||||
/* Send an IPI to all HARTs waiting for coldboot */
|
||||
for (int i = 0; i <= sbi_scratch_last_hartid(); i++) {
|
||||
if ((i != hartid) &&
|
||||
sbi_hartmask_test_hart(i, &coldboot_wait_hmask))
|
||||
sbi_platform_ipi_send(plat, i);
|
||||
}
|
||||
|
||||
/* Release coldboot lock */
|
||||
spin_unlock(&coldboot_lock);
|
||||
}
|
||||
|
||||
static unsigned long init_count_offset;
|
||||
@@ -80,16 +200,30 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
|
||||
unsigned long *init_count;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
/* Note: This has to be first thing in coldboot init sequence */
|
||||
rc = sbi_scratch_init(scratch);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
/* Note: This has to be second thing in coldboot init sequence */
|
||||
rc = sbi_domain_init(scratch, hartid);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
init_count_offset = sbi_scratch_alloc_offset(__SIZEOF_POINTER__,
|
||||
"INIT_COUNT");
|
||||
if (!init_count_offset)
|
||||
sbi_hart_hang();
|
||||
|
||||
rc = sbi_system_early_init(scratch, TRUE);
|
||||
rc = sbi_hsm_init(scratch, hartid, TRUE);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
rc = sbi_hart_init(scratch, hartid, TRUE);
|
||||
rc = sbi_platform_early_init(plat, TRUE);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
rc = sbi_hart_init(scratch, TRUE);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
@@ -97,40 +231,82 @@ static void __noreturn init_coldboot(struct sbi_scratch *scratch, u32 hartid)
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
sbi_boot_print_banner(scratch);
|
||||
|
||||
rc = sbi_platform_irqchip_init(plat, TRUE);
|
||||
if (rc)
|
||||
if (rc) {
|
||||
sbi_printf("%s: platform irqchip init failed (error %d)\n",
|
||||
__func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
rc = sbi_ipi_init(scratch, TRUE);
|
||||
if (rc)
|
||||
if (rc) {
|
||||
sbi_printf("%s: ipi init failed (error %d)\n", __func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
rc = sbi_tlb_init(scratch, TRUE);
|
||||
if (rc)
|
||||
if (rc) {
|
||||
sbi_printf("%s: tlb init failed (error %d)\n", __func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
rc = sbi_timer_init(scratch, TRUE);
|
||||
if (rc)
|
||||
if (rc) {
|
||||
sbi_printf("%s: timer init failed (error %d)\n", __func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
rc = sbi_ecall_init();
|
||||
if (rc)
|
||||
if (rc) {
|
||||
sbi_printf("%s: ecall init failed (error %d)\n", __func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
rc = sbi_system_final_init(scratch, TRUE);
|
||||
if (rc)
|
||||
sbi_boot_print_general(scratch);
|
||||
|
||||
/*
|
||||
* Note: Finalize domains after HSM initialization so that we
|
||||
* can startup non-root domains.
|
||||
* Note: Finalize domains before HART PMP configuration so
|
||||
* that we use correct domain for configuring PMP.
|
||||
*/
|
||||
rc = sbi_domain_finalize(scratch, hartid);
|
||||
if (rc) {
|
||||
sbi_printf("%s: domain finalize failed (error %d)\n",
|
||||
__func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
if (!(scratch->options & SBI_SCRATCH_NO_BOOT_PRINTS))
|
||||
sbi_boot_prints(scratch, hartid);
|
||||
sbi_boot_print_domains(scratch);
|
||||
|
||||
sbi_hart_wake_coldboot_harts(scratch, hartid);
|
||||
rc = sbi_hart_pmp_configure(scratch);
|
||||
if (rc) {
|
||||
sbi_printf("%s: PMP configure failed (error %d)\n",
|
||||
__func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
sbi_hart_mark_available(hartid);
|
||||
/*
|
||||
* Note: Platform final initialization should be last so that
|
||||
* it sees correct domain assignment and PMP configuration.
|
||||
*/
|
||||
rc = sbi_platform_final_init(plat, TRUE);
|
||||
if (rc) {
|
||||
sbi_printf("%s: platform final init failed (error %d)\n",
|
||||
__func__, rc);
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
sbi_boot_print_hart(scratch, hartid);
|
||||
|
||||
wake_coldboot_harts(scratch, hartid);
|
||||
|
||||
init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
|
||||
(*init_count)++;
|
||||
|
||||
sbi_hsm_prepare_next_jump(scratch, hartid);
|
||||
sbi_hart_switch_mode(hartid, scratch->next_arg1, scratch->next_addr,
|
||||
scratch->next_mode, FALSE);
|
||||
}
|
||||
@@ -141,16 +317,20 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
|
||||
unsigned long *init_count;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
sbi_hart_wait_for_coldboot(scratch, hartid);
|
||||
wait_for_coldboot(scratch, hartid);
|
||||
|
||||
if (!init_count_offset)
|
||||
sbi_hart_hang();
|
||||
|
||||
rc = sbi_system_early_init(scratch, FALSE);
|
||||
rc = sbi_hsm_init(scratch, hartid, FALSE);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
rc = sbi_hart_init(scratch, hartid, FALSE);
|
||||
rc = sbi_platform_early_init(plat, FALSE);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
rc = sbi_hart_init(scratch, FALSE);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
@@ -170,15 +350,18 @@ static void __noreturn init_warmboot(struct sbi_scratch *scratch, u32 hartid)
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
rc = sbi_system_final_init(scratch, FALSE);
|
||||
rc = sbi_hart_pmp_configure(scratch);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
sbi_hart_mark_available(hartid);
|
||||
rc = sbi_platform_final_init(plat, FALSE);
|
||||
if (rc)
|
||||
sbi_hart_hang();
|
||||
|
||||
init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
|
||||
(*init_count)++;
|
||||
|
||||
sbi_hsm_prepare_next_jump(scratch, hartid);
|
||||
sbi_hart_switch_mode(hartid, scratch->next_arg1,
|
||||
scratch->next_addr,
|
||||
scratch->next_mode, FALSE);
|
||||
@@ -200,14 +383,42 @@ static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0);
|
||||
*/
|
||||
void __noreturn sbi_init(struct sbi_scratch *scratch)
|
||||
{
|
||||
bool next_mode_supported = FALSE;
|
||||
bool coldboot = FALSE;
|
||||
u32 hartid = sbi_current_hartid();
|
||||
u32 hartid = current_hartid();
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
if (sbi_platform_hart_disabled(plat, hartid))
|
||||
if ((SBI_HARTMASK_MAX_BITS <= hartid) ||
|
||||
sbi_platform_hart_invalid(plat, hartid))
|
||||
sbi_hart_hang();
|
||||
|
||||
if (atomic_add_return(&coldboot_lottery, 1) == 1)
|
||||
switch (scratch->next_mode) {
|
||||
case PRV_M:
|
||||
next_mode_supported = TRUE;
|
||||
break;
|
||||
case PRV_S:
|
||||
if (misa_extension('S'))
|
||||
next_mode_supported = TRUE;
|
||||
break;
|
||||
case PRV_U:
|
||||
if (misa_extension('U'))
|
||||
next_mode_supported = TRUE;
|
||||
break;
|
||||
default:
|
||||
sbi_hart_hang();
|
||||
}
|
||||
|
||||
/*
|
||||
* Only the HART supporting privilege mode specified in the
|
||||
* scratch->next_mode should be allowed to become the coldboot
|
||||
* HART because the coldboot HART will be directly jumping to
|
||||
* the next booting stage.
|
||||
*
|
||||
* We use a lottery mechanism to select coldboot HART among
|
||||
* HARTs which satisfy above condition.
|
||||
*/
|
||||
|
||||
if (next_mode_supported && atomic_xchg(&coldboot_lottery, 1) == 0)
|
||||
coldboot = TRUE;
|
||||
|
||||
if (coldboot)
|
||||
@@ -221,11 +432,13 @@ unsigned long sbi_init_count(u32 hartid)
|
||||
struct sbi_scratch *scratch;
|
||||
unsigned long *init_count;
|
||||
|
||||
if (sbi_platform_hart_count(sbi_platform_thishart_ptr()) <= hartid ||
|
||||
!init_count_offset)
|
||||
if (!init_count_offset)
|
||||
return 0;
|
||||
|
||||
scratch = sbi_hartid_to_scratch(hartid);
|
||||
if (!scratch)
|
||||
return 0;
|
||||
|
||||
scratch = sbi_hart_id_to_scratch(sbi_scratch_thishart_ptr(), hartid);
|
||||
init_count = sbi_scratch_offset_ptr(scratch, init_count_offset);
|
||||
|
||||
return *init_count;
|
||||
@@ -242,14 +455,12 @@ unsigned long sbi_init_count(u32 hartid)
|
||||
*/
|
||||
void __noreturn sbi_exit(struct sbi_scratch *scratch)
|
||||
{
|
||||
u32 hartid = sbi_current_hartid();
|
||||
u32 hartid = current_hartid();
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
if (sbi_platform_hart_disabled(plat, hartid))
|
||||
if (sbi_platform_hart_invalid(plat, hartid))
|
||||
sbi_hart_hang();
|
||||
|
||||
sbi_hart_unmark_available(hartid);
|
||||
|
||||
sbi_platform_early_exit(plat);
|
||||
|
||||
sbi_timer_exit(scratch);
|
||||
@@ -260,5 +471,5 @@ void __noreturn sbi_exit(struct sbi_scratch *scratch)
|
||||
|
||||
sbi_platform_final_exit(plat);
|
||||
|
||||
sbi_hart_hang();
|
||||
sbi_hsm_exit(scratch);
|
||||
}
|
||||
|
@@ -12,8 +12,10 @@
|
||||
#include <sbi/riscv_atomic.h>
|
||||
#include <sbi/riscv_barrier.h>
|
||||
#include <sbi/sbi_bitops.h>
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_hsm.h>
|
||||
#include <sbi/sbi_init.h>
|
||||
#include <sbi/sbi_ipi.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
@@ -36,16 +38,14 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
|
||||
const struct sbi_ipi_event_ops *ipi_ops;
|
||||
|
||||
if ((SBI_IPI_EVENT_MAX <= event) ||
|
||||
!ipi_ops_array[event] ||
|
||||
sbi_platform_hart_disabled(plat, remote_hartid))
|
||||
!ipi_ops_array[event])
|
||||
return SBI_EINVAL;
|
||||
ipi_ops = ipi_ops_array[event];
|
||||
|
||||
/*
|
||||
* Set IPI type on remote hart's scratch area and
|
||||
* trigger the interrupt
|
||||
*/
|
||||
remote_scratch = sbi_hart_id_to_scratch(scratch, remote_hartid);
|
||||
remote_scratch = sbi_hartid_to_scratch(remote_hartid);
|
||||
if (!remote_scratch)
|
||||
return SBI_EINVAL;
|
||||
|
||||
ipi_data = sbi_scratch_offset_ptr(remote_scratch, ipi_data_off);
|
||||
|
||||
if (ipi_ops->update) {
|
||||
@@ -55,6 +55,10 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set IPI type on remote hart's scratch area and
|
||||
* trigger the interrupt
|
||||
*/
|
||||
atomic_raw_set_bit(event, &ipi_data->ipi_type);
|
||||
smp_wmb();
|
||||
sbi_platform_ipi_send(plat, remote_hartid);
|
||||
@@ -70,36 +74,36 @@ static int sbi_ipi_send(struct sbi_scratch *scratch, u32 remote_hartid,
|
||||
* set to all online harts if the intention is to send IPIs to all the harts.
|
||||
* If hmask is zero, no IPIs will be sent.
|
||||
*/
|
||||
int sbi_ipi_send_many(struct sbi_scratch *scratch, ulong hmask, ulong hbase,
|
||||
u32 event, void *data)
|
||||
int sbi_ipi_send_many(ulong hmask, ulong hbase, u32 event, void *data)
|
||||
{
|
||||
int rc;
|
||||
ulong i, m;
|
||||
ulong mask = sbi_hart_available_mask();
|
||||
ulong tempmask;
|
||||
unsigned long last_bit = __fls(mask);
|
||||
struct sbi_domain *dom = sbi_domain_thishart_ptr();
|
||||
struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
|
||||
|
||||
if (hbase != -1UL) {
|
||||
if (hbase > last_bit)
|
||||
/* hart base is not available */
|
||||
return SBI_EINVAL;
|
||||
/**
|
||||
* FIXME: This check is valid only ULONG size. This is okay for
|
||||
* now as avaialble hart mask can support upto ULONG size only.
|
||||
*/
|
||||
tempmask = hmask << hbase;
|
||||
tempmask = ~mask & tempmask;
|
||||
if (tempmask)
|
||||
/* at least one of the hart in hmask is not available */
|
||||
return SBI_EINVAL;
|
||||
rc = sbi_hsm_hart_started_mask(dom, hbase, &m);
|
||||
if (rc)
|
||||
return rc;
|
||||
m &= hmask;
|
||||
|
||||
mask &= (hmask << hbase);
|
||||
/* Send IPIs */
|
||||
for (i = hbase; m; i++, m >>= 1) {
|
||||
if (m & 1UL)
|
||||
sbi_ipi_send(scratch, i, event, data);
|
||||
}
|
||||
} else {
|
||||
hbase = 0;
|
||||
while (!sbi_hsm_hart_started_mask(dom, hbase, &m)) {
|
||||
/* Send IPIs */
|
||||
for (i = hbase; m; i++, m >>= 1) {
|
||||
if (m & 1UL)
|
||||
sbi_ipi_send(scratch, i, event, data);
|
||||
}
|
||||
hbase += BITS_PER_LONG;
|
||||
}
|
||||
}
|
||||
|
||||
/* Send IPIs to every other hart on the set */
|
||||
for (i = 0, m = mask; m; i++, m >>= 1)
|
||||
if (m & 1UL)
|
||||
sbi_ipi_send(scratch, i, event, data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -141,19 +145,19 @@ static struct sbi_ipi_event_ops ipi_smode_ops = {
|
||||
|
||||
static u32 ipi_smode_event = SBI_IPI_EVENT_MAX;
|
||||
|
||||
int sbi_ipi_send_smode(struct sbi_scratch *scratch, ulong hmask, ulong hbase)
|
||||
int sbi_ipi_send_smode(ulong hmask, ulong hbase)
|
||||
{
|
||||
return sbi_ipi_send_many(scratch, hmask, hbase, ipi_smode_event, NULL);
|
||||
return sbi_ipi_send_many(hmask, hbase, ipi_smode_event, NULL);
|
||||
}
|
||||
|
||||
void sbi_ipi_clear_smode(struct sbi_scratch *scratch)
|
||||
void sbi_ipi_clear_smode(void)
|
||||
{
|
||||
csr_clear(CSR_MIP, MIP_SSIP);
|
||||
}
|
||||
|
||||
static void sbi_ipi_process_halt(struct sbi_scratch *scratch)
|
||||
{
|
||||
sbi_exit(scratch);
|
||||
sbi_hsm_hart_stop(scratch, TRUE);
|
||||
}
|
||||
|
||||
static struct sbi_ipi_event_ops ipi_halt_ops = {
|
||||
@@ -163,21 +167,22 @@ static struct sbi_ipi_event_ops ipi_halt_ops = {
|
||||
|
||||
static u32 ipi_halt_event = SBI_IPI_EVENT_MAX;
|
||||
|
||||
int sbi_ipi_send_halt(struct sbi_scratch *scratch, ulong hmask, ulong hbase)
|
||||
int sbi_ipi_send_halt(ulong hmask, ulong hbase)
|
||||
{
|
||||
return sbi_ipi_send_many(scratch, hmask, hbase, ipi_halt_event, NULL);
|
||||
return sbi_ipi_send_many(hmask, hbase, ipi_halt_event, NULL);
|
||||
}
|
||||
|
||||
void sbi_ipi_process(struct sbi_scratch *scratch)
|
||||
void sbi_ipi_process(void)
|
||||
{
|
||||
unsigned long ipi_type;
|
||||
unsigned int ipi_event;
|
||||
const struct sbi_ipi_event_ops *ipi_ops;
|
||||
struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
struct sbi_ipi_data *ipi_data =
|
||||
sbi_scratch_offset_ptr(scratch, ipi_data_off);
|
||||
|
||||
u32 hartid = sbi_current_hartid();
|
||||
u32 hartid = current_hartid();
|
||||
sbi_platform_ipi_clear(plat, hartid);
|
||||
|
||||
ipi_type = atomic_raw_xchg_ulong(&ipi_data->ipi_type, 0);
|
||||
@@ -242,7 +247,7 @@ void sbi_ipi_exit(struct sbi_scratch *scratch)
|
||||
csr_clear(CSR_MIE, MIP_MSIP);
|
||||
|
||||
/* Process pending IPIs */
|
||||
sbi_ipi_process(scratch);
|
||||
sbi_ipi_process();
|
||||
|
||||
/* Platform exit */
|
||||
sbi_platform_ipi_exit(sbi_platform_ptr(scratch));
|
||||
|
23
lib/sbi/sbi_math.c
Normal file
23
lib/sbi/sbi_math.c
Normal file
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Common helper functions used across OpenSBI project.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
unsigned long log2roundup(unsigned long x)
|
||||
{
|
||||
unsigned long ret = 0;
|
||||
|
||||
while (ret < __riscv_xlen) {
|
||||
if (x <= (1UL << ret))
|
||||
break;
|
||||
ret++;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
@@ -21,12 +21,10 @@ union reg_data {
|
||||
u64 data_u64;
|
||||
};
|
||||
|
||||
int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
|
||||
ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch)
|
||||
int sbi_misaligned_load_handler(ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs)
|
||||
{
|
||||
ulong insn;
|
||||
ulong insn, insn_len;
|
||||
union reg_data val;
|
||||
struct sbi_trap_info uptrap;
|
||||
int i, fp = 0, shift = 0, len = 0;
|
||||
@@ -37,16 +35,18 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
|
||||
* transformed instruction or custom instruction.
|
||||
*/
|
||||
insn = tinst | INSN_16BIT_MASK;
|
||||
insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
|
||||
} else {
|
||||
/*
|
||||
* Bit[0] == 0 implies trapped instruction value is
|
||||
* zero or special value.
|
||||
*/
|
||||
insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
|
||||
insn = sbi_get_insn(regs->mepc, &uptrap);
|
||||
if (uptrap.cause) {
|
||||
uptrap.epc = regs->mepc;
|
||||
return sbi_trap_redirect(regs, &uptrap, scratch);
|
||||
return sbi_trap_redirect(regs, &uptrap);
|
||||
}
|
||||
insn_len = INSN_LEN(insn);
|
||||
}
|
||||
|
||||
if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {
|
||||
@@ -72,7 +72,6 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
|
||||
shift = 8 * (sizeof(ulong) - len);
|
||||
} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {
|
||||
len = 2;
|
||||
#ifdef __riscv_compressed
|
||||
#if __riscv_xlen >= 64
|
||||
} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {
|
||||
len = 8;
|
||||
@@ -108,29 +107,28 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
|
||||
fp = 1;
|
||||
len = 4;
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
} else {
|
||||
uptrap.epc = regs->mepc;
|
||||
uptrap.cause = mcause;
|
||||
uptrap.cause = CAUSE_MISALIGNED_LOAD;
|
||||
uptrap.tval = addr;
|
||||
uptrap.tval2 = tval2;
|
||||
uptrap.tinst = tinst;
|
||||
return sbi_trap_redirect(regs, &uptrap, scratch);
|
||||
return sbi_trap_redirect(regs, &uptrap);
|
||||
}
|
||||
|
||||
val.data_u64 = 0;
|
||||
for (i = 0; i < len; i++) {
|
||||
val.data_bytes[i] = sbi_load_u8((void *)(addr + i),
|
||||
scratch, &uptrap);
|
||||
&uptrap);
|
||||
if (uptrap.cause) {
|
||||
uptrap.epc = regs->mepc;
|
||||
return sbi_trap_redirect(regs, &uptrap, scratch);
|
||||
return sbi_trap_redirect(regs, &uptrap);
|
||||
}
|
||||
}
|
||||
|
||||
if (!fp)
|
||||
SET_RD(insn, regs, val.data_ulong << shift >> shift);
|
||||
SET_RD(insn, regs, ((long)(val.data_ulong << shift)) >> shift);
|
||||
#ifdef __riscv_flen
|
||||
else if (len == 8)
|
||||
SET_F64_RD(insn, regs, val.data_u64);
|
||||
@@ -138,17 +136,15 @@ int sbi_misaligned_load_handler(u32 hartid, ulong mcause,
|
||||
SET_F32_RD(insn, regs, val.data_ulong);
|
||||
#endif
|
||||
|
||||
regs->mepc += INSN_LEN(insn);
|
||||
regs->mepc += insn_len;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
|
||||
ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs,
|
||||
struct sbi_scratch *scratch)
|
||||
int sbi_misaligned_store_handler(ulong addr, ulong tval2, ulong tinst,
|
||||
struct sbi_trap_regs *regs)
|
||||
{
|
||||
ulong insn;
|
||||
ulong insn, insn_len;
|
||||
union reg_data val;
|
||||
struct sbi_trap_info uptrap;
|
||||
int i, len = 0;
|
||||
@@ -159,16 +155,18 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
|
||||
* transformed instruction or custom instruction.
|
||||
*/
|
||||
insn = tinst | INSN_16BIT_MASK;
|
||||
insn_len = (tinst & 0x2) ? INSN_LEN(insn) : 2;
|
||||
} else {
|
||||
/*
|
||||
* Bit[0] == 0 implies trapped instruction value is
|
||||
* zero or special value.
|
||||
*/
|
||||
insn = sbi_get_insn(regs->mepc, scratch, &uptrap);
|
||||
insn = sbi_get_insn(regs->mepc, &uptrap);
|
||||
if (uptrap.cause) {
|
||||
uptrap.epc = regs->mepc;
|
||||
return sbi_trap_redirect(regs, &uptrap, scratch);
|
||||
return sbi_trap_redirect(regs, &uptrap);
|
||||
}
|
||||
insn_len = INSN_LEN(insn);
|
||||
}
|
||||
|
||||
val.data_ulong = GET_RS2(insn, regs);
|
||||
@@ -189,7 +187,6 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
|
||||
#endif
|
||||
} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {
|
||||
len = 2;
|
||||
#ifdef __riscv_compressed
|
||||
#if __riscv_xlen >= 64
|
||||
} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {
|
||||
len = 8;
|
||||
@@ -221,27 +218,26 @@ int sbi_misaligned_store_handler(u32 hartid, ulong mcause,
|
||||
len = 4;
|
||||
val.data_ulong = GET_F32_RS2C(insn, regs);
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
} else {
|
||||
uptrap.epc = regs->mepc;
|
||||
uptrap.cause = mcause;
|
||||
uptrap.cause = CAUSE_MISALIGNED_STORE;
|
||||
uptrap.tval = addr;
|
||||
uptrap.tval2 = tval2;
|
||||
uptrap.tinst = tinst;
|
||||
return sbi_trap_redirect(regs, &uptrap, scratch);
|
||||
return sbi_trap_redirect(regs, &uptrap);
|
||||
}
|
||||
|
||||
for (i = 0; i < len; i++) {
|
||||
sbi_store_u8((void *)(addr + i), val.data_bytes[i],
|
||||
scratch, &uptrap);
|
||||
&uptrap);
|
||||
if (uptrap.cause) {
|
||||
uptrap.epc = regs->mepc;
|
||||
return sbi_trap_redirect(regs, &uptrap, scratch);
|
||||
return sbi_trap_redirect(regs, &uptrap);
|
||||
}
|
||||
}
|
||||
|
||||
regs->mepc += INSN_LEN(insn);
|
||||
regs->mepc += insn_len;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
90
lib/sbi/sbi_platform.c
Normal file
90
lib/sbi/sbi_platform.c
Normal file
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* SPDX-License-Identifier: BSD-2-Clause
|
||||
*
|
||||
* Copyright (c) 2020 Western Digital Corporation or its affiliates.
|
||||
*
|
||||
* Authors:
|
||||
* Atish Patra <atish.patra@wdc.com>
|
||||
*/
|
||||
|
||||
#include <sbi/sbi_console.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_string.h>
|
||||
|
||||
static inline char *sbi_platform_feature_id2string(unsigned long feature)
|
||||
{
|
||||
char *fstr = NULL;
|
||||
|
||||
if (!feature)
|
||||
return NULL;
|
||||
|
||||
switch (feature) {
|
||||
case SBI_PLATFORM_HAS_TIMER_VALUE:
|
||||
fstr = "timer";
|
||||
break;
|
||||
case SBI_PLATFORM_HAS_HART_HOTPLUG:
|
||||
fstr = "hotplug";
|
||||
break;
|
||||
case SBI_PLATFORM_HAS_MFAULTS_DELEGATION:
|
||||
fstr = "mfdeleg";
|
||||
break;
|
||||
case SBI_PLATFORM_HAS_HART_SECONDARY_BOOT:
|
||||
fstr = "sec_boot";
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return fstr;
|
||||
}
|
||||
|
||||
void sbi_platform_get_features_str(const struct sbi_platform *plat,
|
||||
char *features_str, int nfstr)
|
||||
{
|
||||
unsigned long features, feat = 1UL;
|
||||
char *temp;
|
||||
int offset = 0;
|
||||
|
||||
if (!plat || !features_str || !nfstr)
|
||||
return;
|
||||
sbi_memset(features_str, 0, nfstr);
|
||||
|
||||
features = sbi_platform_get_features(plat);
|
||||
if (!features)
|
||||
goto done;
|
||||
|
||||
do {
|
||||
if (features & feat) {
|
||||
temp = sbi_platform_feature_id2string(feat);
|
||||
if (temp) {
|
||||
sbi_snprintf(features_str + offset, nfstr,
|
||||
"%s,", temp);
|
||||
offset = offset + sbi_strlen(temp) + 1;
|
||||
}
|
||||
}
|
||||
feat = feat << 1;
|
||||
} while (feat <= SBI_PLATFORM_HAS_LAST_FEATURE);
|
||||
|
||||
done:
|
||||
if (offset)
|
||||
features_str[offset - 1] = '\0';
|
||||
else
|
||||
sbi_strncpy(features_str, "none", nfstr);
|
||||
}
|
||||
|
||||
u32 sbi_platform_hart_index(const struct sbi_platform *plat, u32 hartid)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
if (!plat)
|
||||
return -1U;
|
||||
if (plat->hart_index2id) {
|
||||
for (i = 0; i < plat->hart_count; i++) {
|
||||
if (plat->hart_index2id[i] == hartid)
|
||||
return i;
|
||||
}
|
||||
return -1U;
|
||||
}
|
||||
|
||||
return hartid;
|
||||
}
|
@@ -9,20 +9,43 @@
|
||||
|
||||
#include <sbi/riscv_locks.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_hartmask.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_scratch.h>
|
||||
#include <sbi/sbi_string.h>
|
||||
|
||||
u32 last_hartid_having_scratch = SBI_HARTMASK_MAX_BITS;
|
||||
struct sbi_scratch *hartid_to_scratch_table[SBI_HARTMASK_MAX_BITS] = { 0 };
|
||||
|
||||
static spinlock_t extra_lock = SPIN_LOCK_INITIALIZER;
|
||||
static unsigned long extra_offset = SBI_SCRATCH_EXTRA_SPACE_OFFSET;
|
||||
|
||||
typedef struct sbi_scratch *(*hartid2scratch)(ulong hartid, ulong hartindex);
|
||||
|
||||
int sbi_scratch_init(struct sbi_scratch *scratch)
|
||||
{
|
||||
u32 i;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
for (i = 0; i < SBI_HARTMASK_MAX_BITS; i++) {
|
||||
if (sbi_platform_hart_invalid(plat, i))
|
||||
continue;
|
||||
hartid_to_scratch_table[i] =
|
||||
((hartid2scratch)scratch->hartid_to_scratch)(i,
|
||||
sbi_platform_hart_index(plat, i));
|
||||
if (hartid_to_scratch_table[i])
|
||||
last_hartid_having_scratch = i;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long sbi_scratch_alloc_offset(unsigned long size, const char *owner)
|
||||
{
|
||||
u32 i;
|
||||
void *ptr;
|
||||
unsigned long ret = 0;
|
||||
struct sbi_scratch *scratch, *rscratch;
|
||||
const struct sbi_platform *plat;
|
||||
struct sbi_scratch *rscratch;
|
||||
|
||||
/*
|
||||
* We have a simple brain-dead allocator which never expects
|
||||
@@ -51,10 +74,10 @@ done:
|
||||
spin_unlock(&extra_lock);
|
||||
|
||||
if (ret) {
|
||||
scratch = sbi_scratch_thishart_ptr();
|
||||
plat = sbi_platform_ptr(scratch);
|
||||
for (i = 0; i < sbi_platform_hart_count(plat); i++) {
|
||||
rscratch = sbi_hart_id_to_scratch(scratch, i);
|
||||
for (i = 0; i < sbi_scratch_last_hartid(); i++) {
|
||||
rscratch = sbi_hartid_to_scratch(i);
|
||||
if (!rscratch)
|
||||
continue;
|
||||
ptr = sbi_scratch_offset_ptr(rscratch, ret);
|
||||
sbi_memset(ptr, 0, size);
|
||||
}
|
||||
|
@@ -14,6 +14,10 @@
|
||||
|
||||
#include <sbi/sbi_string.h>
|
||||
|
||||
/*
|
||||
Provides sbi_strcmp for the completeness of supporting string functions.
|
||||
it is not recommended to use sbi_strcmp() but use sbi_strncmp instead.
|
||||
*/
|
||||
int sbi_strcmp(const char *a, const char *b)
|
||||
{
|
||||
/* search first diff or end of string */
|
||||
@@ -23,6 +27,15 @@ int sbi_strcmp(const char *a, const char *b)
|
||||
return *a - *b;
|
||||
}
|
||||
|
||||
int sbi_strncmp(const char *a, const char *b, size_t count)
|
||||
{
|
||||
/* search first diff or end of string */
|
||||
for (; count > 0 && *a == *b && *a != '\0'; a++, b++, count--)
|
||||
;
|
||||
|
||||
return *a - *b;
|
||||
}
|
||||
|
||||
size_t sbi_strlen(const char *str)
|
||||
{
|
||||
unsigned long ret = 0;
|
||||
|
@@ -8,58 +8,49 @@
|
||||
* Nick Kossifidis <mick@ics.forth.gr>
|
||||
*/
|
||||
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/sbi_bitops.h>
|
||||
#include <sbi/sbi_domain.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_hsm.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_system.h>
|
||||
#include <sbi/sbi_ipi.h>
|
||||
#include <sbi/sbi_init.h>
|
||||
|
||||
int sbi_system_early_init(struct sbi_scratch *scratch, bool cold_boot)
|
||||
bool sbi_system_reset_supported(u32 reset_type, u32 reset_reason)
|
||||
{
|
||||
return sbi_platform_early_init(sbi_platform_ptr(scratch), cold_boot);
|
||||
if (sbi_platform_system_reset_check(sbi_platform_thishart_ptr(),
|
||||
reset_type, reset_reason))
|
||||
return TRUE;
|
||||
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
int sbi_system_final_init(struct sbi_scratch *scratch, bool cold_boot)
|
||||
void __noreturn sbi_system_reset(u32 reset_type, u32 reset_reason)
|
||||
{
|
||||
return sbi_platform_final_init(sbi_platform_ptr(scratch), cold_boot);
|
||||
}
|
||||
|
||||
void sbi_system_early_exit(struct sbi_scratch *scratch)
|
||||
{
|
||||
sbi_platform_early_exit(sbi_platform_ptr(scratch));
|
||||
}
|
||||
|
||||
void sbi_system_final_exit(struct sbi_scratch *scratch)
|
||||
{
|
||||
sbi_platform_final_exit(sbi_platform_ptr(scratch));
|
||||
}
|
||||
|
||||
void __noreturn sbi_system_reboot(struct sbi_scratch *scratch, u32 type)
|
||||
{
|
||||
u32 current_hartid_mask = 1UL << sbi_current_hartid();
|
||||
ulong hbase = 0, hmask;
|
||||
u32 cur_hartid = current_hartid();
|
||||
struct sbi_domain *dom = sbi_domain_thishart_ptr();
|
||||
struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
|
||||
|
||||
/* Send HALT IPI to every hart other than the current hart */
|
||||
sbi_ipi_send_halt(scratch,
|
||||
sbi_hart_available_mask() & ~current_hartid_mask, 0);
|
||||
while (!sbi_hsm_hart_started_mask(dom, hbase, &hmask)) {
|
||||
if (hbase <= cur_hartid)
|
||||
hmask &= ~(1UL << (cur_hartid - hbase));
|
||||
if (hmask)
|
||||
sbi_ipi_send_halt(hmask, hbase);
|
||||
hbase += BITS_PER_LONG;
|
||||
}
|
||||
|
||||
/* Platform specific reooot */
|
||||
sbi_platform_system_reboot(sbi_platform_ptr(scratch), type);
|
||||
/* Stop current HART */
|
||||
sbi_hsm_hart_stop(scratch, FALSE);
|
||||
|
||||
/* If platform specific reboot did not work then do sbi_exit() */
|
||||
sbi_exit(scratch);
|
||||
}
|
||||
|
||||
void __noreturn sbi_system_shutdown(struct sbi_scratch *scratch, u32 type)
|
||||
{
|
||||
u32 current_hartid_mask = 1UL << sbi_current_hartid();
|
||||
|
||||
/* Send HALT IPI to every hart other than the current hart */
|
||||
sbi_ipi_send_halt(scratch,
|
||||
sbi_hart_available_mask() & ~current_hartid_mask, 0);
|
||||
|
||||
/* Platform specific shutdown */
|
||||
sbi_platform_system_shutdown(sbi_platform_ptr(scratch), type);
|
||||
|
||||
/* If platform specific shutdown did not work then do sbi_exit() */
|
||||
/* Platform specific reset if domain allowed system reset */
|
||||
if (dom->system_reset_allowed)
|
||||
sbi_platform_system_reset(sbi_platform_ptr(scratch),
|
||||
reset_type, reset_reason);
|
||||
|
||||
/* If platform specific reset did not work then do sbi_exit() */
|
||||
sbi_exit(scratch);
|
||||
}
|
||||
|
@@ -10,13 +10,16 @@
|
||||
#include <sbi/riscv_asm.h>
|
||||
#include <sbi/riscv_encoding.h>
|
||||
#include <sbi/sbi_error.h>
|
||||
#include <sbi/sbi_hart.h>
|
||||
#include <sbi/sbi_platform.h>
|
||||
#include <sbi/sbi_scratch.h>
|
||||
#include <sbi/sbi_timer.h>
|
||||
|
||||
static unsigned long time_delta_off;
|
||||
static u64 (*get_time_val)(const struct sbi_platform *plat);
|
||||
|
||||
#if __riscv_xlen == 32
|
||||
u64 get_ticks(void)
|
||||
static u64 get_ticks(const struct sbi_platform *plat)
|
||||
{
|
||||
u32 lo, hi, tmp;
|
||||
__asm__ __volatile__("1:\n"
|
||||
@@ -28,7 +31,7 @@ u64 get_ticks(void)
|
||||
return ((u64)hi << 32) | lo;
|
||||
}
|
||||
#else
|
||||
u64 get_ticks(void)
|
||||
static u64 get_ticks(const struct sbi_platform *plat)
|
||||
{
|
||||
unsigned long n;
|
||||
|
||||
@@ -37,53 +40,52 @@ u64 get_ticks(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
u64 sbi_timer_value(struct sbi_scratch *scratch)
|
||||
u64 sbi_timer_value(void)
|
||||
{
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
|
||||
if (sbi_platform_has_timer_value(plat))
|
||||
return sbi_platform_timer_value(plat);
|
||||
else
|
||||
return get_ticks();
|
||||
return get_time_val(sbi_platform_thishart_ptr());
|
||||
}
|
||||
|
||||
u64 sbi_timer_virt_value(struct sbi_scratch *scratch)
|
||||
u64 sbi_timer_virt_value(void)
|
||||
{
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
|
||||
time_delta_off);
|
||||
|
||||
return sbi_timer_value(scratch) + *time_delta;
|
||||
return sbi_timer_value() + *time_delta;
|
||||
}
|
||||
|
||||
u64 sbi_timer_get_delta(struct sbi_scratch *scratch)
|
||||
u64 sbi_timer_get_delta(void)
|
||||
{
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
|
||||
time_delta_off);
|
||||
|
||||
return *time_delta;
|
||||
}
|
||||
|
||||
void sbi_timer_set_delta(struct sbi_scratch *scratch, ulong delta)
|
||||
void sbi_timer_set_delta(ulong delta)
|
||||
{
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
|
||||
time_delta_off);
|
||||
|
||||
*time_delta = (u64)delta;
|
||||
}
|
||||
|
||||
void sbi_timer_set_delta_upper(struct sbi_scratch *scratch, ulong delta_upper)
|
||||
void sbi_timer_set_delta_upper(ulong delta_upper)
|
||||
{
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
|
||||
u64 *time_delta = sbi_scratch_offset_ptr(sbi_scratch_thishart_ptr(),
|
||||
time_delta_off);
|
||||
|
||||
*time_delta &= 0xffffffffULL;
|
||||
*time_delta |= ((u64)delta_upper << 32);
|
||||
}
|
||||
|
||||
void sbi_timer_event_start(struct sbi_scratch *scratch, u64 next_event)
|
||||
void sbi_timer_event_start(u64 next_event)
|
||||
{
|
||||
sbi_platform_timer_event_start(sbi_platform_ptr(scratch), next_event);
|
||||
sbi_platform_timer_event_start(sbi_platform_thishart_ptr(), next_event);
|
||||
csr_clear(CSR_MIP, MIP_STIP);
|
||||
csr_set(CSR_MIE, MIP_MTIP);
|
||||
}
|
||||
|
||||
void sbi_timer_process(struct sbi_scratch *scratch)
|
||||
void sbi_timer_process(void)
|
||||
{
|
||||
csr_clear(CSR_MIE, MIP_MTIP);
|
||||
csr_set(CSR_MIP, MIP_STIP);
|
||||
@@ -92,6 +94,8 @@ void sbi_timer_process(struct sbi_scratch *scratch)
|
||||
int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
|
||||
{
|
||||
u64 *time_delta;
|
||||
const struct sbi_platform *plat = sbi_platform_ptr(scratch);
|
||||
int ret;
|
||||
|
||||
if (cold_boot) {
|
||||
time_delta_off = sbi_scratch_alloc_offset(sizeof(*time_delta),
|
||||
@@ -106,7 +110,19 @@ int sbi_timer_init(struct sbi_scratch *scratch, bool cold_boot)
|
||||
time_delta = sbi_scratch_offset_ptr(scratch, time_delta_off);
|
||||
*time_delta = 0;
|
||||
|
||||
return sbi_platform_timer_init(sbi_platform_ptr(scratch), cold_boot);
|
||||
ret = sbi_platform_timer_init(plat, cold_boot);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (sbi_hart_has_feature(scratch, SBI_HART_HAS_TIME))
|
||||
get_time_val = get_ticks;
|
||||
else if (sbi_platform_has_timer_value(plat))
|
||||
get_time_val = sbi_platform_timer_value;
|
||||
else
|
||||
/* There is no method to provide timer value */
|
||||
return SBI_ENODEV;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void sbi_timer_exit(struct sbi_scratch *scratch)
|
||||
|
@@ -32,23 +32,30 @@ static void sbi_tlb_flush_all(void)
|
||||
__asm__ __volatile("sfence.vma");
|
||||
}
|
||||
|
||||
static void sbi_tlb_hfence_vvma(struct sbi_tlb_info *tinfo)
|
||||
void sbi_tlb_local_hfence_vvma(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
unsigned long start = tinfo->start;
|
||||
unsigned long size = tinfo->size;
|
||||
unsigned long i;
|
||||
unsigned long vmid = tinfo->vmid;
|
||||
unsigned long i, hgatp;
|
||||
|
||||
hgatp = csr_swap(CSR_HGATP,
|
||||
(vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
|
||||
|
||||
if ((start == 0 && size == 0) || (size == SBI_TLB_FLUSH_ALL)) {
|
||||
__sbi_hfence_vvma_all();
|
||||
return;
|
||||
goto done;
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i += PAGE_SIZE) {
|
||||
__sbi_hfence_vvma_va(start+i);
|
||||
}
|
||||
|
||||
done:
|
||||
csr_write(CSR_HGATP, hgatp);
|
||||
}
|
||||
|
||||
static void sbi_tlb_hfence_gvma(struct sbi_tlb_info *tinfo)
|
||||
void sbi_tlb_local_hfence_gvma(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
unsigned long start = tinfo->start;
|
||||
unsigned long size = tinfo->size;
|
||||
@@ -64,7 +71,7 @@ static void sbi_tlb_hfence_gvma(struct sbi_tlb_info *tinfo)
|
||||
}
|
||||
}
|
||||
|
||||
static void sbi_tlb_sfence_vma(struct sbi_tlb_info *tinfo)
|
||||
void sbi_tlb_local_sfence_vma(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
unsigned long start = tinfo->start;
|
||||
unsigned long size = tinfo->size;
|
||||
@@ -83,33 +90,40 @@ static void sbi_tlb_sfence_vma(struct sbi_tlb_info *tinfo)
|
||||
}
|
||||
}
|
||||
|
||||
static void sbi_tlb_hfence_vvma_asid(struct sbi_tlb_info *tinfo)
|
||||
void sbi_tlb_local_hfence_vvma_asid(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
unsigned long start = tinfo->start;
|
||||
unsigned long size = tinfo->size;
|
||||
unsigned long asid = tinfo->asid;
|
||||
unsigned long i;
|
||||
unsigned long vmid = tinfo->vmid;
|
||||
unsigned long i, hgatp;
|
||||
|
||||
hgatp = csr_swap(CSR_HGATP,
|
||||
(vmid << HGATP_VMID_SHIFT) & HGATP_VMID_MASK);
|
||||
|
||||
if (start == 0 && size == 0) {
|
||||
__sbi_hfence_vvma_all();
|
||||
return;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (size == SBI_TLB_FLUSH_ALL) {
|
||||
__sbi_hfence_vvma_asid(asid);
|
||||
return;
|
||||
goto done;
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i += PAGE_SIZE) {
|
||||
__sbi_hfence_vvma_asid_va(asid, start + i);
|
||||
__sbi_hfence_vvma_asid_va(start + i, asid);
|
||||
}
|
||||
|
||||
done:
|
||||
csr_write(CSR_HGATP, hgatp);
|
||||
}
|
||||
|
||||
static void sbi_tlb_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
|
||||
void sbi_tlb_local_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
unsigned long start = tinfo->start;
|
||||
unsigned long size = tinfo->size;
|
||||
unsigned long vmid = tinfo->asid;
|
||||
unsigned long vmid = tinfo->vmid;
|
||||
unsigned long i;
|
||||
|
||||
if (start == 0 && size == 0) {
|
||||
@@ -123,11 +137,11 @@ static void sbi_tlb_hfence_gvma_vmid(struct sbi_tlb_info *tinfo)
|
||||
}
|
||||
|
||||
for (i = 0; i < size; i += PAGE_SIZE) {
|
||||
__sbi_hfence_gvma_vmid_gpa(vmid, start+i);
|
||||
__sbi_hfence_gvma_vmid_gpa(start + i, vmid);
|
||||
}
|
||||
}
|
||||
|
||||
static void sbi_tlb_sfence_vma_asid(struct sbi_tlb_info *tinfo)
|
||||
void sbi_tlb_local_sfence_vma_asid(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
unsigned long start = tinfo->start;
|
||||
unsigned long size = tinfo->size;
|
||||
@@ -156,51 +170,24 @@ static void sbi_tlb_sfence_vma_asid(struct sbi_tlb_info *tinfo)
|
||||
}
|
||||
}
|
||||
|
||||
static void sbi_tlb_local_flush(struct sbi_tlb_info *tinfo)
|
||||
void sbi_tlb_local_fence_i(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
switch (tinfo->type) {
|
||||
case SBI_TLB_FLUSH_VMA:
|
||||
sbi_tlb_sfence_vma(tinfo);
|
||||
break;
|
||||
case SBI_TLB_FLUSH_VMA_ASID:
|
||||
sbi_tlb_sfence_vma_asid(tinfo);
|
||||
break;
|
||||
case SBI_TLB_FLUSH_GVMA:
|
||||
sbi_tlb_hfence_gvma(tinfo);
|
||||
break;
|
||||
case SBI_TLB_FLUSH_GVMA_VMID:
|
||||
sbi_tlb_hfence_gvma_vmid(tinfo);
|
||||
break;
|
||||
case SBI_TLB_FLUSH_VVMA:
|
||||
sbi_tlb_hfence_vvma(tinfo);
|
||||
break;
|
||||
case SBI_TLB_FLUSH_VVMA_ASID:
|
||||
sbi_tlb_hfence_vvma_asid(tinfo);
|
||||
break;
|
||||
case SBI_ITLB_FLUSH:
|
||||
__asm__ __volatile("fence.i");
|
||||
break;
|
||||
default:
|
||||
sbi_printf("Invalid tlb flush request type [%lu]\n",
|
||||
tinfo->type);
|
||||
}
|
||||
return;
|
||||
__asm__ __volatile("fence.i");
|
||||
}
|
||||
|
||||
static void sbi_tlb_entry_process(struct sbi_scratch *scratch,
|
||||
struct sbi_tlb_info *tinfo)
|
||||
static void sbi_tlb_entry_process(struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
u32 i;
|
||||
u64 m;
|
||||
u32 rhartid;
|
||||
struct sbi_scratch *rscratch = NULL;
|
||||
unsigned long *rtlb_sync = NULL;
|
||||
|
||||
sbi_tlb_local_flush(tinfo);
|
||||
for (i = 0, m = tinfo->shart_mask; m; i++, m >>= 1) {
|
||||
if (!(m & 1UL))
|
||||
tinfo->local_fn(tinfo);
|
||||
|
||||
sbi_hartmask_for_each_hart(rhartid, &tinfo->smask) {
|
||||
rscratch = sbi_hartid_to_scratch(rhartid);
|
||||
if (!rscratch)
|
||||
continue;
|
||||
|
||||
rscratch = sbi_hart_id_to_scratch(scratch, i);
|
||||
rtlb_sync = sbi_scratch_offset_ptr(rscratch, tlb_sync_off);
|
||||
while (atomic_raw_xchg_ulong(rtlb_sync, 1)) ;
|
||||
}
|
||||
@@ -214,7 +201,7 @@ static void sbi_tlb_process_count(struct sbi_scratch *scratch, int count)
|
||||
sbi_scratch_offset_ptr(scratch, tlb_fifo_off);
|
||||
|
||||
while (!sbi_fifo_dequeue(tlb_fifo, &tinfo)) {
|
||||
sbi_tlb_entry_process(scratch, &tinfo);
|
||||
sbi_tlb_entry_process(&tinfo);
|
||||
deq_count++;
|
||||
if (deq_count > count)
|
||||
break;
|
||||
@@ -229,7 +216,7 @@ static void sbi_tlb_process(struct sbi_scratch *scratch)
|
||||
sbi_scratch_offset_ptr(scratch, tlb_fifo_off);
|
||||
|
||||
while (!sbi_fifo_dequeue(tlb_fifo, &tinfo))
|
||||
sbi_tlb_entry_process(scratch, &tinfo);
|
||||
sbi_tlb_entry_process(&tinfo);
|
||||
}
|
||||
|
||||
static void sbi_tlb_sync(struct sbi_scratch *scratch)
|
||||
@@ -263,11 +250,11 @@ static inline int __sbi_tlb_range_check(struct sbi_tlb_info *curr,
|
||||
if (next->start <= curr->start && next_end > curr_end) {
|
||||
curr->start = next->start;
|
||||
curr->size = next->size;
|
||||
curr->shart_mask = curr->shart_mask | next->shart_mask;
|
||||
ret = SBI_FIFO_UPDATED;
|
||||
sbi_hartmask_or(&curr->smask, &curr->smask, &next->smask);
|
||||
ret = SBI_FIFO_UPDATED;
|
||||
} else if (next->start >= curr->start && next_end <= curr_end) {
|
||||
curr->shart_mask = curr->shart_mask | next->shart_mask;
|
||||
ret = SBI_FIFO_SKIP;
|
||||
sbi_hartmask_or(&curr->smask, &curr->smask, &next->smask);
|
||||
ret = SBI_FIFO_SKIP;
|
||||
}
|
||||
|
||||
return ret;
|
||||
@@ -303,13 +290,13 @@ static int sbi_tlb_update_cb(void *in, void *data)
|
||||
curr = (struct sbi_tlb_info *)data;
|
||||
next = (struct sbi_tlb_info *)in;
|
||||
|
||||
if (next->type == SBI_TLB_FLUSH_VMA_ASID &&
|
||||
curr->type == SBI_TLB_FLUSH_VMA_ASID) {
|
||||
if (next->local_fn == sbi_tlb_local_sfence_vma_asid &&
|
||||
curr->local_fn == sbi_tlb_local_sfence_vma_asid) {
|
||||
if (next->asid == curr->asid)
|
||||
ret = __sbi_tlb_range_check(curr, next);
|
||||
} else if (next->type == SBI_TLB_FLUSH_VMA &&
|
||||
curr->type == SBI_TLB_FLUSH_VMA) {
|
||||
ret = __sbi_tlb_range_check(curr, next);
|
||||
} else if (next->local_fn == sbi_tlb_local_sfence_vma &&
|
||||
curr->local_fn == sbi_tlb_local_sfence_vma) {
|
||||
ret = __sbi_tlb_range_check(curr, next);
|
||||
}
|
||||
|
||||
return ret;
|
||||
@@ -322,7 +309,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch,
|
||||
int ret;
|
||||
struct sbi_fifo *tlb_fifo_r;
|
||||
struct sbi_tlb_info *tinfo = data;
|
||||
u32 curr_hartid = sbi_current_hartid();
|
||||
u32 curr_hartid = current_hartid();
|
||||
|
||||
/*
|
||||
* If address range to flush is too big then simply
|
||||
@@ -339,7 +326,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch,
|
||||
* then just do a local flush and return;
|
||||
*/
|
||||
if (remote_hartid == curr_hartid) {
|
||||
sbi_tlb_local_flush(tinfo);
|
||||
tinfo->local_fn(tinfo);
|
||||
return -1;
|
||||
}
|
||||
|
||||
@@ -360,7 +347,7 @@ static int sbi_tlb_update(struct sbi_scratch *scratch,
|
||||
* this properly.
|
||||
*/
|
||||
sbi_tlb_process_count(scratch, 1);
|
||||
sbi_dprintf(remote_scratch, "hart%d: hart%d tlb fifo full\n",
|
||||
sbi_dprintf("hart%d: hart%d tlb fifo full\n",
|
||||
curr_hartid, remote_hartid);
|
||||
}
|
||||
|
||||
@@ -376,10 +363,12 @@ static struct sbi_ipi_event_ops tlb_ops = {
|
||||
|
||||
static u32 tlb_event = SBI_IPI_EVENT_MAX;
|
||||
|
||||
int sbi_tlb_request(struct sbi_scratch *scratch, ulong hmask,
|
||||
ulong hbase, struct sbi_tlb_info *tinfo)
|
||||
int sbi_tlb_request(ulong hmask, ulong hbase, struct sbi_tlb_info *tinfo)
|
||||
{
|
||||
return sbi_ipi_send_many(scratch, hmask, hbase, tlb_event, tinfo);
|
||||
if (!tinfo->local_fn)
|
||||
return SBI_EINVAL;
|
||||
|
||||
return sbi_ipi_send_many(hmask, hbase, tlb_event, tinfo);
|
||||
}
|
||||
|
||||
int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot)
|
||||
@@ -392,11 +381,11 @@ int sbi_tlb_init(struct sbi_scratch *scratch, bool cold_boot)
|
||||
|
||||
if (cold_boot) {
|
||||
tlb_sync_off = sbi_scratch_alloc_offset(sizeof(*tlb_sync),
|
||||
"IPI_TLB_SYNC");
|
||||
"IPI_TLB_SYNC");
|
||||
if (!tlb_sync_off)
|
||||
return SBI_ENOMEM;
|
||||
tlb_fifo_off = sbi_scratch_alloc_offset(sizeof(*tlb_q),
|
||||
"IPI_TLB_FIFO");
|
||||
"IPI_TLB_FIFO");
|
||||
if (!tlb_fifo_off) {
|
||||
sbi_scratch_free_offset(tlb_sync_off);
|
||||
return SBI_ENOMEM;
|
||||
|
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user