lib: utils/irqchip: Add shared MMIO region for PLIC in root domain

On platforms with Smepmp, the MMIO regions accessed by M-mode need
to be explicitly marked with M-mode only read/write or shared (both
(M-mode and S-mode) read/write permission.

If the above is not done then runtime PLIC access from M-mode on
platforms with Smepmp will result in access fault when further
results in CPU hotplug not working.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
This commit is contained in:
Anup Patel
2023-12-11 14:07:56 +05:30
committed by Anup Patel
parent 80169b25f8
commit cdebae2cc9
9 changed files with 21 additions and 1 deletions

View File

@@ -32,6 +32,7 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
static struct plic_data plic = {
.addr = K210_PLIC_BASE_ADDR,
.size = K210_PLIC_BASE_SIZE,
.num_src = K210_PLIC_NUM_SOURCES,
};

View File

@@ -27,6 +27,7 @@
#define K210_ACLINT_MTIMER_ADDR \
(K210_CLINT_BASE_ADDR + CLINT_MTIMER_OFFSET)
#define K210_PLIC_BASE_ADDR 0x0C000000ULL
#define K210_PLIC_BASE_SIZE (0x200000ULL + (K210_HART_COUNT * 0x1000))
/* Registers */
#define K210_PLL0 0x08