forked from Mirrors/opensbi
cdebae2cc9
On platforms with Smepmp, the MMIO regions accessed by M-mode need to be explicitly marked with M-mode only read/write or shared (both (M-mode and S-mode) read/write permission. If the above is not done then runtime PLIC access from M-mode on platforms with Smepmp will result in access fault when further results in CPU hotplug not working. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
51 lines
1.2 KiB
C
51 lines
1.2 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Damien Le Moal <damien.lemoal@wdc.com>
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*/
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#ifndef _K210_PLATFORM_H_
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#define _K210_PLATFORM_H_
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#include <sbi/riscv_io.h>
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#define K210_HART_COUNT 2
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#define K210_UART_BAUDRATE 115200
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#define K210_ACLINT_MTIMER_FREQ 7800000
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#define K210_CLK0_FREQ 26000000UL
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#define K210_PLIC_NUM_SOURCES 65
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/* Registers base address */
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#define K210_SYSCTL_BASE_ADDR 0x50440000ULL
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#define K210_UART_BASE_ADDR 0x38000000ULL
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#define K210_CLINT_BASE_ADDR 0x02000000ULL
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#define K210_ACLINT_MSWI_ADDR \
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(K210_CLINT_BASE_ADDR + CLINT_MSWI_OFFSET)
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#define K210_ACLINT_MTIMER_ADDR \
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(K210_CLINT_BASE_ADDR + CLINT_MTIMER_OFFSET)
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#define K210_PLIC_BASE_ADDR 0x0C000000ULL
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#define K210_PLIC_BASE_SIZE (0x200000ULL + (K210_HART_COUNT * 0x1000))
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/* Registers */
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#define K210_PLL0 0x08
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#define K210_CLKSEL0 0x20
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#define K210_RESET 0x30
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/* Register bit masks */
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#define K210_RESET_MASK 0x01
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static inline u32 k210_read_sysreg(u32 reg)
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{
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return readl((volatile void *)(K210_SYSCTL_BASE_ADDR + reg));
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}
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static inline void k210_write_sysreg(u32 val, u32 reg)
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{
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writel(val, (volatile void *)(K210_SYSCTL_BASE_ADDR + reg));
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}
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#endif /* _K210_PLATFORM_H_ */
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