forked from Mirrors/opensbi

On platforms with Smepmp, the MMIO regions accessed by M-mode need to be explicitly marked with M-mode only read/write or shared (both (M-mode and S-mode) read/write permission. If the above is not done then runtime PLIC access from M-mode on platforms with Smepmp will result in access fault when further results in CPU hotplug not working. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
204 lines
4.3 KiB
C
204 lines
4.3 KiB
C
/*
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Damien Le Moal <damien.lemoal@wdc.com>
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*/
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#include <sbi/riscv_asm.h>
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#include <sbi/riscv_encoding.h>
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#include <sbi/sbi_console.h>
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#include <sbi/sbi_const.h>
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#include <sbi/sbi_platform.h>
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#include <sbi/sbi_system.h>
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#include <sbi_utils/fdt/fdt_helper.h>
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#include <sbi_utils/fdt/fdt_fixup.h>
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#include <sbi_utils/ipi/aclint_mswi.h>
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#include <sbi_utils/irqchip/plic.h>
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#include <sbi_utils/serial/sifive-uart.h>
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#include <sbi_utils/timer/aclint_mtimer.h>
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#include "platform.h"
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extern const char dt_k210_start[];
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unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
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unsigned long arg2, unsigned long arg3,
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unsigned long arg4)
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{
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return (unsigned long)&dt_k210_start[0];
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}
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static struct plic_data plic = {
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.addr = K210_PLIC_BASE_ADDR,
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.size = K210_PLIC_BASE_SIZE,
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.num_src = K210_PLIC_NUM_SOURCES,
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};
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static struct aclint_mswi_data mswi = {
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.addr = K210_ACLINT_MSWI_ADDR,
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.size = ACLINT_MSWI_SIZE,
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.first_hartid = 0,
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.hart_count = K210_HART_COUNT,
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};
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static struct aclint_mtimer_data mtimer = {
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.mtime_freq = K210_ACLINT_MTIMER_FREQ,
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.mtime_addr = K210_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIME_OFFSET,
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.mtime_size = ACLINT_DEFAULT_MTIME_SIZE,
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.mtimecmp_addr = K210_ACLINT_MTIMER_ADDR +
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ACLINT_DEFAULT_MTIMECMP_OFFSET,
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.mtimecmp_size = ACLINT_DEFAULT_MTIMECMP_SIZE,
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.first_hartid = 0,
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.hart_count = K210_HART_COUNT,
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.has_64bit_mmio = true,
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};
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static u32 k210_get_clk_freq(void)
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{
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u32 clksel0, pll0;
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u64 pll0_freq, clkr0, clkf0, clkod0, div;
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/*
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* If the clock selector is not set, use the base frequency.
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* Otherwise, use PLL0 frequency with a frequency divisor.
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*/
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clksel0 = k210_read_sysreg(K210_CLKSEL0);
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if (!(clksel0 & 0x1))
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return K210_CLK0_FREQ;
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/*
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* Get PLL0 frequency:
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* freq = base frequency * clkf0 / (clkr0 * clkod0)
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*/
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pll0 = k210_read_sysreg(K210_PLL0);
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clkr0 = 1 + (pll0 & 0x0000000f);
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clkf0 = 1 + ((pll0 & 0x000003f0) >> 4);
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clkod0 = 1 + ((pll0 & 0x00003c00) >> 10);
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pll0_freq = clkf0 * K210_CLK0_FREQ / (clkr0 * clkod0);
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/* Get the frequency divisor from the clock selector */
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div = 2ULL << ((clksel0 & 0x00000006) >> 1);
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return pll0_freq / div;
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}
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static int k210_system_reset_check(u32 type, u32 reason)
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{
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return 1;
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}
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static void k210_system_reset(u32 type, u32 reason)
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{
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u32 val;
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val = k210_read_sysreg(K210_RESET);
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val |= K210_RESET_MASK;
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k210_write_sysreg(val, K210_RESET);
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while (1);
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}
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static struct sbi_system_reset_device k210_reset = {
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.name = "kendryte_k210_reset",
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.system_reset_check = k210_system_reset_check,
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.system_reset = k210_system_reset
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};
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static int k210_early_init(bool cold_boot)
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{
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if (cold_boot)
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sbi_system_reset_add_device(&k210_reset);
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return 0;
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}
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static int k210_final_init(bool cold_boot)
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{
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void *fdt;
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if (!cold_boot)
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return 0;
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fdt = fdt_get_address();
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fdt_cpu_fixup(fdt);
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fdt_fixups(fdt);
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return 0;
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}
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static int k210_console_init(void)
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{
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return sifive_uart_init(K210_UART_BASE_ADDR, k210_get_clk_freq(),
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K210_UART_BAUDRATE);
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}
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static int k210_irqchip_init(bool cold_boot)
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{
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int rc;
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u32 hartid = current_hartid();
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if (cold_boot) {
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rc = plic_cold_irqchip_init(&plic);
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if (rc)
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return rc;
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}
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return plic_warm_irqchip_init(&plic, hartid * 2, hartid * 2 + 1);
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}
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static int k210_ipi_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = aclint_mswi_cold_init(&mswi);
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if (rc)
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return rc;
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}
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return aclint_mswi_warm_init();
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}
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static int k210_timer_init(bool cold_boot)
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{
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int rc;
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if (cold_boot) {
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rc = aclint_mtimer_cold_init(&mtimer, NULL);
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if (rc)
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return rc;
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}
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return aclint_mtimer_warm_init();
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}
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const struct sbi_platform_operations platform_ops = {
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.early_init = k210_early_init,
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.final_init = k210_final_init,
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.console_init = k210_console_init,
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.irqchip_init = k210_irqchip_init,
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.ipi_init = k210_ipi_init,
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.timer_init = k210_timer_init,
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};
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const struct sbi_platform platform = {
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.opensbi_version = OPENSBI_VERSION,
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.platform_version = SBI_PLATFORM_VERSION(0x0, 0x01),
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.name = "Kendryte K210",
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.features = 0,
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.hart_count = K210_HART_COUNT,
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.hart_stack_size = SBI_PLATFORM_DEFAULT_HART_STACK_SIZE,
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.heap_size =
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SBI_PLATFORM_DEFAULT_HEAP_SIZE(K210_HART_COUNT),
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.platform_ops_addr = (unsigned long)&platform_ops
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};
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