forked from Mirrors/opensbi
		
	lib: utils/irqchip: Add shared MMIO region for PLIC in root domain
On platforms with Smepmp, the MMIO regions accessed by M-mode need to be explicitly marked with M-mode only read/write or shared (both (M-mode and S-mode) read/write permission. If the above is not done then runtime PLIC access from M-mode on platforms with Smepmp will result in access fault when further results in CPU hotplug not working. Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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		@@ -32,6 +32,7 @@ unsigned long fw_platform_init(unsigned long arg0, unsigned long arg1,
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static struct plic_data plic = {
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	.addr = K210_PLIC_BASE_ADDR,
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	.size = K210_PLIC_BASE_SIZE,
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	.num_src = K210_PLIC_NUM_SOURCES,
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};
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@@ -27,6 +27,7 @@
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#define K210_ACLINT_MTIMER_ADDR \
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		(K210_CLINT_BASE_ADDR + CLINT_MTIMER_OFFSET)
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#define K210_PLIC_BASE_ADDR	0x0C000000ULL
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#define K210_PLIC_BASE_SIZE	(0x200000ULL + (K210_HART_COUNT * 0x1000))
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/* Registers */
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#define K210_PLL0		0x08
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