68 lines
2.2 KiB
C
68 lines
2.2 KiB
C
/*
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RISC-V machine interrupts.
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SPDX-License-Identifier: Unlicense
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https://five-embeddev.com/
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*/
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#ifndef RISCV_TRAPS_H
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#define RISCV_TRAPS_H
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enum {
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RISCV_INT_MSI = 3,
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RISCV_INT_MTI = 7,
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RISCV_INT_MEI = 11,
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RISCV_INT_SSI = 1,
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RISCV_INT_STI = 5,
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RISCV_INT_SEI = 9,
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RISCV_INT_USI = 0,
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RISCV_INT_UTI = 4,
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RISCV_INT_UEI = 8,
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};
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enum {
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RISCV_INT_POS_MSI = 3,
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RISCV_INT_POS_MTI = 7,
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RISCV_INT_POS_MEI = 11,
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RISCV_INT_POS_SSI = 1,
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RISCV_INT_POS_STI = 5,
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RISCV_INT_POS_SEI = 9,
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RISCV_INT_POS_USI = 0,
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RISCV_INT_POS_UTI = 4,
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RISCV_INT_POS_UEI = 8,
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};
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enum {
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RISCV_INT_MASK_MSI = (1UL<<RISCV_INT_POS_MSI),
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RISCV_INT_MASK_MTI = (1UL<<RISCV_INT_POS_MTI),
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RISCV_INT_MASK_MEI = (1UL<<RISCV_INT_POS_MEI),
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RISCV_INT_MASK_SSI = (1UL<<RISCV_INT_POS_SSI),
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RISCV_INT_MASK_STI = (1UL<<RISCV_INT_POS_STI),
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RISCV_INT_MASK_SEI = (1UL<<RISCV_INT_POS_SEI),
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RISCV_INT_MASK_USI = (1UL<<RISCV_INT_POS_USI),
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RISCV_INT_MASK_UTI = (1UL<<RISCV_INT_POS_UTI),
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RISCV_INT_MASK_UEI = (1UL<<RISCV_INT_POS_UEI),
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};
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enum {
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RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED=0, /* Instruction address misaligned */
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RISCV_EXCP_INSTRUCTION_ACCESS_FAULT=1, /* Instruction access fault */
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RISCV_EXCP_ILLEGAL_INSTRUCTION=2, /* Illegal instruction */
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RISCV_EXCP_BREAKPOINT=3, /* Breakpoint */
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RISCV_EXCP_LOAD_ADDRESS_MISALIGNED=4, /* Load address misaligned */
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RISCV_EXCP_LOAD_ACCESS_FAULT=5, /* Load access fault */
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RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED =6, /* Store/AMO address misaligned */
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RISCV_EXCP_STORE_AMO_ACCESS_FAULT=7, /* Store/AMO access fault */
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RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE=8, /* Environment call from U-mode */
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RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE=9, /* Environment call from S-mode */
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RISCV_EXCP_RESERVED10=10, /* Reserved */
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RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE=11, /* Environment call from M-mode */
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RISCV_EXCP_INSTRUCTION_PAGE_FAULT=12, /* Instruction page fault */
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RISCV_EXCP_LOAD_PAGE_FAULT=13, /* Load page fault */
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RISCV_EXCP_RESERVED14=14, /* Reserved */
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RISCV_EXCP_STORE_AMO_PAGE_FAULT=15, /* Store/AMO page fault */
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};
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#endif /* RISCV_TRAPS_H */ |