updates build system to support selection of Target memory, includes trace buffer

CMakeLists.txt

@@ -1,11 +1,11 @@
 cmake_minimum_required(VERSION 3.21)
+list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/cmake)
 ###############################################################################
 # we are building embedded, so no shared libs
 set(BUILD_SHARED_LIBS OFF)
 include(${CMAKE_TOOLCHAIN_FILE})
 ###############################################################################
 add_subdirectory(port/moonlight)
-set(TARGET_MEM "ram" CACHE STRING "memory map to use")
 ###############################################################################
 # Adds picolibc
 #set(CMAKE_SYSTEM_PROCESSOR riscv)
@@ -27,6 +27,9 @@ set(NETXDUO_CUSTOM_PORT ${CMAKE_CURRENT_LIST_DIR}/port/netxduo)
 set(NXD_ENABLE_FILE_SERVERS OFF)
 add_subdirectory(third-party/netxduo)
 if(NX_DEBUG)
+  target_compile_definitions(netxduo PRIVATE NX_DEBUG)
+endif()
+if(NX_DEBUG_PACKET)
   target_compile_definitions(netxduo PRIVATE NX_DEBUG NX_DEBUG_PACKET NX_ENABLE_PACKET_DEBUG_INFO)
 endif()
 if(TX_TRACE)
@@ -34,14 +37,19 @@ if(TX_TRACE)
   target_compile_definitions(threadx_smp PUBLIC TX_ENABLE_EVENT_TRACE)
   target_compile_definitions(netxduo PUBLIC TX_ENABLE_EVENT_TRACE)
 endif()
+target_include_directories(netxduo PRIVATE ${CMAKE_CURRENT_LIST_DIR}/port/moonlight)
+target_link_libraries(netxduo PUBLIC threadx c)
 ###############################################################################
 project(threadx_demo C ASM)
+set(TARGET_MEM "ram" CACHE STRING "memory map to use")
 option(NX_DEBUG "compile netxduo debug output in" OFF)
+option(NX_DEBUG_PACKET "compile netxduo debug output for ethernet packets in" OFF)
 option(TX_TRACE "Enable dump of traces to be read by TraceX" OFF)
 set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
 
 function(setup_target TARGET)
   set(options)
+  set(oneValueArgs TARGET_MEM)
   set(multiValueArgs LIBRARIES SOURCES)
   cmake_parse_arguments(ST "${options}" "${oneValueArgs}" "${multiValueArgs}" ${ARGN})
   if(ST_UNPARSED_ARGUMENTS)
@@ -60,6 +68,11 @@ function(setup_target TARGET)
     target_link_libraries(${TARGET} PRIVATE ${ST_LIBRARIES})
   endif()
 
+  if(ST_TARGET_MEM)
+    set(TARGET_MEM "${ST_TARGET_MEM}")
+  endif()
+  target_link_options(${TARGET} PUBLIC -T ${TARGET_MEM}.lds)
+
   target_link_options(${TARGET} PRIVATE
     -Wl,-Map=${CMAKE_BINARY_DIR}/${TARGET}.map)
 

cmake/rv32gc_gnu.cmake

@@ -6,6 +6,7 @@ set(THREADX_ARCH "risc-v32")
 set(THREADX_TOOLCHAIN "gnu")
 set(ARCH_FLAGS "-march=rv32gc_zicsr_zifencei -mabi=ilp32d -mcmodel=medany")
 set(CFLAGS "${ARCH_FLAGS}")
+set(CXXFLAGS "${ARCH_FLAGS}")
 set(ASFLAGS "${ARCH_FLAGS}")
 set(LDFLAGS "${ARCH_FLAGS}")
 

cmake/rv32imac_gnu.cmake

@@ -6,6 +6,7 @@ set(THREADX_ARCH "risc-v32")
 set(THREADX_TOOLCHAIN "gnu")
 set(ARCH_FLAGS "-march=rv32imac_zicsr_zifencei -mabi=ilp32 -mcmodel=medany")
 set(CFLAGS "${ARCH_FLAGS}")
+set(CXXFLAGS "${ARCH_FLAGS}")
 set(ASFLAGS "${ARCH_FLAGS}")
 set(LDFLAGS "${ARCH_FLAGS}")
 

cmake/rv64gc_gnu.cmake

@@ -6,6 +6,7 @@ set(THREADX_ARCH "risc-v64")
 set(THREADX_TOOLCHAIN "gnu")
 set(ARCH_FLAGS "-march=rv64gc_zicsr_zifencei -mabi=lp64d -mcmodel=medany")
 set(CFLAGS "${ARCH_FLAGS}")
+set(CXXFLAGS "${ARCH_FLAGS}")
 set(ASFLAGS "${ARCH_FLAGS}")
 set(LDFLAGS "${ARCH_FLAGS}")
 

cmake/rv64imac_gnu.cmake

@@ -6,6 +6,7 @@ set(THREADX_ARCH "risc-v64")
 set(THREADX_TOOLCHAIN "gnu")
 set(ARCH_FLAGS "-march=rv64imac_zicsr_zifencei -mabi=lp64 -mcmodel=medany")
 set(CFLAGS "${ARCH_FLAGS}")
+set(CXXFLAGS "${ARCH_FLAGS}")
 set(ASFLAGS "${ARCH_FLAGS}")
 set(LDFLAGS "${ARCH_FLAGS}")
 

port/moonlight/CMakeLists.txt

@@ -7,10 +7,6 @@ set(MOONLIGHT_INC_DIR ${MOONLIGHT_ROOT}/inc)
 set(MOONLIGHT_SRC_DIR ${MOONLIGHT_ROOT}/src)
 set(MOONLIGHT_LDS_DIR ${MOONLIGHT_ROOT}/lds)
 
-if(NOT DEFINED TARGET_MEM)
-  set(TARGET_MEM "ram" CACHE STRING "memory map to use")
-endif()
-
 if(NOT DEFINED MOONLIGHT_TRAP_SOURCE)
   set(MOONLIGHT_TRAP_SOURCE ${MOONLIGHT_SRC_DIR}/trap_non_vectored.c)
 endif()
@@ -36,6 +32,5 @@ target_compile_options(moonlight
 target_link_options(moonlight
   INTERFACE
   -nostartfiles
-  -T ${MOONLIGHT_LDS_DIR}/${TARGET_MEM}.lds
   -Wl,--gc-sections
 )

port/moonlight/inc/csr.h

@@ -60,7 +60,7 @@ static inline uint64_t riscv_get_mstatus()
     return x;
 }
 
-static inline void riscv_writ_mstatus(uint64_t x)
+static inline void riscv_write_mstatus(uint64_t x)
 {
     asm volatile("csrw mstatus, %0" : : "r"(x));
 }
@@ -68,7 +68,7 @@ static inline void riscv_writ_mstatus(uint64_t x)
 // machine exception program counter, holds the
 // instruction address to which a return from
 // exception will go.
-static inline void riscv_writ_mepc(uint64_t x)
+static inline void riscv_write_mepc(uint64_t x)
 {
     asm volatile("csrw mepc, %0" : : "r"(x));
 }
@@ -80,7 +80,7 @@ static inline uint64_t riscv_get_sstatus()
     return x;
 }
 
-static inline void riscv_writ_sstatus(uint64_t x)
+static inline void riscv_write_sstatus(uint64_t x)
 {
     asm volatile("csrw sstatus, %0" : : "r"(x));
 }
@@ -93,7 +93,7 @@ static inline uint64_t riscv_get_sip()
     return x;
 }
 
-static inline void riscv_writ_sip(uint64_t x)
+static inline void riscv_write_sip(uint64_t x)
 {
     asm volatile("csrw sip, %0" : : "r"(x));
 }
@@ -105,7 +105,7 @@ static inline uint64_t riscv_get_sie()
     return x;
 }
 
-static inline void riscv_writ_sie(uint64_t x)
+static inline void riscv_write_sie(uint64_t x)
 {
     asm volatile("csrw sie, %0" : : "r"(x));
 }
@@ -117,7 +117,7 @@ static inline uint64_t riscv_get_mie()
     return x;
 }
 
-static inline void riscv_writ_mie(uint64_t x)
+static inline void riscv_write_mie(uint64_t x)
 {
     asm volatile("csrw mie, %0" : : "r"(x));
 }
@@ -125,7 +125,7 @@ static inline void riscv_writ_mie(uint64_t x)
 // supervisor exception program counter, holds the
 // instruction address to which a return from
 // exception will go.
-static inline void riscv_writ_sepc(uint64_t x)
+static inline void riscv_write_sepc(uint64_t x)
 {
     asm volatile("csrw sepc, %0" : : "r"(x));
 }
@@ -145,7 +145,7 @@ static inline uint64_t riscv_get_medeleg()
     return x;
 }
 
-static inline void riscv_writ_medeleg(uint64_t x)
+static inline void riscv_write_medeleg(uint64_t x)
 {
     asm volatile("csrw medeleg, %0" : : "r"(x));
 }
@@ -158,14 +158,14 @@ static inline uint64_t riscv_get_mideleg()
     return x;
 }
 
-static inline void riscv_writ_mideleg(uint64_t x)
+static inline void riscv_write_mideleg(uint64_t x)
 {
     asm volatile("csrw mideleg, %0" : : "r"(x));
 }
 
 // Supervisor Trap-Vector Base Address
 // low two bits are mode.
-static inline void riscv_writ_stvec(uint64_t x)
+static inline void riscv_write_stvec(uint64_t x)
 {
     asm volatile("csrw stvec, %0" : : "r"(x));
 }
@@ -186,7 +186,7 @@ static inline uint64_t riscv_get_stimecmp()
     return x;
 }
 
-static inline void riscv_writ_stimecmp(uint64_t x)
+static inline void riscv_write_stimecmp(uint64_t x)
 {
     // asm volatile("csrw stimecmp, %0" : : "r" (x));
     asm volatile("csrw 0x14d, %0" : : "r"(x));
@@ -201,26 +201,26 @@ static inline uint64_t riscv_get_menvcfg()
     return x;
 }
 
-static inline void riscv_writ_menvcfg(uint64_t x)
+static inline void riscv_write_menvcfg(uint64_t x)
 {
     // asm volatile("csrw menvcfg, %0" : : "r" (x));
     asm volatile("csrw 0x30a, %0" : : "r"(x));
 }
 
 // Physical Memory Protection
-static inline void riscv_writ_pmpcfg0(uint64_t x)
+static inline void riscv_write_pmpcfg0(uint64_t x)
 {
     asm volatile("csrw pmpcfg0, %0" : : "r"(x));
 }
 
-static inline void riscv_writ_pmpaddr0(uint64_t x)
+static inline void riscv_write_pmpaddr0(uint64_t x)
 {
     asm volatile("csrw pmpaddr0, %0" : : "r"(x));
 }
 
 // supervisor address translation and protection;
 // holds the address of the page table.
-static inline void riscv_writ_satp(uint64_t x)
+static inline void riscv_write_satp(uint64_t x)
 {
     asm volatile("csrw satp, %0" : : "r"(x));
 }
@@ -249,7 +249,7 @@ static inline uint64_t riscv_get_stval()
 }
 
 // Machine-mode Counter-Enable
-static inline void riscv_writ_mcounteren(uint64_t x)
+static inline void riscv_write_mcounteren(uint64_t x)
 {
     asm volatile("csrw mcounteren, %0" : : "r"(x));
 }
@@ -274,7 +274,7 @@ static inline void riscv_sintr_on()
 {
     uint64_t sstatus = riscv_get_sstatus();
     sstatus |= SSTATUS_SIE;
-    riscv_writ_sstatus(sstatus);
+    riscv_write_sstatus(sstatus);
 }
 
 // disable device interrupts
@@ -282,7 +282,7 @@ static inline void riscv_sintr_off()
 {
     uint64_t sstatus = riscv_get_sstatus();
     sstatus &= (~SSTATUS_SIE);
-    riscv_writ_sstatus(sstatus);
+    riscv_write_sstatus(sstatus);
 }
 
 // are device interrupts enabled?
@@ -305,7 +305,7 @@ static inline void riscv_mintr_on()
 {
     uint64_t mstatus = riscv_get_mstatus();
     mstatus |= MSTATUS_MIE;
-    riscv_writ_mstatus(mstatus);
+    riscv_write_mstatus(mstatus);
 }
 
 // disable device interrupts
@@ -313,7 +313,7 @@ static inline void riscv_mintr_off()
 {
     uint64_t mstatus = riscv_get_mstatus();
     mstatus &= (~MSTATUS_MIE);
-    riscv_writ_mstatus(mstatus);
+    riscv_write_mstatus(mstatus);
 }
 
 // are device interrupts enabled?
@@ -347,7 +347,7 @@ static inline uint64_t riscv_get_tp()
     return x;
 }
 
-static inline void riscv_writ_tp(uint64_t x)
+static inline void riscv_write_tp(uint64_t x)
 {
     asm volatile("mv tp, %0" : : "r"(x));
 }

port/moonlight/lds/memory_map.ld

@@ -2,6 +2,7 @@ MEMORY
 {
   rom   (rxai!w) : ORIGIN = 0x10080000, LENGTH = 8k
   flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 16M
-  ram   (wxa!ri) : ORIGIN = 0x30000000, LENGTH = 128K
+  ram   (wxa!ri) : ORIGIN = 0x30000000, LENGTH = 256K
+  trace (wxa!ri) : ORIGIN = 0x31000000, LENGTH = 1M
   dram  (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 1024M
 }

port/moonlight/lds/sections.ld

@@ -105,5 +105,13 @@ SECTIONS
   PROVIDE( tohost = . );
   PROVIDE( fromhost = . + 8 );
 
+  .trace_buffer (NOLOAD) :
+  {
+    . =  ORIGIN(trace);
+    __trace_buffer_start = .;
+    . = ORIGIN(trace) + LENGTH(trace);  /* pad until end of trace */
+    __trace_buffer_end = .;
+  } > trace
+
   /DISCARD/ : { *(.eh_frame*) *(.comment) *(.note .note.*) }
 }

port/moonlight/src/exception.c

@@ -1,83 +1,100 @@
+#include "riscv-csr.h"
+#include "riscv-traps.h"
 #include <stdint.h>
 #include <stdio.h>
-#include "riscv-traps.h"
-#include "riscv-csr.h"
 
 // Expect this to increment one time per second - inside exception handler, after each return of MTI handler.
 static volatile uint64_t ecall_count = 0;
 #ifdef NX_DEBUG
-#define PUTS(STR) puts(STR)
+#define PUTS(STR)   puts(STR)
 #define PRINTF(...) printf(__VA_ARGS__)
 #else
 #define PUTS(STR)
 #define PRINTF(...)
 #endif
-void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
+void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval)
-    switch(mcause) {
+{
-        case RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED: {
+    switch (mcause)
+    {
+        case RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED:
+        {
             puts("[EXCEPTION] : Instruction address misaligned\n");
             break;
         }
-        case RISCV_EXCP_INSTRUCTION_ACCESS_FAULT: {
+        case RISCV_EXCP_INSTRUCTION_ACCESS_FAULT:
+        {
             puts("[EXCEPTION] : Instruction access fault\n");
             break;
         }
-        case RISCV_EXCP_ILLEGAL_INSTRUCTION: {
+        case RISCV_EXCP_ILLEGAL_INSTRUCTION:
+        {
             puts("[EXCEPTION] : Illegal Instruction\n");
             break;
         }
-        case RISCV_EXCP_BREAKPOINT: {
+        case RISCV_EXCP_BREAKPOINT:
+        {
             puts("[EXCEPTION] : Breakpoint\n");
             break;
         }
-        case RISCV_EXCP_LOAD_ADDRESS_MISALIGNED: {
+        case RISCV_EXCP_LOAD_ADDRESS_MISALIGNED:
+        {
             puts("[EXCEPTION] : Load address misaligned");
             break;
         }
-        case RISCV_EXCP_LOAD_ACCESS_FAULT: {
+        case RISCV_EXCP_LOAD_ACCESS_FAULT:
+        {
             puts("[EXCEPTION] : Load access fault\n");
             break;
         }
-        case RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED: {
+        case RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED:
+        {
             puts("[EXCEPTION] : Store/AMO address misaligned");
             break;
         }
-        case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: {
+        case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
+        {
             puts("[EXCEPTION] : Store/AMO access fault\n");
             break;
         }
-        case RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE: {
+        case RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE:
+        {
             puts("[EXCEPTION] : Environment call from U-mode\n");
             break;
         }
-        case RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE: {
+        case RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE:
+        {
             puts("[EXCEPTION] : Environment call from S-mode\n");
             break;
         }
-        case RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE: {
+        case RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE:
+        {
             puts("[EXCEPTION] : Environment call from M-mode\n");
             ecall_count++;
-            csr_write_mepc(mepc+4);
+            csr_write_mepc(mepc + 4);
             break;
         }
-        case RISCV_EXCP_INSTRUCTION_PAGE_FAULT: {
+        case RISCV_EXCP_INSTRUCTION_PAGE_FAULT:
+        {
             puts("[EXCEPTION] : Instruction page fault\n");
             break;
         }
-        case RISCV_EXCP_LOAD_PAGE_FAULT: {
+        case RISCV_EXCP_LOAD_PAGE_FAULT:
+        {
             puts("[EXCEPTION] : Load page fault\n");
             break;
         }
-        case RISCV_EXCP_STORE_AMO_PAGE_FAULT: {
+        case RISCV_EXCP_STORE_AMO_PAGE_FAULT:
+        {
             puts("[EXCEPTION] : Store/AMO page fault\n");
             break;
         }
-        default: {
+        default:
+        {
             printf("[EXCEPTION] : Unknown trap cause: %lu\n", mcause);
         }
     }
     printf("[EXCEPTION] : PC: 0x%x\n", mepc);
     printf("[EXCEPTION] : Addr: 0x%x\n", mtval);
-    while(1)
+    while (1)
         ;
 }

port/threadx/src/trap_entry.S

@@ -70,16 +70,16 @@
 
 	STORE   x1, 28*REGBYTES(sp)       // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])
 
-    	call    _tx_thread_context_save    	
+	call    _tx_thread_context_save    	
 
 	csrr a0, mcause
 	csrr a1, mepc
     csrr a2, mtval
 	addi    sp, sp, -8
-    	STORE      ra, 0(sp)
+	STORE      ra, 0(sp)
-    	call    trap_handler
+	call    trap_handler
-    	LOAD      ra, 0(sp)
+	LOAD      ra, 0(sp)
-    	addi    sp, sp, 8
+	addi    sp, sp, 8
 	call _tx_thread_context_restore 
 	// it will nerver return
 .weak trap_handler