corrects saving of floating point registers

The previous implementation always made space for XLEN sized registers, in RV32D this leads to overlaps

port/threadx_smp/inc/tx_port.h

@@ -77,6 +77,54 @@
 #endif
 #define REGBYTES (1 << LOG_REGBYTES)
 
+#define TX_CONTEXT_ALIGN(size) (((size) + 15) & -16)
+
+/* Keep the existing hard-float enable policy. Save the full hardware register
+ * width, even when the calling convention uses narrower floating-point values.
+ */
+#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
+#define TX_CONTEXT_FP_ENABLED 1
+#if __riscv_flen == 64
+#define TX_FP_BYTES 8
+#define TX_FP_LOAD  fld
+#define TX_FP_STORE fsd
+#elif __riscv_flen == 32
+#define TX_FP_BYTES 4
+#define TX_FP_LOAD  flw
+#define TX_FP_STORE fsw
+#else
+#error "Unsupported RISC-V floating-point register width"
+#endif
+#else
+#define TX_CONTEXT_FP_ENABLED 0
+#define TX_FP_BYTES           0
+#endif
+
+/* Integer slots 0..30 contain the interrupt context; slot 31 is padding.
+ * Voluntary switches use slots 0..14; slot 15 is padding. Starting the FP
+ * areas at these boundaries aligns double registers on RV32 as well as RV64.
+ */
+#define TX_INTERRUPT_FP_BASE      (32 * REGBYTES)
+#define TX_SOLICITED_FP_BASE      (16 * REGBYTES)
+#define TX_INTERRUPT_FP_OFFSET(n) (TX_INTERRUPT_FP_BASE + (n) * TX_FP_BYTES)
+/* Solicited FP indices: fs0, fs1, fs2, ... fs11 (not architectural numbers). */
+#define TX_SOLICITED_FP_OFFSET(n) (TX_SOLICITED_FP_BASE + (n) * TX_FP_BYTES)
+#define TX_INTERRUPT_FCSR_OFFSET  TX_INTERRUPT_FP_OFFSET(32)
+#define TX_SOLICITED_FCSR_OFFSET  TX_SOLICITED_FP_OFFSET(12)
+
+/* fcsr follows the FP registers and occupies one REGBYTES slot because
+ * it is accessed with integer LOAD/STORE. Round the complete frame up to
+ * 16 bytes so allocating or releasing it preserves stack alignment. Without
+ * FP support, the frame contains only the integer slots and their padding.
+ */
+#if TX_CONTEXT_FP_ENABLED
+#define TX_INTERRUPT_FRAME_SIZE TX_CONTEXT_ALIGN(TX_INTERRUPT_FCSR_OFFSET + REGBYTES)
+#define TX_SOLICITED_FRAME_SIZE TX_CONTEXT_ALIGN(TX_SOLICITED_FCSR_OFFSET + REGBYTES)
+#else
+#define TX_INTERRUPT_FRAME_SIZE TX_INTERRUPT_FP_BASE
+#define TX_SOLICITED_FRAME_SIZE TX_SOLICITED_FP_BASE
+#endif
+
 #else /*not __ASSEMBLER__ */
 
 /************* Define ThreadX SMP constants.  *************/