Firmware/ThreadX4TGFS
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changes memeory map to match RISCV-VP, commit a94fd67

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Eyck Jentzsch
2026-02-01 18:58:28 +01:00
parent 3ee8f6d230
commit f3232373fe
3 changed files with 15 additions and 10 deletions
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8
src/memory_map.ld
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@@ -1,7 +1,7 @@
MEMORY
{
ram (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 128K
rom (rxai!w) : ORIGIN = 0x10080000, LENGTH = 8k
flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 16M
dram (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 2048M
dram (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 1024M
ram (wxa!ri) : ORIGIN = 0xE0000000, LENGTH = 128K
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 8k
flash (rxai!w) : ORIGIN = 0xF2000000, LENGTH = 16M
}

11
src/sections.ld
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@@ -11,7 +11,6 @@ SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
__stack_segment_size = DEFINED(__stack_segment_size) ? __stack_segment_size : __stack_size;
__data_vma_base = ORIGIN(LOCATION_DATA) + ((ORIGIN(LOCATION_DATA) == 0) ? 0x10 : 0);
/* Code/Const in LOCATION_TEXT */
. = ORIGIN(LOCATION_TEXT);
@@ -48,9 +47,15 @@ SECTIONS
PROVIDE_HIDDEN(__fini_array_end = .);
} > LOCATION_TEXT :text
/* .data in LOCATION_DATA, Load-Image in LOCATION_TEXT, PHDR is data */
.data __data_vma_base : ALIGN(4)
.data_pad (NOLOAD) : ALIGN(4)
{
} > LOCATION_DATA :data
__data_offs = ((ADDR(.data_pad) == 0) ? 0x10 : 0);
/* .data in LOCATION_DATA, Load-Image in LOCATION_TEXT, PHDR is data */
.data : ALIGN(4)
{
. += __data_offs;
__data_start = .;
*(.data .data.*)
__data_end = .;