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This commit is contained in:
Eyck-Alexander Jentzsch
2026-05-28 12:36:29 +02:00
parent b27cf7d852
commit d45a8f9231
2 changed files with 44 additions and 27 deletions
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port/moonlight/src/exception.c
+39 -22
View File
@@ -1,83 +1,100 @@
#include "riscv-csr.h"
#include "riscv-traps.h"
#include <stdint.h> #include <stdint.h>
#include <stdio.h> #include <stdio.h>
#include "riscv-traps.h"
#include "riscv-csr.h"
// Expect this to increment one time per second - inside exception handler, after each return of MTI handler. // Expect this to increment one time per second - inside exception handler, after each return of MTI handler.
static volatile uint64_t ecall_count = 0; static volatile uint64_t ecall_count = 0;
#ifdef NX_DEBUG #ifdef NX_DEBUG
#define PUTS(STR) puts(STR) #define PUTS(STR) puts(STR)
#define PRINTF(...) printf(__VA_ARGS__) #define PRINTF(...) printf(__VA_ARGS__)
#else #else
#define PUTS(STR) #define PUTS(STR)
#define PRINTF(...) #define PRINTF(...)
#endif #endif
void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) { void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval)
switch(mcause) { {
case RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED: { switch (mcause)
{
case RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED:
{
puts("[EXCEPTION] : Instruction address misaligned\n"); puts("[EXCEPTION] : Instruction address misaligned\n");
break; break;
} }
case RISCV_EXCP_INSTRUCTION_ACCESS_FAULT: { case RISCV_EXCP_INSTRUCTION_ACCESS_FAULT:
{
puts("[EXCEPTION] : Instruction access fault\n"); puts("[EXCEPTION] : Instruction access fault\n");
break; break;
} }
case RISCV_EXCP_ILLEGAL_INSTRUCTION: { case RISCV_EXCP_ILLEGAL_INSTRUCTION:
{
puts("[EXCEPTION] : Illegal Instruction\n"); puts("[EXCEPTION] : Illegal Instruction\n");
break; break;
} }
case RISCV_EXCP_BREAKPOINT: { case RISCV_EXCP_BREAKPOINT:
{
puts("[EXCEPTION] : Breakpoint\n"); puts("[EXCEPTION] : Breakpoint\n");
break; break;
} }
case RISCV_EXCP_LOAD_ADDRESS_MISALIGNED: { case RISCV_EXCP_LOAD_ADDRESS_MISALIGNED:
{
puts("[EXCEPTION] : Load address misaligned"); puts("[EXCEPTION] : Load address misaligned");
break; break;
} }
case RISCV_EXCP_LOAD_ACCESS_FAULT: { case RISCV_EXCP_LOAD_ACCESS_FAULT:
{
puts("[EXCEPTION] : Load access fault\n"); puts("[EXCEPTION] : Load access fault\n");
break; break;
} }
case RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED: { case RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED:
{
puts("[EXCEPTION] : Store/AMO address misaligned"); puts("[EXCEPTION] : Store/AMO address misaligned");
break; break;
} }
case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: { case RISCV_EXCP_STORE_AMO_ACCESS_FAULT:
{
puts("[EXCEPTION] : Store/AMO access fault\n"); puts("[EXCEPTION] : Store/AMO access fault\n");
break; break;
} }
case RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE: { case RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE:
{
puts("[EXCEPTION] : Environment call from U-mode\n"); puts("[EXCEPTION] : Environment call from U-mode\n");
break; break;
} }
case RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE: { case RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE:
{
puts("[EXCEPTION] : Environment call from S-mode\n"); puts("[EXCEPTION] : Environment call from S-mode\n");
break; break;
} }
case RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE: { case RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE:
{
puts("[EXCEPTION] : Environment call from M-mode\n"); puts("[EXCEPTION] : Environment call from M-mode\n");
ecall_count++; ecall_count++;
csr_write_mepc(mepc+4); csr_write_mepc(mepc + 4);
break; break;
} }
case RISCV_EXCP_INSTRUCTION_PAGE_FAULT: { case RISCV_EXCP_INSTRUCTION_PAGE_FAULT:
{
puts("[EXCEPTION] : Instruction page fault\n"); puts("[EXCEPTION] : Instruction page fault\n");
break; break;
} }
case RISCV_EXCP_LOAD_PAGE_FAULT: { case RISCV_EXCP_LOAD_PAGE_FAULT:
{
puts("[EXCEPTION] : Load page fault\n"); puts("[EXCEPTION] : Load page fault\n");
break; break;
} }
case RISCV_EXCP_STORE_AMO_PAGE_FAULT: { case RISCV_EXCP_STORE_AMO_PAGE_FAULT:
{
puts("[EXCEPTION] : Store/AMO page fault\n"); puts("[EXCEPTION] : Store/AMO page fault\n");
break; break;
} }
default: { default:
{
printf("[EXCEPTION] : Unknown trap cause: %lu\n", mcause); printf("[EXCEPTION] : Unknown trap cause: %lu\n", mcause);
} }
} }
printf("[EXCEPTION] : PC: 0x%x\n", mepc); printf("[EXCEPTION] : PC: 0x%x\n", mepc);
printf("[EXCEPTION] : Addr: 0x%x\n", mtval); printf("[EXCEPTION] : Addr: 0x%x\n", mtval);
while(1) while (1)
; ;
} }
port/threadx/src/trap_entry.S
+5 -5
View File
@@ -70,16 +70,16 @@
STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv]) STORE x1, 28*REGBYTES(sp) // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])
call _tx_thread_context_save call _tx_thread_context_save
csrr a0, mcause csrr a0, mcause
csrr a1, mepc csrr a1, mepc
csrr a2, mtval csrr a2, mtval
addi sp, sp, -8 addi sp, sp, -8
STORE ra, 0(sp) STORE ra, 0(sp)
call trap_handler call trap_handler
LOAD ra, 0(sp) LOAD ra, 0(sp)
addi sp, sp, 8 addi sp, sp, 8
call _tx_thread_context_restore call _tx_thread_context_restore
// it will nerver return // it will nerver return
.weak trap_handler .weak trap_handler