formats files

2026-05-28 12:36:29 +02:00
parent b27cf7d852
commit d45a8f9231
2 changed files with 44 additions and 27 deletions
@@ -70,16 +70,16 @@

 	STORE   x1, 28*REGBYTES(sp)       // Store RA, 28*REGBYTES(because call will override ra [ra is a calle register in riscv])

-    	call    _tx_thread_context_save    	
+	call    _tx_thread_context_save    	

 	csrr a0, mcause
 	csrr a1, mepc
    csrr a2, mtval
 	addi    sp, sp, -8
-    	STORE      ra, 0(sp)
-    	call    trap_handler
-    	LOAD      ra, 0(sp)
-    	addi    sp, sp, 8
+	STORE      ra, 0(sp)
+	call    trap_handler
+	LOAD      ra, 0(sp)
+	addi    sp, sp, 8
 	call _tx_thread_context_restore 
 	// it will nerver return
 .weak trap_handler