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updates memeory map to match RISCV-VP commit b8b1c23

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This commit is contained in:
Eyck Jentzsch
2026-02-03 08:07:10 +01:00
parent c805aca52d
commit 39ffc7c743
4 changed files with 21 additions and 17 deletions
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14
port/moonlight/exception.c
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@@ -5,7 +5,13 @@
// Expect this to increment one time per second - inside exception handler, after each return of MTI handler. // Expect this to increment one time per second - inside exception handler, after each return of MTI handler.
static volatile uint64_t ecall_count = 0; static volatile uint64_t ecall_count = 0;
#ifdef NX_DEBUG
#define PUTS(STR) puts(STR)
#define PRINTF(...) printf(__VA_ARGS__)
#else
#define PUTS(STR)
#define PRINTF(...)
#endif
void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) { void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
switch(mcause) { switch(mcause) {
case RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED: { case RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED: {
@@ -26,8 +32,6 @@ void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
} }
case RISCV_EXCP_LOAD_ADDRESS_MISALIGNED: { case RISCV_EXCP_LOAD_ADDRESS_MISALIGNED: {
puts("[EXCEPTION] : Load address misaligned"); puts("[EXCEPTION] : Load address misaligned");
printf("[EXCEPTION] : PC: 0x%x\n", mepc);
printf("[EXCEPTION] : Addr: 0x%x\n", mtval);
break; break;
} }
case RISCV_EXCP_LOAD_ACCESS_FAULT: { case RISCV_EXCP_LOAD_ACCESS_FAULT: {
@@ -36,8 +40,6 @@ void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
} }
case RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED: { case RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED: {
puts("[EXCEPTION] : Store/AMO address misaligned"); puts("[EXCEPTION] : Store/AMO address misaligned");
printf("[EXCEPTION] : PC: 0x%x\n", mepc);
printf("[EXCEPTION] : Addr: 0x%x\n", mtval);
break; break;
} }
case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: { case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: {
@@ -74,6 +76,8 @@ void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
printf("[EXCEPTION] : Unknown trap cause: %lu\n", mcause); printf("[EXCEPTION] : Unknown trap cause: %lu\n", mcause);
} }
} }
printf("[EXCEPTION] : PC: 0x%x\n", mepc);
printf("[EXCEPTION] : Addr: 0x%x\n", mtval);
while(1) while(1)
; ;
} }

4
port/moonlight/mnrs_network_driver.c
View File

@@ -950,7 +950,7 @@ VOID _nx_mnrs_eth_recv_packet(UINT id, volatile ethmac_t* ethmac){
from_mac.nx_mac_address_msw=(buffer[6]<<8) + buffer[7]; from_mac.nx_mac_address_msw=(buffer[6]<<8) + buffer[7];
from_mac.nx_mac_address_lsw=(buffer[8]<<24) + (buffer[9]<<16) + (buffer[10]<<8) + buffer[11]; from_mac.nx_mac_address_lsw=(buffer[8]<<24) + (buffer[9]<<16) + (buffer[10]<<8) + buffer[11];
// find the diver instance belonging to our ethmac // find the diver instance belonging to our ethmac
for(i=0; i<NX_MAX_MNRS_INTERFACES; ++i) for(i=0; i<NX_MAX_MNRS_INTERFACES; ++i) {
if(nx_mnrs_driver[i].ethmac == ethmac) if(nx_mnrs_driver[i].ethmac == ethmac)
{ {
ip_ptr = nx_mnrs_driver[i].nx_mnrs_driver_ip_ptr; ip_ptr = nx_mnrs_driver[i].nx_mnrs_driver_ip_ptr;
@@ -995,7 +995,6 @@ VOID _nx_mnrs_eth_recv_packet(UINT id, volatile ethmac_t* ethmac){
if (status) if (status)
{ {
nx_packet_release(packet_ptr); nx_packet_release(packet_ptr);
// _tx_thread_context_restore();
return; return;
} }
} }
@@ -1055,6 +1054,7 @@ VOID _nx_mnrs_eth_recv_packet(UINT id, volatile ethmac_t* ethmac){
nx_packet_release(packet_ptr); nx_packet_release(packet_ptr);
} }
} }
}
set_ethmac_mac_intr_rx_data_avail_intr_enable(ethmac, 1); set_ethmac_mac_intr_rx_data_avail_intr_enable(ethmac, 1);
} }

10
port/moonlight/platform.h
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@@ -5,11 +5,11 @@
#include "riscv-traps.h" #include "riscv-traps.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR)) #define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
#define APB_BASE 0xF0000000 #define PERIPH_BASE 0x10000000
#define uart PERIPH(uart_t, APB_BASE + 0x01000) #define uart PERIPH(uart_t, PERIPH_BASE + 0x01000)
#define aclint PERIPH(aclint_t, APB_BASE + 0x30000) #define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000)
#define ethmac0 PERIPH(ethmac_t, 0xF1000000) #define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000)
#define ethmac1 PERIPH(ethmac_t, 0xF1001000) #define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000)
#define UART0_IRQ 16 #define UART0_IRQ 16
#define TIMER0_IRQ0 17 #define TIMER0_IRQ0 17

8
src/memory_map.ld
View File

@@ -1,7 +1,7 @@
MEMORY MEMORY
{ {
dram (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 1024M rom (rxai!w) : ORIGIN = 0x10080000, LENGTH = 8k
ram (wxa!ri) : ORIGIN = 0xE0000000, LENGTH = 128K flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 16M
rom (rxai!w) : ORIGIN = 0xF0080000, LENGTH = 8k ram (wxa!ri) : ORIGIN = 0x30000000, LENGTH = 128K
flash (rxai!w) : ORIGIN = 0xF2000000, LENGTH = 16M dram (wxa!ri) : ORIGIN = 0x40000000, LENGTH = 1024M
} }