Firmware/ThreadX4TGFS
8
0
Fork 2
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

corrects typo

Browse Source
This commit is contained in:
Eyck-Alexander Jentzsch
2026-05-28 12:35:01 +02:00
parent c3cd8c3fbd
commit 3955789298
1 changed files with 21 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files
port/moonlight/inc/csr.h
+21 -21
View File
@@ -60,7 +60,7 @@ static inline uint64_t riscv_get_mstatus()
return x; return x;
} }
static inline void riscv_writ_mstatus(uint64_t x) static inline void riscv_write_mstatus(uint64_t x)
{ {
asm volatile("csrw mstatus, %0" : : "r"(x)); asm volatile("csrw mstatus, %0" : : "r"(x));
} }
@@ -68,7 +68,7 @@ static inline void riscv_writ_mstatus(uint64_t x)
// machine exception program counter, holds the // machine exception program counter, holds the
// instruction address to which a return from // instruction address to which a return from
// exception will go. // exception will go.
static inline void riscv_writ_mepc(uint64_t x) static inline void riscv_write_mepc(uint64_t x)
{ {
asm volatile("csrw mepc, %0" : : "r"(x)); asm volatile("csrw mepc, %0" : : "r"(x));
} }
@@ -80,7 +80,7 @@ static inline uint64_t riscv_get_sstatus()
return x; return x;
} }
static inline void riscv_writ_sstatus(uint64_t x) static inline void riscv_write_sstatus(uint64_t x)
{ {
asm volatile("csrw sstatus, %0" : : "r"(x)); asm volatile("csrw sstatus, %0" : : "r"(x));
} }
@@ -93,7 +93,7 @@ static inline uint64_t riscv_get_sip()
return x; return x;
} }
static inline void riscv_writ_sip(uint64_t x) static inline void riscv_write_sip(uint64_t x)
{ {
asm volatile("csrw sip, %0" : : "r"(x)); asm volatile("csrw sip, %0" : : "r"(x));
} }
@@ -105,7 +105,7 @@ static inline uint64_t riscv_get_sie()
return x; return x;
} }
static inline void riscv_writ_sie(uint64_t x) static inline void riscv_write_sie(uint64_t x)
{ {
asm volatile("csrw sie, %0" : : "r"(x)); asm volatile("csrw sie, %0" : : "r"(x));
} }
@@ -117,7 +117,7 @@ static inline uint64_t riscv_get_mie()
return x; return x;
} }
static inline void riscv_writ_mie(uint64_t x) static inline void riscv_write_mie(uint64_t x)
{ {
asm volatile("csrw mie, %0" : : "r"(x)); asm volatile("csrw mie, %0" : : "r"(x));
} }
@@ -125,7 +125,7 @@ static inline void riscv_writ_mie(uint64_t x)
// supervisor exception program counter, holds the // supervisor exception program counter, holds the
// instruction address to which a return from // instruction address to which a return from
// exception will go. // exception will go.
static inline void riscv_writ_sepc(uint64_t x) static inline void riscv_write_sepc(uint64_t x)
{ {
asm volatile("csrw sepc, %0" : : "r"(x)); asm volatile("csrw sepc, %0" : : "r"(x));
} }
@@ -145,7 +145,7 @@ static inline uint64_t riscv_get_medeleg()
return x; return x;
} }
static inline void riscv_writ_medeleg(uint64_t x) static inline void riscv_write_medeleg(uint64_t x)
{ {
asm volatile("csrw medeleg, %0" : : "r"(x)); asm volatile("csrw medeleg, %0" : : "r"(x));
} }
@@ -158,14 +158,14 @@ static inline uint64_t riscv_get_mideleg()
return x; return x;
} }
static inline void riscv_writ_mideleg(uint64_t x) static inline void riscv_write_mideleg(uint64_t x)
{ {
asm volatile("csrw mideleg, %0" : : "r"(x)); asm volatile("csrw mideleg, %0" : : "r"(x));
} }
// Supervisor Trap-Vector Base Address // Supervisor Trap-Vector Base Address
// low two bits are mode. // low two bits are mode.
static inline void riscv_writ_stvec(uint64_t x) static inline void riscv_write_stvec(uint64_t x)
{ {
asm volatile("csrw stvec, %0" : : "r"(x)); asm volatile("csrw stvec, %0" : : "r"(x));
} }
@@ -186,7 +186,7 @@ static inline uint64_t riscv_get_stimecmp()
return x; return x;
} }
static inline void riscv_writ_stimecmp(uint64_t x) static inline void riscv_write_stimecmp(uint64_t x)
{ {
// asm volatile("csrw stimecmp, %0" : : "r" (x)); // asm volatile("csrw stimecmp, %0" : : "r" (x));
asm volatile("csrw 0x14d, %0" : : "r"(x)); asm volatile("csrw 0x14d, %0" : : "r"(x));
@@ -201,26 +201,26 @@ static inline uint64_t riscv_get_menvcfg()
return x; return x;
} }
static inline void riscv_writ_menvcfg(uint64_t x) static inline void riscv_write_menvcfg(uint64_t x)
{ {
// asm volatile("csrw menvcfg, %0" : : "r" (x)); // asm volatile("csrw menvcfg, %0" : : "r" (x));
asm volatile("csrw 0x30a, %0" : : "r"(x)); asm volatile("csrw 0x30a, %0" : : "r"(x));
} }
// Physical Memory Protection // Physical Memory Protection
static inline void riscv_writ_pmpcfg0(uint64_t x) static inline void riscv_write_pmpcfg0(uint64_t x)
{ {
asm volatile("csrw pmpcfg0, %0" : : "r"(x)); asm volatile("csrw pmpcfg0, %0" : : "r"(x));
} }
static inline void riscv_writ_pmpaddr0(uint64_t x) static inline void riscv_write_pmpaddr0(uint64_t x)
{ {
asm volatile("csrw pmpaddr0, %0" : : "r"(x)); asm volatile("csrw pmpaddr0, %0" : : "r"(x));
} }
// supervisor address translation and protection; // supervisor address translation and protection;
// holds the address of the page table. // holds the address of the page table.
static inline void riscv_writ_satp(uint64_t x) static inline void riscv_write_satp(uint64_t x)
{ {
asm volatile("csrw satp, %0" : : "r"(x)); asm volatile("csrw satp, %0" : : "r"(x));
} }
@@ -249,7 +249,7 @@ static inline uint64_t riscv_get_stval()
} }
// Machine-mode Counter-Enable // Machine-mode Counter-Enable
static inline void riscv_writ_mcounteren(uint64_t x) static inline void riscv_write_mcounteren(uint64_t x)
{ {
asm volatile("csrw mcounteren, %0" : : "r"(x)); asm volatile("csrw mcounteren, %0" : : "r"(x));
} }
@@ -274,7 +274,7 @@ static inline void riscv_sintr_on()
{ {
uint64_t sstatus = riscv_get_sstatus(); uint64_t sstatus = riscv_get_sstatus();
sstatus |= SSTATUS_SIE; sstatus |= SSTATUS_SIE;
riscv_writ_sstatus(sstatus); riscv_write_sstatus(sstatus);
} }
// disable device interrupts // disable device interrupts
@@ -282,7 +282,7 @@ static inline void riscv_sintr_off()
{ {
uint64_t sstatus = riscv_get_sstatus(); uint64_t sstatus = riscv_get_sstatus();
sstatus &= (~SSTATUS_SIE); sstatus &= (~SSTATUS_SIE);
riscv_writ_sstatus(sstatus); riscv_write_sstatus(sstatus);
} }
// are device interrupts enabled? // are device interrupts enabled?
@@ -305,7 +305,7 @@ static inline void riscv_mintr_on()
{ {
uint64_t mstatus = riscv_get_mstatus(); uint64_t mstatus = riscv_get_mstatus();
mstatus |= MSTATUS_MIE; mstatus |= MSTATUS_MIE;
riscv_writ_mstatus(mstatus); riscv_write_mstatus(mstatus);
} }
// disable device interrupts // disable device interrupts
@@ -313,7 +313,7 @@ static inline void riscv_mintr_off()
{ {
uint64_t mstatus = riscv_get_mstatus(); uint64_t mstatus = riscv_get_mstatus();
mstatus &= (~MSTATUS_MIE); mstatus &= (~MSTATUS_MIE);
riscv_writ_mstatus(mstatus); riscv_write_mstatus(mstatus);
} }
// are device interrupts enabled? // are device interrupts enabled?
@@ -347,7 +347,7 @@ static inline uint64_t riscv_get_tp()
return x; return x;
} }
static inline void riscv_writ_tp(uint64_t x) static inline void riscv_write_tp(uint64_t x)
{ {
asm volatile("mv tp, %0" : : "r"(x)); asm volatile("mv tp, %0" : : "r"(x));
} }