initial commit
This commit is contained in:
97
port/moonlight/gen/aclint.h
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97
port/moonlight/gen/aclint.h
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@@ -0,0 +1,97 @@
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/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-08-02 08:46:07 UTC
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* by peakrdl_mnrs version 1.2.7
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*/
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#ifndef _BSP_ACLINT_H
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#define _BSP_ACLINT_H
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#include <stdint.h>
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typedef struct {
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volatile uint32_t MSIP[4096];
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struct {
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volatile uint32_t LO;
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volatile uint32_t HI;
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} MTIMECMP[4095];
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volatile uint32_t MTIME_LO;
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volatile uint32_t MTIME_HI;
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} aclint_t;
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#define ACLINT_MSIP_OFFS 0
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#define ACLINT_MSIP_MASK 0x1
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#define ACLINT_MSIP(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
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#define ACLINT_MTIMECMPLO_OFFS 0
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#define ACLINT_MTIMECMPLO_MASK 0xffffffff
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#define ACLINT_MTIMECMPLO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
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#define ACLINT_MTIMECMPHI_OFFS 0
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#define ACLINT_MTIMECMPHI_MASK 0xffffffff
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#define ACLINT_MTIMECMPHI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
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#define ACLINT_MTIME_LO_OFFS 0
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#define ACLINT_MTIME_LO_MASK 0xffffffff
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#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
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#define ACLINT_MTIME_HI_OFFS 0
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#define ACLINT_MTIME_HI_MASK 0xffffffff
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#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
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// ACLINT_MSIP0
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static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP[0]; }
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static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP[0] = value; }
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static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP[0] >> 0) & 0x1; }
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static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) {
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reg->MSIP[0] = (reg->MSIP[0] & ~(0x1U << 0)) | (value << 0);
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}
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// ACLINT_MSIP
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static inline uint32_t get_aclint_msip(volatile aclint_t* reg, unsigned idx) { return reg->MSIP[idx]; }
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static inline void set_aclint_msip(volatile aclint_t* reg, unsigned idx, uint32_t value) { reg->MSIP[idx] = value; }
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static inline uint32_t get_aclint_msip_msip(volatile aclint_t* reg, unsigned idx) { return (reg->MSIP[idx] >> 0) & 0x1; }
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static inline void set_aclint_msip_msip(volatile aclint_t* reg, unsigned idx, uint8_t value) {
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reg->MSIP[idx] = (reg->MSIP[idx] & ~(0x1U << 0)) | (value << 0);
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}
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// ACLINT_MTIMECMP0LO
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static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP[0].LO >> 0) & 0xffffffff; }
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static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
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reg->MTIMECMP[0].LO = (reg->MTIMECMP[0].LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIMECMPxLO
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static inline uint32_t get_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].LO >> 0) & 0xffffffff; }
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static inline void set_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx, uint32_t value) {
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reg->MTIMECMP[idx].LO = (reg->MTIMECMP[idx].LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIMECMP0HI
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static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP[0].HI >> 0) & 0xffffffff; }
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static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
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reg->MTIMECMP[0].HI = (reg->MTIMECMP[0].HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIMECMPxHI
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static inline uint32_t get_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].HI >> 0) & 0xffffffff; }
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static inline void set_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx, uint32_t value) {
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reg->MTIMECMP[idx].HI = (reg->MTIMECMP[idx].HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIME_LO
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static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
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static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
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reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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// ACLINT_MTIME_HI
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static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
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static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
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reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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#endif /* _BSP_ACLINT_H */
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477
port/moonlight/gen/ethmac.h
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477
port/moonlight/gen/ethmac.h
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@@ -0,0 +1,477 @@
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/*
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* Copyright (c) 2023 - 2026 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2026-01-26 15:33:03 UTC
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* by peakrdl_mnrs version 1.3.1
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*/
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#ifndef _BSP_ETHMAC_H
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#define _BSP_ETHMAC_H
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#include <stdint.h>
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typedef struct {
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volatile uint32_t MAC_CTRL;
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uint8_t fill0[12];
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volatile uint32_t MAC_TX;
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volatile uint32_t MAC_TX_AVAILABILITY;
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uint8_t fill1[8];
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volatile uint32_t MAC_RX;
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uint8_t fill2[8];
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volatile uint32_t MAC_RX_STATS;
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volatile uint32_t MAC_INTR;
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uint8_t fill3[12];
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volatile uint32_t MDIO_DATA;
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volatile uint32_t MDIO_STATUS;
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volatile uint32_t MDIO_CONFIG;
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volatile uint32_t MDIO_INTR;
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uint8_t fill4[16];
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volatile uint32_t MDIO_SCLK_CONFIG;
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volatile uint32_t MDIO_SSGEN_SETUP;
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volatile uint32_t MDIO_SSGEN_HOLD;
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volatile uint32_t MDIO_SSGEN_DISABLE;
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volatile uint32_t MDIO_SSGEN_ACTIVE_HIGH;
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uint8_t fill5[28];
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volatile uint32_t MDIO_DIRECT_WRITE;
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volatile uint32_t MDIO_DIRECT_READ_WRITE;
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volatile uint32_t MDIO_DIRECT_READ;
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}ethmac_t;
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#define ETHMAC_MAC_CTRL_TX_FLUSH_OFFS 0
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#define ETHMAC_MAC_CTRL_TX_FLUSH_MASK 0x1
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#define ETHMAC_MAC_CTRL_TX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_TX_FLUSH_MASK) << ETHMAC_MAC_CTRL_TX_FLUSH_OFFS)
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#define ETHMAC_MAC_CTRL_TX_READY_OFFS 1
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#define ETHMAC_MAC_CTRL_TX_READY_MASK 0x1
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#define ETHMAC_MAC_CTRL_TX_READY(V) ((V & ETHMAC_MAC_CTRL_TX_READY_MASK) << ETHMAC_MAC_CTRL_TX_READY_OFFS)
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#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS 2
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#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK 0x1
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#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS)
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#define ETHMAC_MAC_CTRL_RX_FLUSH_OFFS 4
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#define ETHMAC_MAC_CTRL_RX_FLUSH_MASK 0x1
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#define ETHMAC_MAC_CTRL_RX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_RX_FLUSH_MASK) << ETHMAC_MAC_CTRL_RX_FLUSH_OFFS)
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#define ETHMAC_MAC_CTRL_RX_PENDING_OFFS 5
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#define ETHMAC_MAC_CTRL_RX_PENDING_MASK 0x1
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#define ETHMAC_MAC_CTRL_RX_PENDING(V) ((V & ETHMAC_MAC_CTRL_RX_PENDING_MASK) << ETHMAC_MAC_CTRL_RX_PENDING_OFFS)
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#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS 6
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#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK 0x1
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#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS)
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#define ETHMAC_MAC_TX_OFFS 0
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#define ETHMAC_MAC_TX_MASK 0xffffffff
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#define ETHMAC_MAC_TX(V) ((V & ETHMAC_MAC_TX_MASK) << ETHMAC_MAC_TX_OFFS)
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#define ETHMAC_MAC_TX_AVAILABILITY_OFFS 0
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#define ETHMAC_MAC_TX_AVAILABILITY_MASK 0x7ff
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#define ETHMAC_MAC_TX_AVAILABILITY(V) ((V & ETHMAC_MAC_TX_AVAILABILITY_MASK) << ETHMAC_MAC_TX_AVAILABILITY_OFFS)
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#define ETHMAC_MAC_RX_OFFS 0
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#define ETHMAC_MAC_RX_MASK 0xffffffff
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#define ETHMAC_MAC_RX(V) ((V & ETHMAC_MAC_RX_MASK) << ETHMAC_MAC_RX_OFFS)
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#define ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS 0
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#define ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK 0xff
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#define ETHMAC_MAC_RX_STATS_RX_ERRORS(V) ((V & ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK) << ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS)
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#define ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS 8
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#define ETHMAC_MAC_RX_STATS_RX_DROPS_MASK 0xff
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#define ETHMAC_MAC_RX_STATS_RX_DROPS(V) ((V & ETHMAC_MAC_RX_STATS_RX_DROPS_MASK) << ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS)
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#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS 0
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#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK 0x1
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#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS)
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#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS 1
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#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK 0x1
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#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS)
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#define ETHMAC_MDIO_DATA_DATA_OFFS 0
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#define ETHMAC_MDIO_DATA_DATA_MASK 0xff
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#define ETHMAC_MDIO_DATA_DATA(V) ((V & ETHMAC_MDIO_DATA_DATA_MASK) << ETHMAC_MDIO_DATA_DATA_OFFS)
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#define ETHMAC_MDIO_DATA_WRITE_OFFS 8
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#define ETHMAC_MDIO_DATA_WRITE_MASK 0x1
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#define ETHMAC_MDIO_DATA_WRITE(V) ((V & ETHMAC_MDIO_DATA_WRITE_MASK) << ETHMAC_MDIO_DATA_WRITE_OFFS)
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#define ETHMAC_MDIO_DATA_READ_OFFS 9
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#define ETHMAC_MDIO_DATA_READ_MASK 0x1
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#define ETHMAC_MDIO_DATA_READ(V) ((V & ETHMAC_MDIO_DATA_READ_MASK) << ETHMAC_MDIO_DATA_READ_OFFS)
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#define ETHMAC_MDIO_DATA_SSGEN_OFFS 11
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#define ETHMAC_MDIO_DATA_SSGEN_MASK 0x1
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#define ETHMAC_MDIO_DATA_SSGEN(V) ((V & ETHMAC_MDIO_DATA_SSGEN_MASK) << ETHMAC_MDIO_DATA_SSGEN_OFFS)
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#define ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS 31
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#define ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK 0x1
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#define ETHMAC_MDIO_DATA_RX_DATA_INVALID(V) ((V & ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK) << ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS)
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#define ETHMAC_MDIO_STATUS_TX_FREE_OFFS 0
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#define ETHMAC_MDIO_STATUS_TX_FREE_MASK 0x3f
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#define ETHMAC_MDIO_STATUS_TX_FREE(V) ((V & ETHMAC_MDIO_STATUS_TX_FREE_MASK) << ETHMAC_MDIO_STATUS_TX_FREE_OFFS)
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#define ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS 16
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#define ETHMAC_MDIO_STATUS_RX_AVAIL_MASK 0x3f
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#define ETHMAC_MDIO_STATUS_RX_AVAIL(V) ((V & ETHMAC_MDIO_STATUS_RX_AVAIL_MASK) << ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS)
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#define ETHMAC_MDIO_CONFIG_CPOL_OFFS 0
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#define ETHMAC_MDIO_CONFIG_CPOL_MASK 0x1
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#define ETHMAC_MDIO_CONFIG_CPOL(V) ((V & ETHMAC_MDIO_CONFIG_CPOL_MASK) << ETHMAC_MDIO_CONFIG_CPOL_OFFS)
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#define ETHMAC_MDIO_CONFIG_CPHA_OFFS 1
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#define ETHMAC_MDIO_CONFIG_CPHA_MASK 0x1
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#define ETHMAC_MDIO_CONFIG_CPHA(V) ((V & ETHMAC_MDIO_CONFIG_CPHA_MASK) << ETHMAC_MDIO_CONFIG_CPHA_OFFS)
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#define ETHMAC_MDIO_CONFIG_MODE_OFFS 4
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#define ETHMAC_MDIO_CONFIG_MODE_MASK 0x1
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#define ETHMAC_MDIO_CONFIG_MODE(V) ((V & ETHMAC_MDIO_CONFIG_MODE_MASK) << ETHMAC_MDIO_CONFIG_MODE_OFFS)
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#define ETHMAC_MDIO_INTR_TX_IE_OFFS 0
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#define ETHMAC_MDIO_INTR_TX_IE_MASK 0x1
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#define ETHMAC_MDIO_INTR_TX_IE(V) ((V & ETHMAC_MDIO_INTR_TX_IE_MASK) << ETHMAC_MDIO_INTR_TX_IE_OFFS)
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#define ETHMAC_MDIO_INTR_RX_IE_OFFS 1
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#define ETHMAC_MDIO_INTR_RX_IE_MASK 0x1
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#define ETHMAC_MDIO_INTR_RX_IE(V) ((V & ETHMAC_MDIO_INTR_RX_IE_MASK) << ETHMAC_MDIO_INTR_RX_IE_OFFS)
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#define ETHMAC_MDIO_INTR_TX_IP_OFFS 8
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#define ETHMAC_MDIO_INTR_TX_IP_MASK 0x1
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#define ETHMAC_MDIO_INTR_TX_IP(V) ((V & ETHMAC_MDIO_INTR_TX_IP_MASK) << ETHMAC_MDIO_INTR_TX_IP_OFFS)
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#define ETHMAC_MDIO_INTR_RX_IP_OFFS 9
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#define ETHMAC_MDIO_INTR_RX_IP_MASK 0x1
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#define ETHMAC_MDIO_INTR_RX_IP(V) ((V & ETHMAC_MDIO_INTR_RX_IP_MASK) << ETHMAC_MDIO_INTR_RX_IP_OFFS)
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#define ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS 16
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#define ETHMAC_MDIO_INTR_TX_ACTIVE_MASK 0x1
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#define ETHMAC_MDIO_INTR_TX_ACTIVE(V) ((V & ETHMAC_MDIO_INTR_TX_ACTIVE_MASK) << ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS)
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#define ETHMAC_MDIO_SCLK_CONFIG_OFFS 0
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#define ETHMAC_MDIO_SCLK_CONFIG_MASK 0xfff
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#define ETHMAC_MDIO_SCLK_CONFIG(V) ((V & ETHMAC_MDIO_SCLK_CONFIG_MASK) << ETHMAC_MDIO_SCLK_CONFIG_OFFS)
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#define ETHMAC_MDIO_SSGEN_SETUP_OFFS 0
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#define ETHMAC_MDIO_SSGEN_SETUP_MASK 0xfff
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#define ETHMAC_MDIO_SSGEN_SETUP(V) ((V & ETHMAC_MDIO_SSGEN_SETUP_MASK) << ETHMAC_MDIO_SSGEN_SETUP_OFFS)
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#define ETHMAC_MDIO_SSGEN_HOLD_OFFS 0
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#define ETHMAC_MDIO_SSGEN_HOLD_MASK 0xfff
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#define ETHMAC_MDIO_SSGEN_HOLD(V) ((V & ETHMAC_MDIO_SSGEN_HOLD_MASK) << ETHMAC_MDIO_SSGEN_HOLD_OFFS)
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#define ETHMAC_MDIO_SSGEN_DISABLE_OFFS 0
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#define ETHMAC_MDIO_SSGEN_DISABLE_MASK 0xfff
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#define ETHMAC_MDIO_SSGEN_DISABLE(V) ((V & ETHMAC_MDIO_SSGEN_DISABLE_MASK) << ETHMAC_MDIO_SSGEN_DISABLE_OFFS)
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#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS 0
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#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK 0x1
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#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH(V) ((V & ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK) << ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS)
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#define ETHMAC_MDIO_DIRECT_WRITE_OFFS 0
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#define ETHMAC_MDIO_DIRECT_WRITE_MASK 0xff
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#define ETHMAC_MDIO_DIRECT_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_WRITE_MASK) << ETHMAC_MDIO_DIRECT_WRITE_OFFS)
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#define ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS 0
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#define ETHMAC_MDIO_DIRECT_READ_WRITE_MASK 0xff
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#define ETHMAC_MDIO_DIRECT_READ_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_READ_WRITE_MASK) << ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS)
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#define ETHMAC_MDIO_DIRECT_READ_OFFS 0
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#define ETHMAC_MDIO_DIRECT_READ_MASK 0xff
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#define ETHMAC_MDIO_DIRECT_READ(V) ((V & ETHMAC_MDIO_DIRECT_READ_MASK) << ETHMAC_MDIO_DIRECT_READ_OFFS)
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//ETHMAC_MAC_CTRL
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static inline uint32_t get_ethmac_mac_ctrl(volatile ethmac_t* reg){
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return reg->MAC_CTRL;
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}
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static inline void set_ethmac_mac_ctrl(volatile ethmac_t* reg, uint32_t value){
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reg->MAC_CTRL = value;
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}
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static inline uint32_t get_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg){
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return (reg->MAC_CTRL >> 0) & 0x1;
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}
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static inline void set_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg, uint8_t value){
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reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 0)) | (value << 0);
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}
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static inline uint32_t get_ethmac_mac_ctrl_tx_ready(volatile ethmac_t* reg){
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return (reg->MAC_CTRL >> 1) & 0x1;
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}
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static inline uint32_t get_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg){
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return (reg->MAC_CTRL >> 2) & 0x1;
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}
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static inline void set_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
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reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 2)) | (value << 2);
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}
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static inline uint32_t get_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg){
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return (reg->MAC_CTRL >> 4) & 0x1;
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}
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static inline void set_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 4)) | (value << 4);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mac_ctrl_rx_pending(volatile ethmac_t* reg){
|
||||
return (reg->MAC_CTRL >> 5) & 0x1;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg){
|
||||
return (reg->MAC_CTRL >> 6) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 6)) | (value << 6);
|
||||
}
|
||||
|
||||
//ETHMAC_MAC_TX
|
||||
static inline uint32_t get_ethmac_mac_tx(volatile ethmac_t* reg){
|
||||
return (reg->MAC_TX >> 0) & 0xffffffff;
|
||||
}
|
||||
static inline void set_ethmac_mac_tx(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MAC_TX = (reg->MAC_TX & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MAC_TX_AVAILABILITY
|
||||
static inline uint32_t get_ethmac_mac_tx_availability(volatile ethmac_t* reg){
|
||||
return reg->MAC_TX_AVAILABILITY;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mac_tx_availability_words_avail(volatile ethmac_t* reg){
|
||||
return (reg->MAC_TX_AVAILABILITY >> 0) & 0x7ff;
|
||||
}
|
||||
|
||||
//ETHMAC_MAC_RX
|
||||
static inline uint32_t get_ethmac_mac_rx(volatile ethmac_t* reg){
|
||||
return (reg->MAC_RX >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
//ETHMAC_MAC_RX_STATS
|
||||
static inline uint32_t get_ethmac_mac_rx_stats(volatile ethmac_t* reg){
|
||||
return reg->MAC_RX_STATS;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mac_rx_stats_rx_errors(volatile ethmac_t* reg){
|
||||
return (reg->MAC_RX_STATS >> 0) & 0xff;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mac_rx_stats_rx_drops(volatile ethmac_t* reg){
|
||||
return (reg->MAC_RX_STATS >> 8) & 0xff;
|
||||
}
|
||||
|
||||
//ETHMAC_MAC_INTR
|
||||
static inline uint32_t get_ethmac_mac_intr(volatile ethmac_t* reg){
|
||||
return reg->MAC_INTR;
|
||||
}
|
||||
static inline void set_ethmac_mac_intr(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MAC_INTR = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg){
|
||||
return (reg->MAC_INTR >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg){
|
||||
return (reg->MAC_INTR >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_DATA
|
||||
static inline uint32_t get_ethmac_mdio_data(volatile ethmac_t* reg){
|
||||
return reg->MDIO_DATA;
|
||||
}
|
||||
static inline void set_ethmac_mdio_data(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_DATA = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_data_data(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_DATA >> 0) & 0xff;
|
||||
}
|
||||
static inline void set_ethmac_mdio_data_data(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_data_write(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_DATA >> 8) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_data_write(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_data_read(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_DATA >> 9) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_data_read(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_data_ssgen(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_DATA >> 11) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_data_ssgen(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_data_rx_data_invalid(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_DATA >> 31) & 0x1;
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_STATUS
|
||||
static inline uint32_t get_ethmac_mdio_status(volatile ethmac_t* reg){
|
||||
return reg->MDIO_STATUS;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_status_tx_free(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_STATUS >> 0) & 0x3f;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_status_rx_avail(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_STATUS >> 16) & 0x3f;
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_CONFIG
|
||||
static inline uint32_t get_ethmac_mdio_config(volatile ethmac_t* reg){
|
||||
return reg->MDIO_CONFIG;
|
||||
}
|
||||
static inline void set_ethmac_mdio_config(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_CONFIG = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_config_cpol(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_CONFIG >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_config_cpol(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_config_cpha(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_CONFIG >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_config_cpha(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_config_mode(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_CONFIG >> 4) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_config_mode(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 4)) | (value << 4);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_INTR
|
||||
static inline uint32_t get_ethmac_mdio_intr(volatile ethmac_t* reg){
|
||||
return reg->MDIO_INTR;
|
||||
}
|
||||
static inline void set_ethmac_mdio_intr(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_INTR = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_INTR >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_INTR >> 1) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_INTR >> 8) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_INTR >> 9) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_intr_tx_active(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_INTR >> 16) & 0x1;
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_SCLK_CONFIG
|
||||
static inline uint32_t get_ethmac_mdio_sclk_config(volatile ethmac_t* reg){
|
||||
return reg->MDIO_SCLK_CONFIG;
|
||||
}
|
||||
static inline void set_ethmac_mdio_sclk_config(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_SCLK_CONFIG = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_SCLK_CONFIG >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg, uint16_t value){
|
||||
reg->MDIO_SCLK_CONFIG = (reg->MDIO_SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_SSGEN_SETUP
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg){
|
||||
return reg->MDIO_SSGEN_SETUP;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_SSGEN_SETUP = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_SSGEN_SETUP >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg, uint16_t value){
|
||||
reg->MDIO_SSGEN_SETUP = (reg->MDIO_SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_SSGEN_HOLD
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg){
|
||||
return reg->MDIO_SSGEN_HOLD;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_SSGEN_HOLD = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_SSGEN_HOLD >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg, uint16_t value){
|
||||
reg->MDIO_SSGEN_HOLD = (reg->MDIO_SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_SSGEN_DISABLE
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg){
|
||||
return reg->MDIO_SSGEN_DISABLE;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_SSGEN_DISABLE = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_SSGEN_DISABLE >> 0) & 0xfff;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg, uint16_t value){
|
||||
reg->MDIO_SSGEN_DISABLE = (reg->MDIO_SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_SSGEN_ACTIVE_HIGH
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg){
|
||||
return reg->MDIO_SSGEN_ACTIVE_HIGH;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_SSGEN_ACTIVE_HIGH = value;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_SSGEN_ACTIVE_HIGH >> 0) & 0x1;
|
||||
}
|
||||
static inline void set_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_SSGEN_ACTIVE_HIGH = (reg->MDIO_SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_DIRECT_WRITE
|
||||
static inline void set_ethmac_mdio_direct_write(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_DIRECT_WRITE = value;
|
||||
}
|
||||
static inline void set_ethmac_mdio_direct_write_data(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_DIRECT_WRITE = (reg->MDIO_DIRECT_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_DIRECT_READ_WRITE
|
||||
static inline void set_ethmac_mdio_direct_read_write(volatile ethmac_t* reg, uint32_t value){
|
||||
reg->MDIO_DIRECT_READ_WRITE = value;
|
||||
}
|
||||
static inline void set_ethmac_mdio_direct_read_write_data(volatile ethmac_t* reg, uint8_t value){
|
||||
reg->MDIO_DIRECT_READ_WRITE = (reg->MDIO_DIRECT_READ_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
//ETHMAC_MDIO_DIRECT_READ
|
||||
static inline uint32_t get_ethmac_mdio_direct_read(volatile ethmac_t* reg){
|
||||
return reg->MDIO_DIRECT_READ;
|
||||
}
|
||||
static inline uint32_t get_ethmac_mdio_direct_read_data(volatile ethmac_t* reg){
|
||||
return (reg->MDIO_DIRECT_READ >> 0) & 0xff;
|
||||
}
|
||||
|
||||
#endif /* _BSP_ETHMAC_H */
|
||||
176
port/moonlight/gen/uart.h
Normal file
176
port/moonlight/gen/uart.h
Normal file
@@ -0,0 +1,176 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-08-02 08:46:07 UTC
|
||||
* by peakrdl_mnrs version 1.2.7
|
||||
*/
|
||||
|
||||
#ifndef _BSP_UART_H
|
||||
#define _BSP_UART_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct {
|
||||
volatile uint32_t RX_TX_REG;
|
||||
volatile uint32_t INT_CTRL_REG;
|
||||
volatile uint32_t CLK_DIVIDER_REG;
|
||||
volatile uint32_t FRAME_CONFIG_REG;
|
||||
volatile uint32_t STATUS_REG;
|
||||
} uart_t;
|
||||
|
||||
#define UART_RX_TX_REG_DATA_OFFS 0
|
||||
#define UART_RX_TX_REG_DATA_MASK 0xff
|
||||
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
|
||||
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
|
||||
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_TX_FREE_OFFS 15
|
||||
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
|
||||
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
|
||||
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
|
||||
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_CLK_DIVIDER_REG_OFFS 0
|
||||
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
|
||||
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
|
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#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
|
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#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
|
||||
#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_READ_ERROR_OFFS 0
|
||||
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
|
||||
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_STALL_OFFS 1
|
||||
#define UART_STATUS_REG_STALL_MASK 0x1
|
||||
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
|
||||
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_SET_BREAK_OFFS 10
|
||||
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
|
||||
|
||||
// UART_RX_TX_REG
|
||||
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
|
||||
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
|
||||
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
|
||||
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
|
||||
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
|
||||
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
|
||||
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
|
||||
|
||||
// UART_INT_CTRL_REG
|
||||
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
|
||||
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
|
||||
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
|
||||
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
|
||||
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
|
||||
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
|
||||
}
|
||||
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
|
||||
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
|
||||
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
|
||||
|
||||
// UART_CLK_DIVIDER_REG
|
||||
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
|
||||
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
|
||||
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
|
||||
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
|
||||
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
|
||||
// UART_FRAME_CONFIG_REG
|
||||
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
|
||||
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
|
||||
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
|
||||
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
|
||||
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
|
||||
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
|
||||
}
|
||||
|
||||
// UART_STATUS_REG
|
||||
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
|
||||
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
|
||||
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
|
||||
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
|
||||
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
|
||||
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
|
||||
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
|
||||
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
|
||||
}
|
||||
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
|
||||
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
|
||||
#endif /* _BSP_UART_H */
|
||||
Reference in New Issue
Block a user