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Eyck Jentzsch
2026-01-27 20:45:47 +01:00
commit 1e5eb44ca9
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6
port/moonlight/README.md Normal file
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## Generation of register files
```
pip install --extra-index-url https://git.minres.com/api/packages/Tools/pypi/simple peakrdl-mnrs
mnrs_gen --firmware -o port/moonlight EthMac.rdl
```

39
port/moonlight/aclint.h Normal file
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#ifndef _DEVICES_ACLINT_H
#define _DEVICES_ACLINT_H
#include "gen/aclint.h"
#include <stdint.h>
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value) {
set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
set_aclint_mtime_lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtime(volatile aclint_t* reg) {
#if(__riscv_xlen == 64)
// this assume little endianness
volatile uint64_t* mtime = (volatile uint64_t*)(uint64_t)(&reg->MTIME_LO);
return *mtime;
#else
uint32_t mtimeh_val;
uint32_t mtimel_val;
do {
mtimeh_val = get_aclint_mtime_hi(reg);
mtimel_val = get_aclint_mtime_lo(reg);
} while(mtimeh_val != get_aclint_mtime_hi(reg));
return (uint64_t)((((uint64_t)mtimeh_val) << 32) | mtimel_val);
#endif
}
static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value) {
set_aclint_mtimecmp0lo(reg, (uint32_t)0xFFFFFFFF);
set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
set_aclint_mtimecmp0lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg) {
uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg);
return value;
}
#endif /* _DEVICES_ACLINT_H */

39
port/moonlight/board.c Normal file
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#include "hwtimer.h"
#include "csr.h"
#include "platform.h"
#include "uart.h"
#include <stdio.h>
#include <stdarg.h>
// needed by picolibc/port.c
int uart_putc(int ch) {
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
uart_write(uart, ch);
riscv_mintr_restore(intr_enable);
return 1;
}
int uart_getc(void) {
int intr_enable = riscv_mintr_get();
riscv_mintr_off();
int ch = uart_read(uart);
riscv_mintr_restore(intr_enable);
return ch;
}
int uart_init(void) {
puts("[UART0] : Uart Init Done, this is Test output!");
return 0;
};
int board_init(void) {
int ret;
ret = uart_init();
if(ret)
return ret;
ret = hwtimer_init();
if(ret)
return ret;
return 0;
}

101
port/moonlight/bootup.c Normal file
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/*
Simple C++ startup routine to setup CRT
SPDX-License-Identifier: Unlicense
(https://five-embeddev.com/ | http://www.shincbm.com/)
*/
#include <stdint.h>
#include <string.h>
#ifdef __cplusplus
#define EXTERN_C extern "C"
#else
#define EXTERN_C extern
#endif
// Generic C function pointer.
typedef void(*function_t)(void) ;
// These symbols are defined by the linker script.
// See linker.lds
EXTERN_C uint8_t __bss_start;
EXTERN_C uint8_t __bss_end;
EXTERN_C const uint8_t __data_source;
EXTERN_C uint8_t __data_start;
EXTERN_C uint8_t __data_end;
EXTERN_C function_t __init_array_start;
EXTERN_C function_t __init_array_end;
EXTERN_C function_t __fini_array_start;
EXTERN_C function_t __fini_array_end;
// This function will be placed by the linker script according to the section
// Raw function 'called' by the CPU with no runtime.
EXTERN_C void _start(void) __attribute__ ((naked,section(".text.init")));
// Entry and exit points as C functions.
EXTERN_C void _initialize(void) __attribute__ ((noreturn,section(".init")));
EXTERN_C void _exit(int exit_code) __attribute__ ((noreturn,noinline,weak));
// Standard entry point, no arguments.
extern int main(void);
// The linker script will place this in the reset entry point.
// It will be 'called' with no stack or C runtime configuration.
// NOTE - this only supports a single hart.
// tp will not be initialized
void _start(void) {
// Setup SP and GP
// The locations are defined in the linker script
__asm__ volatile (
".option push;"
// The 'norelax' option is critical here.
// Without 'norelax' the global pointer will
// be loaded relative to the global pointer!
".option norelax;"
"la gp, __global_pointer$;"
".option pop;"
"la sp, _sp;"
"jal zero, _initialize;"
: /* output: none %0 */
: /* input: none */
: /* clobbers: none */);
// This point will not be executed, _initialize() will be called with no return.
}
// At this point we have a stack and global poiner, but no access to global variables.
void _initialize(void) {
// Init memory regions
// Clear the .bss section (global variables with no initial values)
memset((void*) &__bss_start,
0,
(&__bss_end - &__bss_start));
// Initialize the .data section (global variables with initial values)
memcpy((void*)&__data_start,
(const void*)&__data_source,
(&__data_end - &__data_end));
// Call constructors
for (const function_t* entry=&__init_array_start;
entry < &__init_array_end;
++entry) {
(*entry)();
}
int rc = main();
// Call destructors
for (const function_t* entry=&__fini_array_start;
entry < &__fini_array_end;
++entry) {
(*entry)();
}
_exit(rc);
}
// This should never be called. Busy loop with the CPU in idle state.
void _exit(int exit_code) {
(void)exit_code;
// Halt
while (1) {
__asm__ volatile ("wfi");
}
}

79
port/moonlight/exception.c Normal file
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#include <stdint.h>
#include <stdio.h>
#include "riscv-traps.h"
#include "riscv-csr.h"
// Expect this to increment one time per second - inside exception handler, after each return of MTI handler.
static volatile uint64_t ecall_count = 0;
void exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
switch(mcause) {
case RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED: {
puts("[EXCEPTION] : Instruction address misaligned\n");
break;
}
case RISCV_EXCP_INSTRUCTION_ACCESS_FAULT: {
puts("[EXCEPTION] : Instruction access fault\n");
break;
}
case RISCV_EXCP_ILLEGAL_INSTRUCTION: {
puts("[EXCEPTION] : Illegal Instruction\n");
break;
}
case RISCV_EXCP_BREAKPOINT: {
puts("[EXCEPTION] : Breakpoint\n");
break;
}
case RISCV_EXCP_LOAD_ADDRESS_MISALIGNED: {
puts("[EXCEPTION] : Load address misaligned");
printf("[EXCEPTION] : PC: 0x%x\n", mepc);
printf("[EXCEPTION] : Addr: 0x%x\n", mtval);
break;
}
case RISCV_EXCP_LOAD_ACCESS_FAULT: {
puts("[EXCEPTION] : Load access fault\n");
break;
}
case RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED: {
puts("[EXCEPTION] : Store/AMO address misaligned");
printf("[EXCEPTION] : PC: 0x%x\n", mepc);
printf("[EXCEPTION] : Addr: 0x%x\n", mtval);
break;
}
case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: {
puts("[EXCEPTION] : Store/AMO access fault\n");
break;
}
case RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE: {
puts("[EXCEPTION] : Environment call from U-mode\n");
break;
}
case RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE: {
puts("[EXCEPTION] : Environment call from S-mode\n");
break;
}
case RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE: {
puts("[EXCEPTION] : Environment call from M-mode\n");
ecall_count++;
csr_write_mepc(mepc+4);
break;
}
case RISCV_EXCP_INSTRUCTION_PAGE_FAULT: {
puts("[EXCEPTION] : Instruction page fault\n");
break;
}
case RISCV_EXCP_LOAD_PAGE_FAULT: {
puts("[EXCEPTION] : Load page fault\n");
break;
}
case RISCV_EXCP_STORE_AMO_PAGE_FAULT: {
puts("[EXCEPTION] : Store/AMO page fault\n");
break;
}
default: {
printf("[EXCEPTION] : Unknown trap cause: %lu\n", mcause);
}
}
while(1)
;
}

97
port/moonlight/gen/aclint.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H
#include <stdint.h>
typedef struct {
volatile uint32_t MSIP[4096];
struct {
volatile uint32_t LO;
volatile uint32_t HI;
} MTIMECMP[4095];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
} aclint_t;
#define ACLINT_MSIP_OFFS 0
#define ACLINT_MSIP_MASK 0x1
#define ACLINT_MSIP(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
#define ACLINT_MTIMECMPLO_OFFS 0
#define ACLINT_MTIMECMPLO_MASK 0xffffffff
#define ACLINT_MTIMECMPLO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
#define ACLINT_MTIMECMPHI_OFFS 0
#define ACLINT_MTIMECMPHI_MASK 0xffffffff
#define ACLINT_MTIMECMPHI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
#define ACLINT_MTIME_LO_OFFS 0
#define ACLINT_MTIME_LO_MASK 0xffffffff
#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
#define ACLINT_MTIME_HI_OFFS 0
#define ACLINT_MTIME_HI_MASK 0xffffffff
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0
static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP[0]; }
static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP[0] = value; }
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP[0] >> 0) & 0x1; }
static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) {
reg->MSIP[0] = (reg->MSIP[0] & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MSIP
static inline uint32_t get_aclint_msip(volatile aclint_t* reg, unsigned idx) { return reg->MSIP[idx]; }
static inline void set_aclint_msip(volatile aclint_t* reg, unsigned idx, uint32_t value) { reg->MSIP[idx] = value; }
static inline uint32_t get_aclint_msip_msip(volatile aclint_t* reg, unsigned idx) { return (reg->MSIP[idx] >> 0) & 0x1; }
static inline void set_aclint_msip_msip(volatile aclint_t* reg, unsigned idx, uint8_t value) {
reg->MSIP[idx] = (reg->MSIP[idx] & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0LO
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP[0].LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP[0].LO = (reg->MTIMECMP[0].LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMPxLO
static inline uint32_t get_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx, uint32_t value) {
reg->MTIMECMP[idx].LO = (reg->MTIMECMP[idx].LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0HI
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP[0].HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP[0].HI = (reg->MTIMECMP[0].HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMPxHI
static inline uint32_t get_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx, uint32_t value) {
reg->MTIMECMP[idx].HI = (reg->MTIMECMP[idx].HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_LO
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_HI
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_ACLINT_H */

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port/moonlight/gen/ethmac.h Normal file
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/*
* Copyright (c) 2023 - 2026 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2026-01-26 15:33:03 UTC
* by peakrdl_mnrs version 1.3.1
*/
#ifndef _BSP_ETHMAC_H
#define _BSP_ETHMAC_H
#include <stdint.h>
typedef struct {
volatile uint32_t MAC_CTRL;
uint8_t fill0[12];
volatile uint32_t MAC_TX;
volatile uint32_t MAC_TX_AVAILABILITY;
uint8_t fill1[8];
volatile uint32_t MAC_RX;
uint8_t fill2[8];
volatile uint32_t MAC_RX_STATS;
volatile uint32_t MAC_INTR;
uint8_t fill3[12];
volatile uint32_t MDIO_DATA;
volatile uint32_t MDIO_STATUS;
volatile uint32_t MDIO_CONFIG;
volatile uint32_t MDIO_INTR;
uint8_t fill4[16];
volatile uint32_t MDIO_SCLK_CONFIG;
volatile uint32_t MDIO_SSGEN_SETUP;
volatile uint32_t MDIO_SSGEN_HOLD;
volatile uint32_t MDIO_SSGEN_DISABLE;
volatile uint32_t MDIO_SSGEN_ACTIVE_HIGH;
uint8_t fill5[28];
volatile uint32_t MDIO_DIRECT_WRITE;
volatile uint32_t MDIO_DIRECT_READ_WRITE;
volatile uint32_t MDIO_DIRECT_READ;
}ethmac_t;
#define ETHMAC_MAC_CTRL_TX_FLUSH_OFFS 0
#define ETHMAC_MAC_CTRL_TX_FLUSH_MASK 0x1
#define ETHMAC_MAC_CTRL_TX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_TX_FLUSH_MASK) << ETHMAC_MAC_CTRL_TX_FLUSH_OFFS)
#define ETHMAC_MAC_CTRL_TX_READY_OFFS 1
#define ETHMAC_MAC_CTRL_TX_READY_MASK 0x1
#define ETHMAC_MAC_CTRL_TX_READY(V) ((V & ETHMAC_MAC_CTRL_TX_READY_MASK) << ETHMAC_MAC_CTRL_TX_READY_OFFS)
#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS 2
#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK 0x1
#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS)
#define ETHMAC_MAC_CTRL_RX_FLUSH_OFFS 4
#define ETHMAC_MAC_CTRL_RX_FLUSH_MASK 0x1
#define ETHMAC_MAC_CTRL_RX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_RX_FLUSH_MASK) << ETHMAC_MAC_CTRL_RX_FLUSH_OFFS)
#define ETHMAC_MAC_CTRL_RX_PENDING_OFFS 5
#define ETHMAC_MAC_CTRL_RX_PENDING_MASK 0x1
#define ETHMAC_MAC_CTRL_RX_PENDING(V) ((V & ETHMAC_MAC_CTRL_RX_PENDING_MASK) << ETHMAC_MAC_CTRL_RX_PENDING_OFFS)
#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS 6
#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK 0x1
#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS)
#define ETHMAC_MAC_TX_OFFS 0
#define ETHMAC_MAC_TX_MASK 0xffffffff
#define ETHMAC_MAC_TX(V) ((V & ETHMAC_MAC_TX_MASK) << ETHMAC_MAC_TX_OFFS)
#define ETHMAC_MAC_TX_AVAILABILITY_OFFS 0
#define ETHMAC_MAC_TX_AVAILABILITY_MASK 0x7ff
#define ETHMAC_MAC_TX_AVAILABILITY(V) ((V & ETHMAC_MAC_TX_AVAILABILITY_MASK) << ETHMAC_MAC_TX_AVAILABILITY_OFFS)
#define ETHMAC_MAC_RX_OFFS 0
#define ETHMAC_MAC_RX_MASK 0xffffffff
#define ETHMAC_MAC_RX(V) ((V & ETHMAC_MAC_RX_MASK) << ETHMAC_MAC_RX_OFFS)
#define ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS 0
#define ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK 0xff
#define ETHMAC_MAC_RX_STATS_RX_ERRORS(V) ((V & ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK) << ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS)
#define ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS 8
#define ETHMAC_MAC_RX_STATS_RX_DROPS_MASK 0xff
#define ETHMAC_MAC_RX_STATS_RX_DROPS(V) ((V & ETHMAC_MAC_RX_STATS_RX_DROPS_MASK) << ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS)
#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS 0
#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK 0x1
#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS)
#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS 1
#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK 0x1
#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS)
#define ETHMAC_MDIO_DATA_DATA_OFFS 0
#define ETHMAC_MDIO_DATA_DATA_MASK 0xff
#define ETHMAC_MDIO_DATA_DATA(V) ((V & ETHMAC_MDIO_DATA_DATA_MASK) << ETHMAC_MDIO_DATA_DATA_OFFS)
#define ETHMAC_MDIO_DATA_WRITE_OFFS 8
#define ETHMAC_MDIO_DATA_WRITE_MASK 0x1
#define ETHMAC_MDIO_DATA_WRITE(V) ((V & ETHMAC_MDIO_DATA_WRITE_MASK) << ETHMAC_MDIO_DATA_WRITE_OFFS)
#define ETHMAC_MDIO_DATA_READ_OFFS 9
#define ETHMAC_MDIO_DATA_READ_MASK 0x1
#define ETHMAC_MDIO_DATA_READ(V) ((V & ETHMAC_MDIO_DATA_READ_MASK) << ETHMAC_MDIO_DATA_READ_OFFS)
#define ETHMAC_MDIO_DATA_SSGEN_OFFS 11
#define ETHMAC_MDIO_DATA_SSGEN_MASK 0x1
#define ETHMAC_MDIO_DATA_SSGEN(V) ((V & ETHMAC_MDIO_DATA_SSGEN_MASK) << ETHMAC_MDIO_DATA_SSGEN_OFFS)
#define ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS 31
#define ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK 0x1
#define ETHMAC_MDIO_DATA_RX_DATA_INVALID(V) ((V & ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK) << ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS)
#define ETHMAC_MDIO_STATUS_TX_FREE_OFFS 0
#define ETHMAC_MDIO_STATUS_TX_FREE_MASK 0x3f
#define ETHMAC_MDIO_STATUS_TX_FREE(V) ((V & ETHMAC_MDIO_STATUS_TX_FREE_MASK) << ETHMAC_MDIO_STATUS_TX_FREE_OFFS)
#define ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS 16
#define ETHMAC_MDIO_STATUS_RX_AVAIL_MASK 0x3f
#define ETHMAC_MDIO_STATUS_RX_AVAIL(V) ((V & ETHMAC_MDIO_STATUS_RX_AVAIL_MASK) << ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS)
#define ETHMAC_MDIO_CONFIG_CPOL_OFFS 0
#define ETHMAC_MDIO_CONFIG_CPOL_MASK 0x1
#define ETHMAC_MDIO_CONFIG_CPOL(V) ((V & ETHMAC_MDIO_CONFIG_CPOL_MASK) << ETHMAC_MDIO_CONFIG_CPOL_OFFS)
#define ETHMAC_MDIO_CONFIG_CPHA_OFFS 1
#define ETHMAC_MDIO_CONFIG_CPHA_MASK 0x1
#define ETHMAC_MDIO_CONFIG_CPHA(V) ((V & ETHMAC_MDIO_CONFIG_CPHA_MASK) << ETHMAC_MDIO_CONFIG_CPHA_OFFS)
#define ETHMAC_MDIO_CONFIG_MODE_OFFS 4
#define ETHMAC_MDIO_CONFIG_MODE_MASK 0x1
#define ETHMAC_MDIO_CONFIG_MODE(V) ((V & ETHMAC_MDIO_CONFIG_MODE_MASK) << ETHMAC_MDIO_CONFIG_MODE_OFFS)
#define ETHMAC_MDIO_INTR_TX_IE_OFFS 0
#define ETHMAC_MDIO_INTR_TX_IE_MASK 0x1
#define ETHMAC_MDIO_INTR_TX_IE(V) ((V & ETHMAC_MDIO_INTR_TX_IE_MASK) << ETHMAC_MDIO_INTR_TX_IE_OFFS)
#define ETHMAC_MDIO_INTR_RX_IE_OFFS 1
#define ETHMAC_MDIO_INTR_RX_IE_MASK 0x1
#define ETHMAC_MDIO_INTR_RX_IE(V) ((V & ETHMAC_MDIO_INTR_RX_IE_MASK) << ETHMAC_MDIO_INTR_RX_IE_OFFS)
#define ETHMAC_MDIO_INTR_TX_IP_OFFS 8
#define ETHMAC_MDIO_INTR_TX_IP_MASK 0x1
#define ETHMAC_MDIO_INTR_TX_IP(V) ((V & ETHMAC_MDIO_INTR_TX_IP_MASK) << ETHMAC_MDIO_INTR_TX_IP_OFFS)
#define ETHMAC_MDIO_INTR_RX_IP_OFFS 9
#define ETHMAC_MDIO_INTR_RX_IP_MASK 0x1
#define ETHMAC_MDIO_INTR_RX_IP(V) ((V & ETHMAC_MDIO_INTR_RX_IP_MASK) << ETHMAC_MDIO_INTR_RX_IP_OFFS)
#define ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS 16
#define ETHMAC_MDIO_INTR_TX_ACTIVE_MASK 0x1
#define ETHMAC_MDIO_INTR_TX_ACTIVE(V) ((V & ETHMAC_MDIO_INTR_TX_ACTIVE_MASK) << ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS)
#define ETHMAC_MDIO_SCLK_CONFIG_OFFS 0
#define ETHMAC_MDIO_SCLK_CONFIG_MASK 0xfff
#define ETHMAC_MDIO_SCLK_CONFIG(V) ((V & ETHMAC_MDIO_SCLK_CONFIG_MASK) << ETHMAC_MDIO_SCLK_CONFIG_OFFS)
#define ETHMAC_MDIO_SSGEN_SETUP_OFFS 0
#define ETHMAC_MDIO_SSGEN_SETUP_MASK 0xfff
#define ETHMAC_MDIO_SSGEN_SETUP(V) ((V & ETHMAC_MDIO_SSGEN_SETUP_MASK) << ETHMAC_MDIO_SSGEN_SETUP_OFFS)
#define ETHMAC_MDIO_SSGEN_HOLD_OFFS 0
#define ETHMAC_MDIO_SSGEN_HOLD_MASK 0xfff
#define ETHMAC_MDIO_SSGEN_HOLD(V) ((V & ETHMAC_MDIO_SSGEN_HOLD_MASK) << ETHMAC_MDIO_SSGEN_HOLD_OFFS)
#define ETHMAC_MDIO_SSGEN_DISABLE_OFFS 0
#define ETHMAC_MDIO_SSGEN_DISABLE_MASK 0xfff
#define ETHMAC_MDIO_SSGEN_DISABLE(V) ((V & ETHMAC_MDIO_SSGEN_DISABLE_MASK) << ETHMAC_MDIO_SSGEN_DISABLE_OFFS)
#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS 0
#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK 0x1
#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH(V) ((V & ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK) << ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS)
#define ETHMAC_MDIO_DIRECT_WRITE_OFFS 0
#define ETHMAC_MDIO_DIRECT_WRITE_MASK 0xff
#define ETHMAC_MDIO_DIRECT_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_WRITE_MASK) << ETHMAC_MDIO_DIRECT_WRITE_OFFS)
#define ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS 0
#define ETHMAC_MDIO_DIRECT_READ_WRITE_MASK 0xff
#define ETHMAC_MDIO_DIRECT_READ_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_READ_WRITE_MASK) << ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS)
#define ETHMAC_MDIO_DIRECT_READ_OFFS 0
#define ETHMAC_MDIO_DIRECT_READ_MASK 0xff
#define ETHMAC_MDIO_DIRECT_READ(V) ((V & ETHMAC_MDIO_DIRECT_READ_MASK) << ETHMAC_MDIO_DIRECT_READ_OFFS)
//ETHMAC_MAC_CTRL
static inline uint32_t get_ethmac_mac_ctrl(volatile ethmac_t* reg){
return reg->MAC_CTRL;
}
static inline void set_ethmac_mac_ctrl(volatile ethmac_t* reg, uint32_t value){
reg->MAC_CTRL = value;
}
static inline uint32_t get_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 0) & 0x1;
}
static inline void set_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mac_ctrl_tx_ready(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 1) & 0x1;
}
static inline uint32_t get_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 2) & 0x1;
}
static inline void set_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 4) & 0x1;
}
static inline void set_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_ethmac_mac_ctrl_rx_pending(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 5) & 0x1;
}
static inline uint32_t get_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 6) & 0x1;
}
static inline void set_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 6)) | (value << 6);
}
//ETHMAC_MAC_TX
static inline uint32_t get_ethmac_mac_tx(volatile ethmac_t* reg){
return (reg->MAC_TX >> 0) & 0xffffffff;
}
static inline void set_ethmac_mac_tx(volatile ethmac_t* reg, uint32_t value){
reg->MAC_TX = (reg->MAC_TX & ~(0xffffffffU << 0)) | (value << 0);
}
//ETHMAC_MAC_TX_AVAILABILITY
static inline uint32_t get_ethmac_mac_tx_availability(volatile ethmac_t* reg){
return reg->MAC_TX_AVAILABILITY;
}
static inline uint32_t get_ethmac_mac_tx_availability_words_avail(volatile ethmac_t* reg){
return (reg->MAC_TX_AVAILABILITY >> 0) & 0x7ff;
}
//ETHMAC_MAC_RX
static inline uint32_t get_ethmac_mac_rx(volatile ethmac_t* reg){
return (reg->MAC_RX >> 0) & 0xffffffff;
}
//ETHMAC_MAC_RX_STATS
static inline uint32_t get_ethmac_mac_rx_stats(volatile ethmac_t* reg){
return reg->MAC_RX_STATS;
}
static inline uint32_t get_ethmac_mac_rx_stats_rx_errors(volatile ethmac_t* reg){
return (reg->MAC_RX_STATS >> 0) & 0xff;
}
static inline uint32_t get_ethmac_mac_rx_stats_rx_drops(volatile ethmac_t* reg){
return (reg->MAC_RX_STATS >> 8) & 0xff;
}
//ETHMAC_MAC_INTR
static inline uint32_t get_ethmac_mac_intr(volatile ethmac_t* reg){
return reg->MAC_INTR;
}
static inline void set_ethmac_mac_intr(volatile ethmac_t* reg, uint32_t value){
reg->MAC_INTR = value;
}
static inline uint32_t get_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg){
return (reg->MAC_INTR >> 0) & 0x1;
}
static inline void set_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg){
return (reg->MAC_INTR >> 1) & 0x1;
}
static inline void set_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 1)) | (value << 1);
}
//ETHMAC_MDIO_DATA
static inline uint32_t get_ethmac_mdio_data(volatile ethmac_t* reg){
return reg->MDIO_DATA;
}
static inline void set_ethmac_mdio_data(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_DATA = value;
}
static inline uint32_t get_ethmac_mdio_data_data(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 0) & 0xff;
}
static inline void set_ethmac_mdio_data_data(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mdio_data_write(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 8) & 0x1;
}
static inline void set_ethmac_mdio_data_write(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t get_ethmac_mdio_data_read(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 9) & 0x1;
}
static inline void set_ethmac_mdio_data_read(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_ethmac_mdio_data_ssgen(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 11) & 0x1;
}
static inline void set_ethmac_mdio_data_ssgen(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 11)) | (value << 11);
}
static inline uint32_t get_ethmac_mdio_data_rx_data_invalid(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 31) & 0x1;
}
//ETHMAC_MDIO_STATUS
static inline uint32_t get_ethmac_mdio_status(volatile ethmac_t* reg){
return reg->MDIO_STATUS;
}
static inline uint32_t get_ethmac_mdio_status_tx_free(volatile ethmac_t* reg){
return (reg->MDIO_STATUS >> 0) & 0x3f;
}
static inline uint32_t get_ethmac_mdio_status_rx_avail(volatile ethmac_t* reg){
return (reg->MDIO_STATUS >> 16) & 0x3f;
}
//ETHMAC_MDIO_CONFIG
static inline uint32_t get_ethmac_mdio_config(volatile ethmac_t* reg){
return reg->MDIO_CONFIG;
}
static inline void set_ethmac_mdio_config(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_CONFIG = value;
}
static inline uint32_t get_ethmac_mdio_config_cpol(volatile ethmac_t* reg){
return (reg->MDIO_CONFIG >> 0) & 0x1;
}
static inline void set_ethmac_mdio_config_cpol(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mdio_config_cpha(volatile ethmac_t* reg){
return (reg->MDIO_CONFIG >> 1) & 0x1;
}
static inline void set_ethmac_mdio_config_cpha(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_ethmac_mdio_config_mode(volatile ethmac_t* reg){
return (reg->MDIO_CONFIG >> 4) & 0x1;
}
static inline void set_ethmac_mdio_config_mode(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 4)) | (value << 4);
}
//ETHMAC_MDIO_INTR
static inline uint32_t get_ethmac_mdio_intr(volatile ethmac_t* reg){
return reg->MDIO_INTR;
}
static inline void set_ethmac_mdio_intr(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_INTR = value;
}
static inline uint32_t get_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 0) & 0x1;
}
static inline void set_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 1) & 0x1;
}
static inline void set_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 8) & 0x1;
}
static inline void set_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t get_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 9) & 0x1;
}
static inline void set_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_ethmac_mdio_intr_tx_active(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 16) & 0x1;
}
//ETHMAC_MDIO_SCLK_CONFIG
static inline uint32_t get_ethmac_mdio_sclk_config(volatile ethmac_t* reg){
return reg->MDIO_SCLK_CONFIG;
}
static inline void set_ethmac_mdio_sclk_config(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SCLK_CONFIG = value;
}
static inline uint32_t get_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg){
return (reg->MDIO_SCLK_CONFIG >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SCLK_CONFIG = (reg->MDIO_SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_SETUP
static inline uint32_t get_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_SETUP;
}
static inline void set_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_SETUP = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_SETUP >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SSGEN_SETUP = (reg->MDIO_SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_HOLD
static inline uint32_t get_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_HOLD;
}
static inline void set_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_HOLD = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_HOLD >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SSGEN_HOLD = (reg->MDIO_SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_DISABLE
static inline uint32_t get_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_DISABLE;
}
static inline void set_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_DISABLE = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_DISABLE >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SSGEN_DISABLE = (reg->MDIO_SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_ACTIVE_HIGH
static inline uint32_t get_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_ACTIVE_HIGH;
}
static inline void set_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_ACTIVE_HIGH = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
static inline void set_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_SSGEN_ACTIVE_HIGH = (reg->MDIO_SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
//ETHMAC_MDIO_DIRECT_WRITE
static inline void set_ethmac_mdio_direct_write(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_DIRECT_WRITE = value;
}
static inline void set_ethmac_mdio_direct_write_data(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DIRECT_WRITE = (reg->MDIO_DIRECT_WRITE & ~(0xffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_DIRECT_READ_WRITE
static inline void set_ethmac_mdio_direct_read_write(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_DIRECT_READ_WRITE = value;
}
static inline void set_ethmac_mdio_direct_read_write_data(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DIRECT_READ_WRITE = (reg->MDIO_DIRECT_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_DIRECT_READ
static inline uint32_t get_ethmac_mdio_direct_read(volatile ethmac_t* reg){
return reg->MDIO_DIRECT_READ;
}
static inline uint32_t get_ethmac_mdio_direct_read_data(volatile ethmac_t* reg){
return (reg->MDIO_DIRECT_READ >> 0) & 0xff;
}
#endif /* _BSP_ETHMAC_H */

176
port/moonlight/gen/uart.h Normal file
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@@ -0,0 +1,176 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_UART_H
#define _BSP_UART_H
#include <stdint.h>
typedef struct {
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
} uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
#define UART_RX_TX_REG_TX_FREE_OFFS 15
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
#define UART_CLK_DIVIDER_REG_OFFS 0
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
#define UART_STATUS_REG_READ_ERROR_OFFS 0
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
#define UART_STATUS_REG_STALL_OFFS 1
#define UART_STATUS_REG_STALL_MASK 0x1
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
#define UART_STATUS_REG_SET_BREAK_OFFS 10
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
// UART_INT_CTRL_REG
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
// UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
// UART_FRAME_CONFIG_REG
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
// UART_STATUS_REG
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_UART_H */

32
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/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_HWTIMER_H
#define RISCV_HWTIMER_H
#include "platform.h"
#define TICKNUM_PER_SECOND 32768
#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 1000)
static inline int hwtimer_init(void) {
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;
}
static inline int hwtimer_handler(void) {
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;
}
#endif

1067
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24
port/moonlight/platform.h Normal file
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#include "uart.h"
#include "gen/ethmac.h"
#include "aclint.h"
#include "riscv-csr.h"
#include "riscv-traps.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
#define APB_BASE 0x10000000
#define uart PERIPH(uart_t, APB_BASE + 0x01000)
#define aclint PERIPH(aclint_t, APB_BASE + 0x30000)
#define ethmac0 PERIPH(ethmac_t, 0x18000000)
#define ethmac1 PERIPH(ethmac_t, 0x18001000)
#define UART0_IRQ 16
#define TIMER0_IRQ0 17
#define TIMER0_IRQ1 18
#define QSPI_IRQ 19
#define I2S_IRQ 20
#define CAM_IRQ 21
#define DMA_IRQ 22
#define GPIO_ORQ 23
#define ETH0_IRQ 24
#define ETH1_IRQ 25

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68
port/moonlight/riscv-traps.h Normal file
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/*
RISC-V machine interrupts.
SPDX-License-Identifier: Unlicense
https://five-embeddev.com/
*/
#ifndef RISCV_TRAPS_H
#define RISCV_TRAPS_H
enum {
RISCV_INT_MSI = 3,
RISCV_INT_MTI = 7,
RISCV_INT_MEI = 11,
RISCV_INT_SSI = 1,
RISCV_INT_STI = 5,
RISCV_INT_SEI = 9,
RISCV_INT_USI = 0,
RISCV_INT_UTI = 4,
RISCV_INT_UEI = 8,
};
enum {
RISCV_INT_POS_MSI = 3,
RISCV_INT_POS_MTI = 7,
RISCV_INT_POS_MEI = 11,
RISCV_INT_POS_SSI = 1,
RISCV_INT_POS_STI = 5,
RISCV_INT_POS_SEI = 9,
RISCV_INT_POS_USI = 0,
RISCV_INT_POS_UTI = 4,
RISCV_INT_POS_UEI = 8,
};
enum {
RISCV_INT_MASK_MSI = (1UL<<RISCV_INT_POS_MSI),
RISCV_INT_MASK_MTI = (1UL<<RISCV_INT_POS_MTI),
RISCV_INT_MASK_MEI = (1UL<<RISCV_INT_POS_MEI),
RISCV_INT_MASK_SSI = (1UL<<RISCV_INT_POS_SSI),
RISCV_INT_MASK_STI = (1UL<<RISCV_INT_POS_STI),
RISCV_INT_MASK_SEI = (1UL<<RISCV_INT_POS_SEI),
RISCV_INT_MASK_USI = (1UL<<RISCV_INT_POS_USI),
RISCV_INT_MASK_UTI = (1UL<<RISCV_INT_POS_UTI),
RISCV_INT_MASK_UEI = (1UL<<RISCV_INT_POS_UEI),
};
enum {
RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED=0, /* Instruction address misaligned */
RISCV_EXCP_INSTRUCTION_ACCESS_FAULT=1, /* Instruction access fault */
RISCV_EXCP_ILLEGAL_INSTRUCTION=2, /* Illegal instruction */
RISCV_EXCP_BREAKPOINT=3, /* Breakpoint */
RISCV_EXCP_LOAD_ADDRESS_MISALIGNED=4, /* Load address misaligned */
RISCV_EXCP_LOAD_ACCESS_FAULT=5, /* Load access fault */
RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED =6, /* Store/AMO address misaligned */
RISCV_EXCP_STORE_AMO_ACCESS_FAULT=7, /* Store/AMO access fault */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE=8, /* Environment call from U-mode */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE=9, /* Environment call from S-mode */
RISCV_EXCP_RESERVED10=10, /* Reserved */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE=11, /* Environment call from M-mode */
RISCV_EXCP_INSTRUCTION_PAGE_FAULT=12, /* Instruction page fault */
RISCV_EXCP_LOAD_PAGE_FAULT=13, /* Load page fault */
RISCV_EXCP_RESERVED14=14, /* Reserved */
RISCV_EXCP_STORE_AMO_PAGE_FAULT=15, /* Store/AMO page fault */
};
#endif /* RISCV_TRAPS_H */

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#include "hwtimer.h"
#include <stdint.h>
#include <tx_api.h>
#include <tx_port.h>
#include <stdio.h>
#include "riscv-traps.h"
#if __riscv_xlen == 64
#define INTERRUPT_BIT 0x8000000000000000ull
#else
#define INTERRUPT_BIT 0x80000000ull
#endif
#define OS_IS_INTERRUPT(mcause) (mcause & INTERRUPT_BIT)
#define OS_IS_TICK_INT(mcause) (mcause == (0x7 | INTERRUPT_BIT))
#define OS_IS_SOFT_INT(mcause) (mcause == (0x3 | INTERRUPT_BIT))
#define OS_IS_EXT_INT(mcause) (mcause == (0xb | INTERRUPT_BIT))
extern void _tx_timer_interrupt(void);
extern uintptr_t exception(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval);
void (*irq_handler[__riscv_xlen])();
int register_irq_handler(unsigned irq_num, void (*handler)()) {
if(irq_num<__riscv_xlen){
irq_handler[irq_num] = handler;
return 1;
}
return 0;
}
void trap_handler(uintptr_t mcause, uintptr_t mepc, uintptr_t mtval) {
if(OS_IS_INTERRUPT(mcause)) {
unsigned irq_id = mcause&(__riscv_xlen-1);
switch(irq_id){
case RISCV_INT_MTI:
hwtimer_handler();
_tx_timer_interrupt();
break;
case RISCV_INT_MEI:
puts("[INTERRUPT]: handler ext irq error!\n");
while(1)
;
break;
default:
if(irq_handler[irq_id])
irq_handler[irq_id]();
else {
printf("[INTERRUPT]: Unkown Interrupt %d!!\n", mcause&0xff);
puts("[INTERRUPT]: now can't deal with the interrupt!\n");
while(1)
;
}
}
} else {
exception( mcause, mepc, mtval);
}
}

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/*
Baremetal main program with timer interrupt.
SPDX-License-Identifier: Unlicense
https://five-embeddev.com/
Tested with sifive-hifive-revb, but should not have any
dependencies to any particular implementation.
*/
// RISC-V CSR definitions and access classes
#include "riscv-csr.h"
#include "riscv-interrupt.h"
#include "hwtimer.h"
#include "vector_table.h"
extern void _tx_timer_interrupt(void);
// Machine mode interrupt service routine
// Global to hold current timestamp, written in MTI handler.
static volatile uint64_t timestamp = 0;
#define RISCV_MTVEC_MODE_VECTORED 1
int init_irq(void) {
// Global interrupt disable
csr_clr_bits_mstatus(MSTATUS_MIE_BIT_MASK);
csr_write_mie(0);
// Setup the IRQ handler entry point, set the mode to vectored
csr_write_mtvec((uint_xlen_t) riscv_mtvec_table | RISCV_MTVEC_MODE_VECTORED);
// Enable MIE.MTI
csr_set_bits_mie(MIE_MTI_BIT_MASK);
// Global interrupt enable
csr_set_bits_mstatus(MSTATUS_MIE_BIT_MASK);
// Setup timer for 1 second interval
hwtimer_init();
// Busy loop
do {
// Wait for timer interrupt
__asm__ volatile ("wfi");
// Try a synchronous exception.
__asm__ volatile ("ecall");
} while (1);
// Will not reach here
return 0;
}
#pragma GCC push_options
// Force the alignment for mtvec.BASE. A 'C' extension program could be aligned to to bytes.
#pragma GCC optimize ("align-functions=4")
// The 'riscv_mtvec_mti' function is added to the vector table by the vector_table.c
void riscv_mtvec_mti(void) {
hwtimer_handler();
_tx_timer_interrupt();
}
// The 'riscv_mtvec_exception' function is added to the vector table by the vector_table.c
// This function looks at the cause of the exception, if it is an 'ecall' instruction then increment a global counter.
void riscv_mtvec_exception(void) {
uint_xlen_t this_cause = csr_read_mcause();
uint_xlen_t this_pc = csr_read_mepc();
//uint_xlen_t this_value = csr_read_mtval();
switch (this_cause) {
case RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE:
ecall_count++;
// Make sure the return address is the instruction AFTER ecall
csr_write_mepc(this_pc+4);
break;
}
}
#pragma GCC pop_options

134
port/moonlight/tx_timer_interrupt.c Normal file
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/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Timer */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
/* Include necessary system files. */
#include "tx_api.h"
#include "tx_timer.h"
#include "tx_thread.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt RISC-V64/GNU */
/* 6.2.1 */
/* AUTHOR */
/* */
/* Scott Larson, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function processes the hardware timer interrupt. This */
/* processing includes incrementing the system clock and checking for */
/* time slice and/or timer expiration. If either is found, the */
/* interrupt context save/restore functions are called along with the */
/* expiration functions. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* _tx_timer_expiration_process Timer expiration processing */
/* _tx_thread_time_slice Time slice interrupted thread */
/* */
/* CALLED BY */
/* */
/* interrupt vector */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 03-08-2023 Scott Larson Initial Version 6.2.1 */
/* */
/**************************************************************************/
VOID _tx_timer_interrupt(VOID)
{
/* Increment system clock. */
_tx_timer_system_clock++;
/* Test for time-slice expiration. */
if (_tx_timer_time_slice)
{
/* Decrement the time_slice. */
_tx_timer_time_slice--;
/* Check for expiration. */
if (_tx_timer_time_slice == 0)
{
/* Set the time-slice expired flag. */
_tx_timer_expired_time_slice = TX_TRUE;
}
}
/* Test for timer expiration. */
if (*_tx_timer_current_ptr)
{
/* Set expiration flag. */
_tx_timer_expired = TX_TRUE;
}
else
{
/* No timer expired, increment the timer pointer. */
_tx_timer_current_ptr++;
/* Check for wrap-around. */
if (_tx_timer_current_ptr == _tx_timer_list_end)
{
/* Wrap to beginning of list. */
_tx_timer_current_ptr = _tx_timer_list_start;
}
}
/* See if anything has expired. */
if ((_tx_timer_expired_time_slice) || (_tx_timer_expired))
{
/* Did a timer expire? */
if (_tx_timer_expired)
{
/* Process timer expiration. */
_tx_timer_expiration_process();
}
/* Did time slice expire? */
if (_tx_timer_expired_time_slice)
{
/* Time slice interrupted thread. */
_tx_thread_time_slice();
}
}
}

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#ifndef _DEVICES_UART_H
#define _DEVICES_UART_H
#include "gen/uart.h"
#include <stdint.h>
static inline uint32_t uart_get_tx_free(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_free(reg); }
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg) { return get_uart_rx_tx_reg_tx_empty(reg); }
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg) { return get_uart_rx_tx_reg_rx_avail(reg); }
static inline void uart_write(volatile uart_t* reg, uint8_t data) {
while(get_uart_rx_tx_reg_tx_free(reg) == 0)
;
set_uart_rx_tx_reg_data(reg, data);
}
static inline uint8_t uart_read(volatile uart_t* reg) {
uint32_t res = get_uart_rx_tx_reg_data(reg);
while((res & 0x10000) == 0)
res = get_uart_rx_tx_reg_data(reg);
return res;
}
#endif /* _DEVICES_UART_H */

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/*
Baremetal main program with timer interrupt.
SPDX-License-Identifier: Unlicense
https://five-embeddev.com/
Tested with sifive-hifive-revb, but should not have any
dependencies to any particular implementation.
*/
// Makes use of GCC interrupt and weak reference/alias attributes
// https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#Common-Function-Attributes
// https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Function-Attributes.html#RISC-V-Function-Attributes
// Vector table - not to be called.
void riscv_mtvec_table(void) __attribute__ ((naked, section(".text.mtvec_table") ,aligned(256)));
void riscv_stvec_table(void) __attribute__ ((naked, section(".text.stvec_table") ,aligned(256)));
void riscv_utvec_table(void) __attribute__ ((naked, section(".text.utvec_table") ,aligned(256)));
// Default "NOP" implementations
static void riscv_nop_machine(void) __attribute__ ((interrupt ("machine")) );
static void riscv_nop_supervisor(void) __attribute__ ((interrupt ("supervisor")) );
static void riscv_nop_user(void) __attribute__ ((interrupt ("user")) );
// Weak alias to the "NOP" implementations. If another function
void riscv_mtvec_exception(void) __attribute__ ((interrupt ("machine") , weak, alias("riscv_nop_machine") ));
void riscv_mtvec_msi(void) __attribute__ ((interrupt ("machine") , weak, alias("riscv_nop_machine") ));
void riscv_mtvec_mti(void) __attribute__ ((interrupt ("machine") , weak, alias("riscv_nop_machine") ));
void riscv_mtvec_mei(void) __attribute__ ((interrupt ("machine") , weak, alias("riscv_nop_machine") ));
void riscv_mtvec_ssi(void) __attribute__ ((interrupt ("supervisor") , weak, alias("riscv_nop_machine") ));
void riscv_mtvec_sti(void) __attribute__ ((interrupt ("supervisor") , weak, alias("riscv_nop_machine") ));
void riscv_mtvec_sei(void) __attribute__ ((interrupt ("supervisor") , weak, alias("riscv_nop_machine") ));
void riscv_stvec_exception(void) __attribute__ ((interrupt ("supervisor") , weak, alias("riscv_nop_supervisor") ));
void riscv_stvec_ssi(void) __attribute__ ((interrupt ("supervisor") , weak, alias("riscv_nop_supervisor") ));
void riscv_stvec_sti(void) __attribute__ ((interrupt ("supervisor") , weak, alias("riscv_nop_supervisor") ));
void riscv_stvec_sei(void) __attribute__ ((interrupt ("supervisor") , weak, alias("riscv_nop_supervisor") ));
void riscv_utvec_usi(void) __attribute__ ((interrupt ("user") , weak, alias("riscv_nop_user") ));
void riscv_utvec_uti(void) __attribute__ ((interrupt ("user") , weak, alias("riscv_nop_user") ));
void riscv_utvec_uei(void) __attribute__ ((interrupt ("user") , weak, alias("riscv_nop_user") ));
#ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
void moonlight_mtvec_irq0(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq1(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq2(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq3(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq4(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq5(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq6(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq7(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq8(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq9(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq10(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq11(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq12(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq13(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq14(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
void moonlight_mtvec_irq15(void) __attribute__ ((interrupt ("machine"), weak, alias("riscv_nop_machine") ));
#endif // #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
#pragma GCC push_options
// Ensure the vector table is aligned.
// The bottom 4 bits of MTVEC are ignored - so align to 16 bytes
// Vector table. Do not call!
// Possible entries defined by mcause table
// http://five-embeddev.com/riscv-isa-manual/latest/machine.html#sec:mcause
//
// When vectored interrupts are enabled, interrupt cause 0, which
// corresponds to user-mode software interrupts, are vectored to the
// same location as synchronous exceptions. This ambiguity does not
// arise in practice, since user-mode software interrupts are either
// disabled or delegated to user mode.
void riscv_mtvec_table(void) {
__asm__ volatile (
".org riscv_mtvec_table + 0*4;"
"jal zero,riscv_mtvec_exception;" /* 0 */
".org riscv_mtvec_table + 1*4;"
"jal zero,riscv_mtvec_ssi;" /* 1 */
".org riscv_mtvec_table + 3*4;"
"jal zero,riscv_mtvec_msi;" /* 3 */
".org riscv_mtvec_table + 5*4;"
"jal zero,riscv_mtvec_sti;" /* 5 */
".org riscv_mtvec_table + 7*4;"
"jal zero,riscv_mtvec_mti;" /* 7 */
".org riscv_mtvec_table + 9*4;"
"jal zero,riscv_mtvec_sei;" /* 9 */
".org riscv_mtvec_table + 11*4;"
"jal zero,riscv_mtvec_mei;" /* 11 */
#ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
".org riscv_mtvec_table + 16*4;"
"jal moonlight_mtvec_irq0;"
"jal moonlight_mtvec_irq1;"
"jal moonlight_mtvec_irq2;"
"jal moonlight_mtvec_irq3;"
"jal moonlight_mtvec_irq4;"
"jal moonlight_mtvec_irq5;"
"jal moonlight_mtvec_irq6;"
"jal moonlight_mtvec_irq7;"
"jal moonlight_mtvec_irq8;"
"jal moonlight_mtvec_irq9;"
"jal moonlight_mtvec_irq10;"
"jal moonlight_mtvec_irq11;"
"jal moonlight_mtvec_irq12;"
"jal moonlight_mtvec_irq13;"
"jal moonlight_mtvec_irq14;"
"jal moonlight_mtvec_irq15;"
#endif
: /* output: none */
: /* input : immediate */
: /* clobbers: none */
);
}
// Vector table. Do not call!
// See scause table for possible entries.
// http://five-embeddev.com/riscv-isa-manual/latest/supervisor.html#sec:scause
void riscv_stvec_table(void) {
__asm__ volatile (
".org riscv_stvec_table + 0*4;"
"jal zero,riscv_stvec_exception;" /* 0 */
".org riscv_stvec_table + 1*4;"
"jal zero,riscv_stvec_ssi;" /* 1 */
".org riscv_stvec_table + 5*4;"
"jal zero,riscv_stvec_sti;" /* 5 */
".org riscv_stvec_table + 9*4;"
"jal zero,riscv_stvec_sei;" /* 9 */
: /* output: none */
: /* input : immediate */
: /* clobbers: none */
);
}
// Vector table. Do not call!
void riscv_utvec_table(void) {
__asm__ volatile (
".org riscv_utvec_table + 0*4;"
"jal zero,riscv_utvec_usi;" /* 0 */
".org riscv_utvec_table + 4*4;"
"jal zero,riscv_utvec_uti;" /* 4 */
".org riscv_utvec_table + 8*4;"
"jal zero,riscv_utvec_uei;" /* 8 */
: /* output: none */
: /* input : immediate */
: /* clobbers: none */
);
}
// Ensure all ISR functions are aligned.
#pragma GCC optimize ("align-functions=4")
static void riscv_nop_machine(void) {
// Nop machine mode interrupt.
}
static void riscv_nop_supervisor(void) {
// Nop supervisor mode interrupt.
}
static void riscv_nop_user(void) {
// Nop user mode interrupt.
}
#pragma GCC pop_options

113
port/moonlight/vector_table.h Normal file
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@@ -0,0 +1,113 @@
/*
Baremetal main program with timer interrupt.
SPDX-License-Identifier: Unlicense
https://five-embeddev.com/
Tested with sifive-hifive-revb, but should not have any
dependencies to any particular implementation.
Declarations of interrupt service routine entry points.
If no implementation is defined then an alias to a default "NOP"
implementation will be linked instead.
*/
#ifndef VECTOR_TABLE_H
#define VECTOR_TABLE_H
/** Symbol for machine mode vector table - do not call
*/
void riscv_mtvec_table(void) __attribute__ ((naked));
void riscv_stvec_table(void) __attribute__ ((naked));
void riscv_utvec_table(void) __attribute__ ((naked));
/** Machine mode syncronous exception handler.
http://five-embeddev.com/riscv-isa-manual/latest/machine.html#machine-trap-vector-base-address-register-mtvec
When vectored interrupts are enabled, interrupt cause 0, which
corresponds to user-mode software interrupts, are vectored to the same
location as synchronous exceptions. This ambiguity does not arise in
practice, since user-mode software interrupts are either disabled or
delegated to user mode.
*/
void riscv_mtvec_exception(void) __attribute__ ((interrupt ("machine")) );
/** Machine mode software interrupt */
void riscv_mtvec_msi(void) __attribute__ ((interrupt ("machine") ));
/** Machine mode timer interrupt */
void riscv_mtvec_mti(void) __attribute__ ((interrupt ("machine") ));
/** Machine mode al interrupt */
void riscv_mtvec_mei(void) __attribute__ ((interrupt ("machine") ));
/** Supervisor mode software interrupt */
void riscv_mtvec_ssi(void) __attribute__ ((interrupt ("machine")) );
/** Supervisor mode timer interrupt */
void riscv_mtvec_sti(void) __attribute__ ((interrupt ("machine")) );
/** Supervisor mode al interrupt */
void riscv_mtvec_sei(void) __attribute__ ((interrupt ("machine")) );
/** Supervisor mode syncronous exception handler. */
void riscv_stvec_exception(void) __attribute__ ((interrupt ("supervisor")) );
/** Supervisor mode software interrupt */
void riscv_stvec_ssi(void) __attribute__ ((interrupt ("supervisor")) );
/** Supervisor mode timer interrupt */
void riscv_stvec_sti(void) __attribute__ ((interrupt ("supervisor")) );
/** Supervisor mode al interrupt */
void riscv_stvec_sei(void) __attribute__ ((interrupt ("supervisor")) );
/** User mode software interrupt */
void riscv_utvec_usi(void) __attribute__ ((interrupt ("user")) );
/** User mode timer interrupt */
void riscv_utvec_uti(void) __attribute__ ((interrupt ("user")) );
/** User mode al interrupt */
void riscv_utvec_uei(void) __attribute__ ((interrupt ("user")) );
#ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
/* Platform interrupts, bits 16+ of mie, mip etc
*/
/* Platform interrupt 0, bit 16 of mip/mie */
void riscv_mtvec_platform_irq0(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 1, bit 17 of mip/mie */
void riscv_mtvec_platform_irq1(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 2, bit 18 of mip/mie */
void riscv_mtvec_platform_irq2(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 3, bit 19 of mip/mie */
void riscv_mtvec_platform_irq3(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 4, bit 20 of mip/mie */
void riscv_mtvec_platform_irq4(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 5, bit 21 of mip/mie */
void riscv_mtvec_platform_irq5(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 6, bit 22 of mip/mie */
void riscv_mtvec_platform_irq6(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 7, bit 23 of mip/mie */
void riscv_mtvec_platform_irq7(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 8, bit 24 of mip/mie */
void riscv_mtvec_platform_irq8(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 9, bit 25 of mip/mie */
void riscv_mtvec_platform_irq9(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 10, bit 26 of mip/mie */
void riscv_mtvec_platform_irq10(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 11, bit 27 of mip/mie */
void riscv_mtvec_platform_irq11(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 12, bit 28 of mip/mie */
void riscv_mtvec_platform_irq12(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 13, bit 29 of mip/mie */
void riscv_mtvec_platform_irq13(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 14, bit 30 of mip/mie */
void riscv_mtvec_platform_irq14(void) __attribute__ ((interrupt ("machine")) );
/* Platform interrupt 15, bit 31 of mip/mie */
void riscv_mtvec_platform_irq15(void) __attribute__ ((interrupt ("machine")) );
#endif // #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
#endif // #ifndef VECTOR_TABLE_H