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cleans up moonlight dir

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This commit is contained in:
Eyck-Alexander Jentzsch
2026-03-21 15:40:54 +01:00
parent ba1b9c44ee
commit 083565251e
20 changed files with 11 additions and 9 deletions
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44
port/moonlight/inc/aclint.h Normal file
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#ifndef _DEVICES_ACLINT_H
#define _DEVICES_ACLINT_H
#include "gen/aclint.h"
#include <stdint.h>
static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value)
{
set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
set_aclint_mtime_lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtime(volatile aclint_t* reg)
{
#if (__riscv_xlen == 64)
// this assume little endianness
volatile uint64_t* mtime = (volatile uint64_t*)(uint64_t)(&reg->MTIME_LO);
return *mtime;
#else
uint32_t mtimeh_val;
uint32_t mtimel_val;
do
{
mtimeh_val = get_aclint_mtime_hi(reg);
mtimel_val = get_aclint_mtime_lo(reg);
} while (mtimeh_val != get_aclint_mtime_hi(reg));
return (uint64_t)((((uint64_t)mtimeh_val) << 32) | mtimel_val);
#endif
}
static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value)
{
set_aclint_mtimecmp0lo(reg, (uint32_t)0xFFFFFFFF);
set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
set_aclint_mtimecmp0lo(reg, (uint32_t)value);
}
static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg)
{
uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg);
return value;
}
#endif /* _DEVICES_ACLINT_H */

12
port/moonlight/inc/aclint_ipi.h Normal file
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#ifndef _DEVICES_ACLINT_IPI
#define _DEVICES_ACLINT_IPI
#include "gen/aclint.h"
#include "platform.h"
#include <stdint.h>
static void send_ipi(uint32_t target_core)
{
set_aclint_msip(aclint, target_core, 1);
}
#endif /* _DEVICES_ACLINT_IPI */

97
port/moonlight/inc/gen/aclint.h Normal file
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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H
#include <stdint.h>
typedef struct {
volatile uint32_t MSIP[4096];
struct {
volatile uint32_t LO;
volatile uint32_t HI;
} MTIMECMP[4095];
volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI;
} aclint_t;
#define ACLINT_MSIP_OFFS 0
#define ACLINT_MSIP_MASK 0x1
#define ACLINT_MSIP(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
#define ACLINT_MTIMECMPLO_OFFS 0
#define ACLINT_MTIMECMPLO_MASK 0xffffffff
#define ACLINT_MTIMECMPLO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
#define ACLINT_MTIMECMPHI_OFFS 0
#define ACLINT_MTIMECMPHI_MASK 0xffffffff
#define ACLINT_MTIMECMPHI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
#define ACLINT_MTIME_LO_OFFS 0
#define ACLINT_MTIME_LO_MASK 0xffffffff
#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
#define ACLINT_MTIME_HI_OFFS 0
#define ACLINT_MTIME_HI_MASK 0xffffffff
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0
static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP[0]; }
static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP[0] = value; }
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP[0] >> 0) & 0x1; }
static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) {
reg->MSIP[0] = (reg->MSIP[0] & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MSIP
static inline uint32_t get_aclint_msip(volatile aclint_t* reg, unsigned idx) { return reg->MSIP[idx]; }
static inline void set_aclint_msip(volatile aclint_t* reg, unsigned idx, uint32_t value) { reg->MSIP[idx] = value; }
static inline uint32_t get_aclint_msip_msip(volatile aclint_t* reg, unsigned idx) { return (reg->MSIP[idx] >> 0) & 0x1; }
static inline void set_aclint_msip_msip(volatile aclint_t* reg, unsigned idx, uint8_t value) {
reg->MSIP[idx] = (reg->MSIP[idx] & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0LO
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP[0].LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP[0].LO = (reg->MTIMECMP[0].LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMPxLO
static inline uint32_t get_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmplo(volatile aclint_t* reg, unsigned idx, uint32_t value) {
reg->MTIMECMP[idx].LO = (reg->MTIMECMP[idx].LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0HI
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP[0].HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIMECMP[0].HI = (reg->MTIMECMP[0].HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIMECMPxHI
static inline uint32_t get_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx) { return (reg->MTIMECMP[idx].HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtimecmphi(volatile aclint_t* reg, unsigned idx, uint32_t value) {
reg->MTIMECMP[idx].HI = (reg->MTIMECMP[idx].HI & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_LO
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
}
// ACLINT_MTIME_HI
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_ACLINT_H */

477
port/moonlight/inc/gen/ethmac.h Normal file
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/*
* Copyright (c) 2023 - 2026 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2026-01-26 15:33:03 UTC
* by peakrdl_mnrs version 1.3.1
*/
#ifndef _BSP_ETHMAC_H
#define _BSP_ETHMAC_H
#include <stdint.h>
typedef struct {
volatile uint32_t MAC_CTRL;
uint8_t fill0[12];
volatile uint32_t MAC_TX;
volatile uint32_t MAC_TX_AVAILABILITY;
uint8_t fill1[8];
volatile uint32_t MAC_RX;
uint8_t fill2[8];
volatile uint32_t MAC_RX_STATS;
volatile uint32_t MAC_INTR;
uint8_t fill3[12];
volatile uint32_t MDIO_DATA;
volatile uint32_t MDIO_STATUS;
volatile uint32_t MDIO_CONFIG;
volatile uint32_t MDIO_INTR;
uint8_t fill4[16];
volatile uint32_t MDIO_SCLK_CONFIG;
volatile uint32_t MDIO_SSGEN_SETUP;
volatile uint32_t MDIO_SSGEN_HOLD;
volatile uint32_t MDIO_SSGEN_DISABLE;
volatile uint32_t MDIO_SSGEN_ACTIVE_HIGH;
uint8_t fill5[28];
volatile uint32_t MDIO_DIRECT_WRITE;
volatile uint32_t MDIO_DIRECT_READ_WRITE;
volatile uint32_t MDIO_DIRECT_READ;
}ethmac_t;
#define ETHMAC_MAC_CTRL_TX_FLUSH_OFFS 0
#define ETHMAC_MAC_CTRL_TX_FLUSH_MASK 0x1
#define ETHMAC_MAC_CTRL_TX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_TX_FLUSH_MASK) << ETHMAC_MAC_CTRL_TX_FLUSH_OFFS)
#define ETHMAC_MAC_CTRL_TX_READY_OFFS 1
#define ETHMAC_MAC_CTRL_TX_READY_MASK 0x1
#define ETHMAC_MAC_CTRL_TX_READY(V) ((V & ETHMAC_MAC_CTRL_TX_READY_MASK) << ETHMAC_MAC_CTRL_TX_READY_OFFS)
#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS 2
#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK 0x1
#define ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_TX_ALIGNER_ENABLE_OFFS)
#define ETHMAC_MAC_CTRL_RX_FLUSH_OFFS 4
#define ETHMAC_MAC_CTRL_RX_FLUSH_MASK 0x1
#define ETHMAC_MAC_CTRL_RX_FLUSH(V) ((V & ETHMAC_MAC_CTRL_RX_FLUSH_MASK) << ETHMAC_MAC_CTRL_RX_FLUSH_OFFS)
#define ETHMAC_MAC_CTRL_RX_PENDING_OFFS 5
#define ETHMAC_MAC_CTRL_RX_PENDING_MASK 0x1
#define ETHMAC_MAC_CTRL_RX_PENDING(V) ((V & ETHMAC_MAC_CTRL_RX_PENDING_MASK) << ETHMAC_MAC_CTRL_RX_PENDING_OFFS)
#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS 6
#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK 0x1
#define ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE(V) ((V & ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_MASK) << ETHMAC_MAC_CTRL_RX_ALIGNER_ENABLE_OFFS)
#define ETHMAC_MAC_TX_OFFS 0
#define ETHMAC_MAC_TX_MASK 0xffffffff
#define ETHMAC_MAC_TX(V) ((V & ETHMAC_MAC_TX_MASK) << ETHMAC_MAC_TX_OFFS)
#define ETHMAC_MAC_TX_AVAILABILITY_OFFS 0
#define ETHMAC_MAC_TX_AVAILABILITY_MASK 0x7ff
#define ETHMAC_MAC_TX_AVAILABILITY(V) ((V & ETHMAC_MAC_TX_AVAILABILITY_MASK) << ETHMAC_MAC_TX_AVAILABILITY_OFFS)
#define ETHMAC_MAC_RX_OFFS 0
#define ETHMAC_MAC_RX_MASK 0xffffffff
#define ETHMAC_MAC_RX(V) ((V & ETHMAC_MAC_RX_MASK) << ETHMAC_MAC_RX_OFFS)
#define ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS 0
#define ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK 0xff
#define ETHMAC_MAC_RX_STATS_RX_ERRORS(V) ((V & ETHMAC_MAC_RX_STATS_RX_ERRORS_MASK) << ETHMAC_MAC_RX_STATS_RX_ERRORS_OFFS)
#define ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS 8
#define ETHMAC_MAC_RX_STATS_RX_DROPS_MASK 0xff
#define ETHMAC_MAC_RX_STATS_RX_DROPS(V) ((V & ETHMAC_MAC_RX_STATS_RX_DROPS_MASK) << ETHMAC_MAC_RX_STATS_RX_DROPS_OFFS)
#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS 0
#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK 0x1
#define ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_TX_FREE_INTR_ENABLE_OFFS)
#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS 1
#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK 0x1
#define ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE(V) ((V & ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_MASK) << ETHMAC_MAC_INTR_RX_DATA_AVAIL_INTR_ENABLE_OFFS)
#define ETHMAC_MDIO_DATA_DATA_OFFS 0
#define ETHMAC_MDIO_DATA_DATA_MASK 0xff
#define ETHMAC_MDIO_DATA_DATA(V) ((V & ETHMAC_MDIO_DATA_DATA_MASK) << ETHMAC_MDIO_DATA_DATA_OFFS)
#define ETHMAC_MDIO_DATA_WRITE_OFFS 8
#define ETHMAC_MDIO_DATA_WRITE_MASK 0x1
#define ETHMAC_MDIO_DATA_WRITE(V) ((V & ETHMAC_MDIO_DATA_WRITE_MASK) << ETHMAC_MDIO_DATA_WRITE_OFFS)
#define ETHMAC_MDIO_DATA_READ_OFFS 9
#define ETHMAC_MDIO_DATA_READ_MASK 0x1
#define ETHMAC_MDIO_DATA_READ(V) ((V & ETHMAC_MDIO_DATA_READ_MASK) << ETHMAC_MDIO_DATA_READ_OFFS)
#define ETHMAC_MDIO_DATA_SSGEN_OFFS 11
#define ETHMAC_MDIO_DATA_SSGEN_MASK 0x1
#define ETHMAC_MDIO_DATA_SSGEN(V) ((V & ETHMAC_MDIO_DATA_SSGEN_MASK) << ETHMAC_MDIO_DATA_SSGEN_OFFS)
#define ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS 31
#define ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK 0x1
#define ETHMAC_MDIO_DATA_RX_DATA_INVALID(V) ((V & ETHMAC_MDIO_DATA_RX_DATA_INVALID_MASK) << ETHMAC_MDIO_DATA_RX_DATA_INVALID_OFFS)
#define ETHMAC_MDIO_STATUS_TX_FREE_OFFS 0
#define ETHMAC_MDIO_STATUS_TX_FREE_MASK 0x3f
#define ETHMAC_MDIO_STATUS_TX_FREE(V) ((V & ETHMAC_MDIO_STATUS_TX_FREE_MASK) << ETHMAC_MDIO_STATUS_TX_FREE_OFFS)
#define ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS 16
#define ETHMAC_MDIO_STATUS_RX_AVAIL_MASK 0x3f
#define ETHMAC_MDIO_STATUS_RX_AVAIL(V) ((V & ETHMAC_MDIO_STATUS_RX_AVAIL_MASK) << ETHMAC_MDIO_STATUS_RX_AVAIL_OFFS)
#define ETHMAC_MDIO_CONFIG_CPOL_OFFS 0
#define ETHMAC_MDIO_CONFIG_CPOL_MASK 0x1
#define ETHMAC_MDIO_CONFIG_CPOL(V) ((V & ETHMAC_MDIO_CONFIG_CPOL_MASK) << ETHMAC_MDIO_CONFIG_CPOL_OFFS)
#define ETHMAC_MDIO_CONFIG_CPHA_OFFS 1
#define ETHMAC_MDIO_CONFIG_CPHA_MASK 0x1
#define ETHMAC_MDIO_CONFIG_CPHA(V) ((V & ETHMAC_MDIO_CONFIG_CPHA_MASK) << ETHMAC_MDIO_CONFIG_CPHA_OFFS)
#define ETHMAC_MDIO_CONFIG_MODE_OFFS 4
#define ETHMAC_MDIO_CONFIG_MODE_MASK 0x1
#define ETHMAC_MDIO_CONFIG_MODE(V) ((V & ETHMAC_MDIO_CONFIG_MODE_MASK) << ETHMAC_MDIO_CONFIG_MODE_OFFS)
#define ETHMAC_MDIO_INTR_TX_IE_OFFS 0
#define ETHMAC_MDIO_INTR_TX_IE_MASK 0x1
#define ETHMAC_MDIO_INTR_TX_IE(V) ((V & ETHMAC_MDIO_INTR_TX_IE_MASK) << ETHMAC_MDIO_INTR_TX_IE_OFFS)
#define ETHMAC_MDIO_INTR_RX_IE_OFFS 1
#define ETHMAC_MDIO_INTR_RX_IE_MASK 0x1
#define ETHMAC_MDIO_INTR_RX_IE(V) ((V & ETHMAC_MDIO_INTR_RX_IE_MASK) << ETHMAC_MDIO_INTR_RX_IE_OFFS)
#define ETHMAC_MDIO_INTR_TX_IP_OFFS 8
#define ETHMAC_MDIO_INTR_TX_IP_MASK 0x1
#define ETHMAC_MDIO_INTR_TX_IP(V) ((V & ETHMAC_MDIO_INTR_TX_IP_MASK) << ETHMAC_MDIO_INTR_TX_IP_OFFS)
#define ETHMAC_MDIO_INTR_RX_IP_OFFS 9
#define ETHMAC_MDIO_INTR_RX_IP_MASK 0x1
#define ETHMAC_MDIO_INTR_RX_IP(V) ((V & ETHMAC_MDIO_INTR_RX_IP_MASK) << ETHMAC_MDIO_INTR_RX_IP_OFFS)
#define ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS 16
#define ETHMAC_MDIO_INTR_TX_ACTIVE_MASK 0x1
#define ETHMAC_MDIO_INTR_TX_ACTIVE(V) ((V & ETHMAC_MDIO_INTR_TX_ACTIVE_MASK) << ETHMAC_MDIO_INTR_TX_ACTIVE_OFFS)
#define ETHMAC_MDIO_SCLK_CONFIG_OFFS 0
#define ETHMAC_MDIO_SCLK_CONFIG_MASK 0xfff
#define ETHMAC_MDIO_SCLK_CONFIG(V) ((V & ETHMAC_MDIO_SCLK_CONFIG_MASK) << ETHMAC_MDIO_SCLK_CONFIG_OFFS)
#define ETHMAC_MDIO_SSGEN_SETUP_OFFS 0
#define ETHMAC_MDIO_SSGEN_SETUP_MASK 0xfff
#define ETHMAC_MDIO_SSGEN_SETUP(V) ((V & ETHMAC_MDIO_SSGEN_SETUP_MASK) << ETHMAC_MDIO_SSGEN_SETUP_OFFS)
#define ETHMAC_MDIO_SSGEN_HOLD_OFFS 0
#define ETHMAC_MDIO_SSGEN_HOLD_MASK 0xfff
#define ETHMAC_MDIO_SSGEN_HOLD(V) ((V & ETHMAC_MDIO_SSGEN_HOLD_MASK) << ETHMAC_MDIO_SSGEN_HOLD_OFFS)
#define ETHMAC_MDIO_SSGEN_DISABLE_OFFS 0
#define ETHMAC_MDIO_SSGEN_DISABLE_MASK 0xfff
#define ETHMAC_MDIO_SSGEN_DISABLE(V) ((V & ETHMAC_MDIO_SSGEN_DISABLE_MASK) << ETHMAC_MDIO_SSGEN_DISABLE_OFFS)
#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS 0
#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK 0x1
#define ETHMAC_MDIO_SSGEN_ACTIVE_HIGH(V) ((V & ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_MASK) << ETHMAC_MDIO_SSGEN_ACTIVE_HIGH_OFFS)
#define ETHMAC_MDIO_DIRECT_WRITE_OFFS 0
#define ETHMAC_MDIO_DIRECT_WRITE_MASK 0xff
#define ETHMAC_MDIO_DIRECT_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_WRITE_MASK) << ETHMAC_MDIO_DIRECT_WRITE_OFFS)
#define ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS 0
#define ETHMAC_MDIO_DIRECT_READ_WRITE_MASK 0xff
#define ETHMAC_MDIO_DIRECT_READ_WRITE(V) ((V & ETHMAC_MDIO_DIRECT_READ_WRITE_MASK) << ETHMAC_MDIO_DIRECT_READ_WRITE_OFFS)
#define ETHMAC_MDIO_DIRECT_READ_OFFS 0
#define ETHMAC_MDIO_DIRECT_READ_MASK 0xff
#define ETHMAC_MDIO_DIRECT_READ(V) ((V & ETHMAC_MDIO_DIRECT_READ_MASK) << ETHMAC_MDIO_DIRECT_READ_OFFS)
//ETHMAC_MAC_CTRL
static inline uint32_t get_ethmac_mac_ctrl(volatile ethmac_t* reg){
return reg->MAC_CTRL;
}
static inline void set_ethmac_mac_ctrl(volatile ethmac_t* reg, uint32_t value){
reg->MAC_CTRL = value;
}
static inline uint32_t get_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 0) & 0x1;
}
static inline void set_ethmac_mac_ctrl_tx_flush(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mac_ctrl_tx_ready(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 1) & 0x1;
}
static inline uint32_t get_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 2) & 0x1;
}
static inline void set_ethmac_mac_ctrl_tx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 4) & 0x1;
}
static inline void set_ethmac_mac_ctrl_rx_flush(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_ethmac_mac_ctrl_rx_pending(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 5) & 0x1;
}
static inline uint32_t get_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg){
return (reg->MAC_CTRL >> 6) & 0x1;
}
static inline void set_ethmac_mac_ctrl_rx_aligner_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_CTRL = (reg->MAC_CTRL & ~(0x1U << 6)) | (value << 6);
}
//ETHMAC_MAC_TX
static inline uint32_t get_ethmac_mac_tx(volatile ethmac_t* reg){
return (reg->MAC_TX >> 0) & 0xffffffff;
}
static inline void set_ethmac_mac_tx(volatile ethmac_t* reg, uint32_t value){
reg->MAC_TX = (reg->MAC_TX & ~(0xffffffffU << 0)) | (value << 0);
}
//ETHMAC_MAC_TX_AVAILABILITY
static inline uint32_t get_ethmac_mac_tx_availability(volatile ethmac_t* reg){
return reg->MAC_TX_AVAILABILITY;
}
static inline uint32_t get_ethmac_mac_tx_availability_words_avail(volatile ethmac_t* reg){
return (reg->MAC_TX_AVAILABILITY >> 0) & 0x7ff;
}
//ETHMAC_MAC_RX
static inline uint32_t get_ethmac_mac_rx(volatile ethmac_t* reg){
return (reg->MAC_RX >> 0) & 0xffffffff;
}
//ETHMAC_MAC_RX_STATS
static inline uint32_t get_ethmac_mac_rx_stats(volatile ethmac_t* reg){
return reg->MAC_RX_STATS;
}
static inline uint32_t get_ethmac_mac_rx_stats_rx_errors(volatile ethmac_t* reg){
return (reg->MAC_RX_STATS >> 0) & 0xff;
}
static inline uint32_t get_ethmac_mac_rx_stats_rx_drops(volatile ethmac_t* reg){
return (reg->MAC_RX_STATS >> 8) & 0xff;
}
//ETHMAC_MAC_INTR
static inline uint32_t get_ethmac_mac_intr(volatile ethmac_t* reg){
return reg->MAC_INTR;
}
static inline void set_ethmac_mac_intr(volatile ethmac_t* reg, uint32_t value){
reg->MAC_INTR = value;
}
static inline uint32_t get_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg){
return (reg->MAC_INTR >> 0) & 0x1;
}
static inline void set_ethmac_mac_intr_tx_free_intr_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg){
return (reg->MAC_INTR >> 1) & 0x1;
}
static inline void set_ethmac_mac_intr_rx_data_avail_intr_enable(volatile ethmac_t* reg, uint8_t value){
reg->MAC_INTR = (reg->MAC_INTR & ~(0x1U << 1)) | (value << 1);
}
//ETHMAC_MDIO_DATA
static inline uint32_t get_ethmac_mdio_data(volatile ethmac_t* reg){
return reg->MDIO_DATA;
}
static inline void set_ethmac_mdio_data(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_DATA = value;
}
static inline uint32_t get_ethmac_mdio_data_data(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 0) & 0xff;
}
static inline void set_ethmac_mdio_data_data(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mdio_data_write(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 8) & 0x1;
}
static inline void set_ethmac_mdio_data_write(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t get_ethmac_mdio_data_read(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 9) & 0x1;
}
static inline void set_ethmac_mdio_data_read(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_ethmac_mdio_data_ssgen(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 11) & 0x1;
}
static inline void set_ethmac_mdio_data_ssgen(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DATA = (reg->MDIO_DATA & ~(0x1U << 11)) | (value << 11);
}
static inline uint32_t get_ethmac_mdio_data_rx_data_invalid(volatile ethmac_t* reg){
return (reg->MDIO_DATA >> 31) & 0x1;
}
//ETHMAC_MDIO_STATUS
static inline uint32_t get_ethmac_mdio_status(volatile ethmac_t* reg){
return reg->MDIO_STATUS;
}
static inline uint32_t get_ethmac_mdio_status_tx_free(volatile ethmac_t* reg){
return (reg->MDIO_STATUS >> 0) & 0x3f;
}
static inline uint32_t get_ethmac_mdio_status_rx_avail(volatile ethmac_t* reg){
return (reg->MDIO_STATUS >> 16) & 0x3f;
}
//ETHMAC_MDIO_CONFIG
static inline uint32_t get_ethmac_mdio_config(volatile ethmac_t* reg){
return reg->MDIO_CONFIG;
}
static inline void set_ethmac_mdio_config(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_CONFIG = value;
}
static inline uint32_t get_ethmac_mdio_config_cpol(volatile ethmac_t* reg){
return (reg->MDIO_CONFIG >> 0) & 0x1;
}
static inline void set_ethmac_mdio_config_cpol(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mdio_config_cpha(volatile ethmac_t* reg){
return (reg->MDIO_CONFIG >> 1) & 0x1;
}
static inline void set_ethmac_mdio_config_cpha(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_ethmac_mdio_config_mode(volatile ethmac_t* reg){
return (reg->MDIO_CONFIG >> 4) & 0x1;
}
static inline void set_ethmac_mdio_config_mode(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_CONFIG = (reg->MDIO_CONFIG & ~(0x1U << 4)) | (value << 4);
}
//ETHMAC_MDIO_INTR
static inline uint32_t get_ethmac_mdio_intr(volatile ethmac_t* reg){
return reg->MDIO_INTR;
}
static inline void set_ethmac_mdio_intr(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_INTR = value;
}
static inline uint32_t get_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 0) & 0x1;
}
static inline void set_ethmac_mdio_intr_tx_ie(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 1) & 0x1;
}
static inline void set_ethmac_mdio_intr_rx_ie(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 8) & 0x1;
}
static inline void set_ethmac_mdio_intr_tx_ip(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 8)) | (value << 8);
}
static inline uint32_t get_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 9) & 0x1;
}
static inline void set_ethmac_mdio_intr_rx_ip(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_INTR = (reg->MDIO_INTR & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_ethmac_mdio_intr_tx_active(volatile ethmac_t* reg){
return (reg->MDIO_INTR >> 16) & 0x1;
}
//ETHMAC_MDIO_SCLK_CONFIG
static inline uint32_t get_ethmac_mdio_sclk_config(volatile ethmac_t* reg){
return reg->MDIO_SCLK_CONFIG;
}
static inline void set_ethmac_mdio_sclk_config(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SCLK_CONFIG = value;
}
static inline uint32_t get_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg){
return (reg->MDIO_SCLK_CONFIG >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_sclk_config_clk_divider(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SCLK_CONFIG = (reg->MDIO_SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_SETUP
static inline uint32_t get_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_SETUP;
}
static inline void set_ethmac_mdio_ssgen_setup(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_SETUP = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_SETUP >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_ssgen_setup_setup_cycles(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SSGEN_SETUP = (reg->MDIO_SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_HOLD
static inline uint32_t get_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_HOLD;
}
static inline void set_ethmac_mdio_ssgen_hold(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_HOLD = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_HOLD >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_ssgen_hold_hold_cycles(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SSGEN_HOLD = (reg->MDIO_SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_DISABLE
static inline uint32_t get_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_DISABLE;
}
static inline void set_ethmac_mdio_ssgen_disable(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_DISABLE = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_DISABLE >> 0) & 0xfff;
}
static inline void set_ethmac_mdio_ssgen_disable_disable_cycles(volatile ethmac_t* reg, uint16_t value){
reg->MDIO_SSGEN_DISABLE = (reg->MDIO_SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_SSGEN_ACTIVE_HIGH
static inline uint32_t get_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg){
return reg->MDIO_SSGEN_ACTIVE_HIGH;
}
static inline void set_ethmac_mdio_ssgen_active_high(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_SSGEN_ACTIVE_HIGH = value;
}
static inline uint32_t get_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg){
return (reg->MDIO_SSGEN_ACTIVE_HIGH >> 0) & 0x1;
}
static inline void set_ethmac_mdio_ssgen_active_high_spi_cs_active_high(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_SSGEN_ACTIVE_HIGH = (reg->MDIO_SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
}
//ETHMAC_MDIO_DIRECT_WRITE
static inline void set_ethmac_mdio_direct_write(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_DIRECT_WRITE = value;
}
static inline void set_ethmac_mdio_direct_write_data(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DIRECT_WRITE = (reg->MDIO_DIRECT_WRITE & ~(0xffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_DIRECT_READ_WRITE
static inline void set_ethmac_mdio_direct_read_write(volatile ethmac_t* reg, uint32_t value){
reg->MDIO_DIRECT_READ_WRITE = value;
}
static inline void set_ethmac_mdio_direct_read_write_data(volatile ethmac_t* reg, uint8_t value){
reg->MDIO_DIRECT_READ_WRITE = (reg->MDIO_DIRECT_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
//ETHMAC_MDIO_DIRECT_READ
static inline uint32_t get_ethmac_mdio_direct_read(volatile ethmac_t* reg){
return reg->MDIO_DIRECT_READ;
}
static inline uint32_t get_ethmac_mdio_direct_read_data(volatile ethmac_t* reg){
return (reg->MDIO_DIRECT_READ >> 0) & 0xff;
}
#endif /* _BSP_ETHMAC_H */

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/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_UART_H
#define _BSP_UART_H
#include <stdint.h>
typedef struct {
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
} uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
#define UART_RX_TX_REG_TX_FREE_OFFS 15
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
#define UART_CLK_DIVIDER_REG_OFFS 0
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
#define UART_STATUS_REG_READ_ERROR_OFFS 0
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
#define UART_STATUS_REG_STALL_OFFS 1
#define UART_STATUS_REG_STALL_MASK 0x1
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
#define UART_STATUS_REG_BREAK_LINE_OFFS 8
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
#define UART_STATUS_REG_SET_BREAK_OFFS 10
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
// UART_INT_CTRL_REG
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
// UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
// UART_FRAME_CONFIG_REG
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
// UART_STATUS_REG
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_UART_H */

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port/moonlight/inc/hwtimer.h Normal file
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/***************************************************************************
* Copyright (c) 2024 Microsoft Corporation
*
* This program and the accompanying materials are made available under the
* terms of the MIT License which is available at
* https://opensource.org/licenses/MIT.
*
* SPDX-License-Identifier: MIT
**************************************************************************/
#ifndef RISCV_HWTIMER_H
#define RISCV_HWTIMER_H
#include "platform.h"
#define TICKNUM_PER_SECOND 32768
#define TICKNUM_PER_TIMER (TICKNUM_PER_SECOND / 1000) // ~ 1ms timer
static inline int hwtimer_init(void)
{
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;
}
static inline int hwtimer_handler(void)
{
uint64_t time = get_aclint_mtime(aclint);
set_aclint_mtimecmp(aclint, time + TICKNUM_PER_TIMER);
return 0;
}
#endif

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port/moonlight/inc/platform.h Normal file
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#include "aclint.h"
#include "gen/ethmac.h"
#include "riscv-csr.h"
#include "riscv-traps.h"
#include "uart.h"
#define PERIPH(TYPE, ADDR) ((volatile TYPE*)(ADDR))
#define PERIPH_BASE 0x10000000
#define uart PERIPH(uart_t, PERIPH_BASE + 0x01000)
#define aclint PERIPH(aclint_t, PERIPH_BASE + 0x30000)
#define ethmac0 PERIPH(ethmac_t, PERIPH_BASE + 0x1000000)
#define ethmac1 PERIPH(ethmac_t, PERIPH_BASE + 0x1001000)
#define UART0_IRQ 16
#define TIMER0_IRQ0 17
#define TIMER0_IRQ1 18
#define QSPI_IRQ 19
#define I2S_IRQ 20
#define CAM_IRQ 21
#define DMA_IRQ 22
#define GPIO_ORQ 23
#define ETH0_IRQ 24
#define ETH1_IRQ 25

4157
port/moonlight/inc/riscv-csr.h Normal file
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71
port/moonlight/inc/riscv-traps.h Normal file
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/*
RISC-V machine interrupts.
SPDX-License-Identifier: Unlicense
https://five-embeddev.com/
*/
#ifndef RISCV_TRAPS_H
#define RISCV_TRAPS_H
enum
{
RISCV_INT_MSI = 3,
RISCV_INT_MTI = 7,
RISCV_INT_MEI = 11,
RISCV_INT_SSI = 1,
RISCV_INT_STI = 5,
RISCV_INT_SEI = 9,
RISCV_INT_USI = 0,
RISCV_INT_UTI = 4,
RISCV_INT_UEI = 8,
};
enum
{
RISCV_INT_POS_MSI = 3,
RISCV_INT_POS_MTI = 7,
RISCV_INT_POS_MEI = 11,
RISCV_INT_POS_SSI = 1,
RISCV_INT_POS_STI = 5,
RISCV_INT_POS_SEI = 9,
RISCV_INT_POS_USI = 0,
RISCV_INT_POS_UTI = 4,
RISCV_INT_POS_UEI = 8,
};
enum
{
RISCV_INT_MASK_MSI = (1UL << RISCV_INT_POS_MSI),
RISCV_INT_MASK_MTI = (1UL << RISCV_INT_POS_MTI),
RISCV_INT_MASK_MEI = (1UL << RISCV_INT_POS_MEI),
RISCV_INT_MASK_SSI = (1UL << RISCV_INT_POS_SSI),
RISCV_INT_MASK_STI = (1UL << RISCV_INT_POS_STI),
RISCV_INT_MASK_SEI = (1UL << RISCV_INT_POS_SEI),
RISCV_INT_MASK_USI = (1UL << RISCV_INT_POS_USI),
RISCV_INT_MASK_UTI = (1UL << RISCV_INT_POS_UTI),
RISCV_INT_MASK_UEI = (1UL << RISCV_INT_POS_UEI),
};
enum
{
RISCV_EXCP_INSTRUCTION_ADDRESS_MISALIGNED = 0, /* Instruction address misaligned */
RISCV_EXCP_INSTRUCTION_ACCESS_FAULT = 1, /* Instruction access fault */
RISCV_EXCP_ILLEGAL_INSTRUCTION = 2, /* Illegal instruction */
RISCV_EXCP_BREAKPOINT = 3, /* Breakpoint */
RISCV_EXCP_LOAD_ADDRESS_MISALIGNED = 4, /* Load address misaligned */
RISCV_EXCP_LOAD_ACCESS_FAULT = 5, /* Load access fault */
RISCV_EXCP_STORE_AMO_ADDRESS_MISALIGNED = 6, /* Store/AMO address misaligned */
RISCV_EXCP_STORE_AMO_ACCESS_FAULT = 7, /* Store/AMO access fault */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_U_MODE = 8, /* Environment call from U-mode */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_S_MODE = 9, /* Environment call from S-mode */
RISCV_EXCP_RESERVED10 = 10, /* Reserved */
RISCV_EXCP_ENVIRONMENT_CALL_FROM_M_MODE = 11, /* Environment call from M-mode */
RISCV_EXCP_INSTRUCTION_PAGE_FAULT = 12, /* Instruction page fault */
RISCV_EXCP_LOAD_PAGE_FAULT = 13, /* Load page fault */
RISCV_EXCP_RESERVED14 = 14, /* Reserved */
RISCV_EXCP_STORE_AMO_PAGE_FAULT = 15, /* Store/AMO page fault */
};
#endif /* RISCV_TRAPS_H */

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#ifndef _DEVICES_UART_H
#define _DEVICES_UART_H
#include "gen/uart.h"
#include <stdint.h>
static inline uint32_t uart_get_tx_free(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_tx_free(reg);
}
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_tx_empty(reg);
}
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg)
{
return get_uart_rx_tx_reg_rx_avail(reg);
}
static inline void uart_write(volatile uart_t* reg, uint8_t data)
{
while (get_uart_rx_tx_reg_tx_free(reg) == 0)
;
set_uart_rx_tx_reg_data(reg, data);
}
static inline uint8_t uart_read(volatile uart_t* reg)
{
uint32_t res = get_uart_rx_tx_reg_data(reg);
while ((res & 0x10000) == 0)
res = get_uart_rx_tx_reg_data(reg);
return res;
}
#endif /* _DEVICES_UART_H */

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port/moonlight/inc/vector_table.h Normal file
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/*
Baremetal main program with timer interrupt.
SPDX-License-Identifier: Unlicense
https://five-embeddev.com/
Tested with sifive-hifive-revb, but should not have any
dependencies to any particular implementation.
Declarations of interrupt service routine entry points.
If no implementation is defined then an alias to a default "NOP"
implementation will be linked instead.
*/
#ifndef VECTOR_TABLE_H
#define VECTOR_TABLE_H
/** Symbol for machine mode vector table - do not call
*/
void riscv_mtvec_table(void) __attribute__((naked));
void riscv_stvec_table(void) __attribute__((naked));
void riscv_utvec_table(void) __attribute__((naked));
/** Machine mode syncronous exception handler.
http://five-embeddev.com/riscv-isa-manual/latest/machine.html#machine-trap-vector-base-address-register-mtvec
When vectored interrupts are enabled, interrupt cause 0, which
corresponds to user-mode software interrupts, are vectored to the same
location as synchronous exceptions. This ambiguity does not arise in
practice, since user-mode software interrupts are either disabled or
delegated to user mode.
*/
void riscv_mtvec_exception(void) __attribute__((interrupt("machine")));
/** Machine mode software interrupt */
void riscv_mtvec_msi(void) __attribute__((interrupt("machine")));
/** Machine mode timer interrupt */
void riscv_mtvec_mti(void) __attribute__((interrupt("machine")));
/** Machine mode al interrupt */
void riscv_mtvec_mei(void) __attribute__((interrupt("machine")));
/** Supervisor mode software interrupt */
void riscv_mtvec_ssi(void) __attribute__((interrupt("machine")));
/** Supervisor mode timer interrupt */
void riscv_mtvec_sti(void) __attribute__((interrupt("machine")));
/** Supervisor mode al interrupt */
void riscv_mtvec_sei(void) __attribute__((interrupt("machine")));
/** Supervisor mode syncronous exception handler. */
void riscv_stvec_exception(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode software interrupt */
void riscv_stvec_ssi(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode timer interrupt */
void riscv_stvec_sti(void) __attribute__((interrupt("supervisor")));
/** Supervisor mode al interrupt */
void riscv_stvec_sei(void) __attribute__((interrupt("supervisor")));
/** User mode software interrupt */
void riscv_utvec_usi(void) __attribute__((interrupt("user")));
/** User mode timer interrupt */
void riscv_utvec_uti(void) __attribute__((interrupt("user")));
/** User mode al interrupt */
void riscv_utvec_uei(void) __attribute__((interrupt("user")));
#ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
/* Platform interrupts, bits 16+ of mie, mip etc
*/
/* Platform interrupt 0, bit 16 of mip/mie */
void riscv_mtvec_platform_irq0(void) __attribute__((interrupt("machine")));
/* Platform interrupt 1, bit 17 of mip/mie */
void riscv_mtvec_platform_irq1(void) __attribute__((interrupt("machine")));
/* Platform interrupt 2, bit 18 of mip/mie */
void riscv_mtvec_platform_irq2(void) __attribute__((interrupt("machine")));
/* Platform interrupt 3, bit 19 of mip/mie */
void riscv_mtvec_platform_irq3(void) __attribute__((interrupt("machine")));
/* Platform interrupt 4, bit 20 of mip/mie */
void riscv_mtvec_platform_irq4(void) __attribute__((interrupt("machine")));
/* Platform interrupt 5, bit 21 of mip/mie */
void riscv_mtvec_platform_irq5(void) __attribute__((interrupt("machine")));
/* Platform interrupt 6, bit 22 of mip/mie */
void riscv_mtvec_platform_irq6(void) __attribute__((interrupt("machine")));
/* Platform interrupt 7, bit 23 of mip/mie */
void riscv_mtvec_platform_irq7(void) __attribute__((interrupt("machine")));
/* Platform interrupt 8, bit 24 of mip/mie */
void riscv_mtvec_platform_irq8(void) __attribute__((interrupt("machine")));
/* Platform interrupt 9, bit 25 of mip/mie */
void riscv_mtvec_platform_irq9(void) __attribute__((interrupt("machine")));
/* Platform interrupt 10, bit 26 of mip/mie */
void riscv_mtvec_platform_irq10(void) __attribute__((interrupt("machine")));
/* Platform interrupt 11, bit 27 of mip/mie */
void riscv_mtvec_platform_irq11(void) __attribute__((interrupt("machine")));
/* Platform interrupt 12, bit 28 of mip/mie */
void riscv_mtvec_platform_irq12(void) __attribute__((interrupt("machine")));
/* Platform interrupt 13, bit 29 of mip/mie */
void riscv_mtvec_platform_irq13(void) __attribute__((interrupt("machine")));
/* Platform interrupt 14, bit 30 of mip/mie */
void riscv_mtvec_platform_irq14(void) __attribute__((interrupt("machine")));
/* Platform interrupt 15, bit 31 of mip/mie */
void riscv_mtvec_platform_irq15(void) __attribute__((interrupt("machine")));
#endif // #ifndef VECTOR_TABLE_MTVEC_PLATFORM_INTS
#endif // #ifndef VECTOR_TABLE_H