230 lines
9.5 KiB
C
230 lines
9.5 KiB
C
/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-06-08 13:20:02 UTC
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* by peakrdl_mnrs version 1.2.5
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*/
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#ifndef _BSP_UART_H
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#define _BSP_UART_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t RX_TX_REG;
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volatile uint32_t INT_CTRL_REG;
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volatile uint32_t CLK_DIVIDER_REG;
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volatile uint32_t FRAME_CONFIG_REG;
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volatile uint32_t STATUS_REG;
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}uart_t;
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#define UART_RX_TX_REG_DATA_OFFS 0
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#define UART_RX_TX_REG_DATA_MASK 0xff
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#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
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#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
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#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
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#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
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#define UART_RX_TX_REG_TX_FREE_OFFS 15
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#define UART_RX_TX_REG_TX_FREE_MASK 0x1
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#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
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#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
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#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
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#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
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#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
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#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
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#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
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#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
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#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
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#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
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#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
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#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
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#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
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#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
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#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
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#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
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#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
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#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
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#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
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#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
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#define UART_CLK_DIVIDER_REG_OFFS 0
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#define UART_CLK_DIVIDER_REG_MASK 0xfffff
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#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
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#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0
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#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7
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#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS)
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#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
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#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
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#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
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#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
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#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
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#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
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#define UART_STATUS_REG_READ_ERROR_OFFS 0
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#define UART_STATUS_REG_READ_ERROR_MASK 0x1
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#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
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#define UART_STATUS_REG_STALL_OFFS 1
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#define UART_STATUS_REG_STALL_MASK 0x1
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#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
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#define UART_STATUS_REG_BREAK_LINE_OFFS 8
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#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
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#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
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#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
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#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
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#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
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#define UART_STATUS_REG_SET_BREAK_OFFS 10
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#define UART_STATUS_REG_SET_BREAK_MASK 0x1
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#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
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#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
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#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
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#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
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//UART_RX_TX_REG
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inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
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return reg->RX_TX_REG;
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}
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inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
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reg->RX_TX_REG = value;
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}
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inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
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return (reg->RX_TX_REG >> 0) & 0xff;
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}
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inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
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reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
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}
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inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
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return (reg->RX_TX_REG >> 14) & 0x1;
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}
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inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
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return (reg->RX_TX_REG >> 15) & 0x1;
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}
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inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
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return (reg->RX_TX_REG >> 16) & 0x1;
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}
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//UART_INT_CTRL_REG
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inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
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return reg->INT_CTRL_REG;
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}
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inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
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reg->INT_CTRL_REG = value;
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}
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inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
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return (reg->INT_CTRL_REG >> 0) & 0x1;
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}
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inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
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reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
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return (reg->INT_CTRL_REG >> 1) & 0x1;
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}
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inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
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reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
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}
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inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
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return (reg->INT_CTRL_REG >> 2) & 0x1;
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}
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inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
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reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
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}
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inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
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return (reg->INT_CTRL_REG >> 8) & 0x1;
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}
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inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
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return (reg->INT_CTRL_REG >> 9) & 0x1;
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}
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inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
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return (reg->INT_CTRL_REG >> 10) & 0x1;
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}
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//UART_CLK_DIVIDER_REG
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inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
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return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
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}
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inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
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reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
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}
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//UART_FRAME_CONFIG_REG
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inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
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return reg->FRAME_CONFIG_REG;
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}
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inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
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reg->FRAME_CONFIG_REG = value;
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}
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inline uint32_t get_uart_frame_config_reg_data_lenght(volatile uart_t* reg){
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return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
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}
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inline void set_uart_frame_config_reg_data_lenght(volatile uart_t* reg, uint8_t value){
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reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
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}
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inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
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return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
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}
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inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
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reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
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}
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inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
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return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
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}
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inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
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reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
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}
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//UART_STATUS_REG
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inline uint32_t get_uart_status_reg(volatile uart_t* reg){
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return reg->STATUS_REG;
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}
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inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
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reg->STATUS_REG = value;
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}
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inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
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return (reg->STATUS_REG >> 0) & 0x1;
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}
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inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
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return (reg->STATUS_REG >> 1) & 0x1;
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}
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inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
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return (reg->STATUS_REG >> 8) & 0x1;
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}
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inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
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return (reg->STATUS_REG >> 9) & 0x1;
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}
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inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
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reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
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}
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inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
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return (reg->STATUS_REG >> 10) & 0x1;
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}
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inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
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reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
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}
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inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
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return (reg->STATUS_REG >> 11) & 0x1;
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}
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inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
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reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
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}
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#endif /* _BSP_UART_H */ |