382 lines
14 KiB
C
382 lines
14 KiB
C
/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-03-28 11:32:47 UTC
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* by peakrdl_mnrs version 1.2.4
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*/
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#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
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#define _BSP_APB3SPIXDRMASTERCTRL_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t DATA;
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volatile uint32_t STATUS;
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volatile uint32_t CONFIG;
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volatile uint32_t INTR;
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uint8_t fill4 [16];
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volatile uint32_t SCLK_CONFIG;
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volatile uint32_t SSGEN_SETUP;
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volatile uint32_t SSGEN_HOLD;
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volatile uint32_t SSGEN_DISABLE;
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volatile uint32_t SSGEN_ACTIVE_HIGH;
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uint8_t fill9 [12];
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volatile uint32_t XIP_ENABLE;
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volatile uint32_t XIP_CONFIG;
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volatile uint32_t XIP_MODE;
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uint8_t fill12 [4];
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volatile uint32_t XIP_WRITE;
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volatile uint32_t XIP_READ_WRITE;
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volatile uint32_t XIP_READ;
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}apb3spixdrmasterctrl_t;
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#define SPI_DATA_DATA_OFFS 0
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#define SPI_DATA_DATA_MASK 0xff
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#define SPI_DATA_DATA(V) ((V & SPI_DATA_DATA_MASK) << SPI_DATA_DATA_OFFS)
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#define SPI_DATA_WRITE_OFFS 8
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#define SPI_DATA_WRITE_MASK 0x1
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#define SPI_DATA_WRITE(V) ((V & SPI_DATA_WRITE_MASK) << SPI_DATA_WRITE_OFFS)
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#define SPI_DATA_READ_OFFS 9
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#define SPI_DATA_READ_MASK 0x1
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#define SPI_DATA_READ(V) ((V & SPI_DATA_READ_MASK) << SPI_DATA_READ_OFFS)
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#define SPI_DATA_KIND_OFFS 11
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#define SPI_DATA_KIND_MASK 0x1
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#define SPI_DATA_KIND(V) ((V & SPI_DATA_KIND_MASK) << SPI_DATA_KIND_OFFS)
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#define SPI_DATA_RX_DATA_INVALID_OFFS 31
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#define SPI_DATA_RX_DATA_INVALID_MASK 0x1
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#define SPI_DATA_RX_DATA_INVALID(V) ((V & SPI_DATA_RX_DATA_INVALID_MASK) << SPI_DATA_RX_DATA_INVALID_OFFS)
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#define SPI_STATUS_TX_FREE_OFFS 0
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#define SPI_STATUS_TX_FREE_MASK 0x3f
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#define SPI_STATUS_TX_FREE(V) ((V & SPI_STATUS_TX_FREE_MASK) << SPI_STATUS_TX_FREE_OFFS)
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#define SPI_STATUS_RX_AVAIL_OFFS 16
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#define SPI_STATUS_RX_AVAIL_MASK 0x3f
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#define SPI_STATUS_RX_AVAIL(V) ((V & SPI_STATUS_RX_AVAIL_MASK) << SPI_STATUS_RX_AVAIL_OFFS)
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#define SPI_CONFIG_KIND_OFFS 0
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#define SPI_CONFIG_KIND_MASK 0x3
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#define SPI_CONFIG_KIND(V) ((V & SPI_CONFIG_KIND_MASK) << SPI_CONFIG_KIND_OFFS)
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#define SPI_CONFIG_MODE_OFFS 4
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#define SPI_CONFIG_MODE_MASK 0x7
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#define SPI_CONFIG_MODE(V) ((V & SPI_CONFIG_MODE_MASK) << SPI_CONFIG_MODE_OFFS)
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#define SPI_INTR_TX_IE_OFFS 0
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#define SPI_INTR_TX_IE_MASK 0x1
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#define SPI_INTR_TX_IE(V) ((V & SPI_INTR_TX_IE_MASK) << SPI_INTR_TX_IE_OFFS)
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#define SPI_INTR_RX_IE_OFFS 1
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#define SPI_INTR_RX_IE_MASK 0x1
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#define SPI_INTR_RX_IE(V) ((V & SPI_INTR_RX_IE_MASK) << SPI_INTR_RX_IE_OFFS)
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#define SPI_INTR_TX_IP_OFFS 8
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#define SPI_INTR_TX_IP_MASK 0x1
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#define SPI_INTR_TX_IP(V) ((V & SPI_INTR_TX_IP_MASK) << SPI_INTR_TX_IP_OFFS)
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#define SPI_INTR_RX_IP_OFFS 9
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#define SPI_INTR_RX_IP_MASK 0x1
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#define SPI_INTR_RX_IP(V) ((V & SPI_INTR_RX_IP_MASK) << SPI_INTR_RX_IP_OFFS)
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#define SPI_INTR_TX_ACTIVE_OFFS 16
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#define SPI_INTR_TX_ACTIVE_MASK 0x1
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#define SPI_INTR_TX_ACTIVE(V) ((V & SPI_INTR_TX_ACTIVE_MASK) << SPI_INTR_TX_ACTIVE_OFFS)
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#define SPI_SCLK_CONFIG_OFFS 0
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#define SPI_SCLK_CONFIG_MASK 0xfff
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#define SPI_SCLK_CONFIG(V) ((V & SPI_SCLK_CONFIG_MASK) << SPI_SCLK_CONFIG_OFFS)
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#define SPI_SSGEN_SETUP_OFFS 0
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#define SPI_SSGEN_SETUP_MASK 0xfff
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#define SPI_SSGEN_SETUP(V) ((V & SPI_SSGEN_SETUP_MASK) << SPI_SSGEN_SETUP_OFFS)
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#define SPI_SSGEN_HOLD_OFFS 0
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#define SPI_SSGEN_HOLD_MASK 0xfff
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#define SPI_SSGEN_HOLD(V) ((V & SPI_SSGEN_HOLD_MASK) << SPI_SSGEN_HOLD_OFFS)
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#define SPI_SSGEN_DISABLE_OFFS 0
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#define SPI_SSGEN_DISABLE_MASK 0xfff
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#define SPI_SSGEN_DISABLE(V) ((V & SPI_SSGEN_DISABLE_MASK) << SPI_SSGEN_DISABLE_OFFS)
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#define SPI_SSGEN_ACTIVE_HIGH_OFFS 0
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#define SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
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#define SPI_SSGEN_ACTIVE_HIGH(V) ((V & SPI_SSGEN_ACTIVE_HIGH_MASK) << SPI_SSGEN_ACTIVE_HIGH_OFFS)
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#define SPI_XIP_ENABLE_OFFS 0
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#define SPI_XIP_ENABLE_MASK 0x1
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#define SPI_XIP_ENABLE(V) ((V & SPI_XIP_ENABLE_MASK) << SPI_XIP_ENABLE_OFFS)
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#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
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#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
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#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
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#define SPI_XIP_CONFIG_ENABLE_OFFS 8
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#define SPI_XIP_CONFIG_ENABLE_MASK 0x1
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#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
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#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
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#define SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
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#define SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
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#define SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
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#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
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#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
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#define SPI_XIP_MODE_INSTRUCTION_OFFS 0
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#define SPI_XIP_MODE_INSTRUCTION_MASK 0x7
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#define SPI_XIP_MODE_INSTRUCTION(V) ((V & SPI_XIP_MODE_INSTRUCTION_MASK) << SPI_XIP_MODE_INSTRUCTION_OFFS)
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#define SPI_XIP_MODE_ADDRESS_OFFS 8
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#define SPI_XIP_MODE_ADDRESS_MASK 0x7
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#define SPI_XIP_MODE_ADDRESS(V) ((V & SPI_XIP_MODE_ADDRESS_MASK) << SPI_XIP_MODE_ADDRESS_OFFS)
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#define SPI_XIP_MODE_DUMMY_OFFS 16
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#define SPI_XIP_MODE_DUMMY_MASK 0x7
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#define SPI_XIP_MODE_DUMMY(V) ((V & SPI_XIP_MODE_DUMMY_MASK) << SPI_XIP_MODE_DUMMY_OFFS)
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#define SPI_XIP_MODE_PAYLOAD_OFFS 24
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#define SPI_XIP_MODE_PAYLOAD_MASK 0x7
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#define SPI_XIP_MODE_PAYLOAD(V) ((V & SPI_XIP_MODE_PAYLOAD_MASK) << SPI_XIP_MODE_PAYLOAD_OFFS)
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#define SPI_XIP_WRITE_OFFS 0
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#define SPI_XIP_WRITE_MASK 0xff
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#define SPI_XIP_WRITE(V) ((V & SPI_XIP_WRITE_MASK) << SPI_XIP_WRITE_OFFS)
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#define SPI_XIP_READ_WRITE_OFFS 0
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#define SPI_XIP_READ_WRITE_MASK 0xff
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#define SPI_XIP_READ_WRITE(V) ((V & SPI_XIP_READ_WRITE_MASK) << SPI_XIP_READ_WRITE_OFFS)
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#define SPI_XIP_READ_OFFS 0
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#define SPI_XIP_READ_MASK 0xff
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#define SPI_XIP_READ(V) ((V & SPI_XIP_READ_MASK) << SPI_XIP_READ_OFFS)
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//SPI_DATA
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inline uint32_t get_spi_data(volatile apb3spixdrmasterctrl_t* reg){
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return reg->DATA;
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}
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inline void set_spi_data(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
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reg->DATA = value;
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}
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inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->DATA >> 8) & 0x1;
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}
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inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
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}
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inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->DATA >> 9) & 0x1;
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}
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inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
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}
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inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->DATA >> 11) & 0x1;
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}
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inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
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}
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inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->DATA >> 31) & 0x1;
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}
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//SPI_STATUS
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inline uint32_t get_spi_status(volatile apb3spixdrmasterctrl_t* reg){
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return reg->STATUS;
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}
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inline void set_spi_status(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
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reg->STATUS = value;
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}
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inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->STATUS >> 0) & 0x3f;
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}
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inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->STATUS >> 16) & 0x3f;
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}
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//SPI_CONFIG
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inline uint32_t get_spi_config(volatile apb3spixdrmasterctrl_t* reg){
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return reg->CONFIG;
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}
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inline void set_spi_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
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reg->CONFIG = value;
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}
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inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->CONFIG >> 0) & 0x3;
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}
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inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->CONFIG >> 4) & 0x7;
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}
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inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
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}
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//SPI_INTR
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inline uint32_t get_spi_intr(volatile apb3spixdrmasterctrl_t* reg){
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return reg->INTR;
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}
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inline void set_spi_intr(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
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reg->INTR = value;
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}
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inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->INTR >> 0) & 0x1;
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}
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inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->INTR >> 1) & 0x1;
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}
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inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
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}
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inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->INTR >> 8) & 0x1;
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}
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inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->INTR >> 9) & 0x1;
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}
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inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->INTR >> 16) & 0x1;
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}
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//SPI_SCLK_CONFIG
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inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->SCLK_CONFIG >> 0) & 0xfff;
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}
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inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
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reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
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}
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//SPI_SSGEN_SETUP
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inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->SSGEN_SETUP >> 0) & 0xfff;
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}
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inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
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reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
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}
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//SPI_SSGEN_HOLD
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inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->SSGEN_HOLD >> 0) & 0xfff;
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}
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inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
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reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
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}
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//SPI_SSGEN_DISABLE
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inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->SSGEN_DISABLE >> 0) & 0xfff;
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}
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inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
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reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
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}
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//SPI_SSGEN_ACTIVE_HIGH
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inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
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}
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inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
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}
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//SPI_XIP_ENABLE
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inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_ENABLE >> 0) & 0x1;
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}
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inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
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}
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//SPI_XIP_CONFIG
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inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg){
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return reg->XIP_CONFIG;
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}
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inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
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reg->XIP_CONFIG = value;
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}
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inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_CONFIG >> 0) & 0xff;
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}
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inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_CONFIG >> 8) & 0x1;
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}
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inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
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}
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inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_CONFIG >> 16) & 0xff;
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}
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inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
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}
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inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_CONFIG >> 24) & 0xf;
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}
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inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
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}
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//SPI_XIP_MODE
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inline uint32_t get_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg){
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return reg->XIP_MODE;
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}
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inline void set_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
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reg->XIP_MODE = value;
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}
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inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_MODE >> 0) & 0x7;
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}
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inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_MODE >> 8) & 0x7;
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}
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inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
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}
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inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_MODE >> 16) & 0x7;
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}
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inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
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}
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inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_MODE >> 24) & 0x7;
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}
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inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
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}
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//SPI_XIP_WRITE
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inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
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}
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//SPI_XIP_READ_WRITE
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inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
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reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
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}
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//SPI_XIP_READ
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inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t* reg){
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return (reg->XIP_READ >> 0) & 0xff;
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}
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#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */ |