Firmware/MNRS-BM-BSP
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fixes inline declarations of functions

Browse Source
This commit is contained in:
Eyck Jentzsch 2025-04-13 18:13:31 +02:00
parent c73bc9e144
commit e1ea5a98d6
14 changed files with 1107 additions and 1733 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
include/ehrenberg/devices/gen/aclint.h
View File

@ -43,48 +43,32 @@ typedef struct {
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS) #define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0 // ACLINT_MSIP0
inline uint32_t get_aclint_msip0(volatile aclint_t* reg){ static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; }
return reg->MSIP0; static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; }
} static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; }
inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){ static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); }
reg->MSIP0 = value;
}
inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
return (reg->MSIP0 >> 0) & 0x1;
}
inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
}
// ACLINT_MTIMECMP0LO // ACLINT_MTIMECMP0LO
inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){ static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; }
return (reg->MTIMECMP0LO >> 0) & 0xffffffff; static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) {
}
inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0); reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIMECMP0HI // ACLINT_MTIMECMP0HI
inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){ static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; }
return (reg->MTIMECMP0HI >> 0) & 0xffffffff; static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) {
}
inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0); reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIME_LO // ACLINT_MTIME_LO
inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){ static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; }
return (reg->MTIME_LO >> 0) & 0xffffffff; static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) {
}
inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0); reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIME_HI // ACLINT_MTIME_HI
inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){ static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; }
return (reg->MTIME_HI >> 0) & 0xffffffff; static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) {
}
inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0); reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
} }

280
include/ehrenberg/devices/gen/apb3spi.h
View File

@ -158,273 +158,153 @@ typedef struct {
#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS) #define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
// APB3SPI_DATA // APB3SPI_DATA
inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; }
return reg->DATA; static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; }
} static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); }
inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){ static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; }
reg->DATA = value; static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); }
} static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; }
inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){ static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); }
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; }
} static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) {
inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
return (reg->DATA >> 8) & 0x1;
}
inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
return (reg->DATA >> 9) & 0x1;
}
inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg){
return (reg->DATA >> 11) & 0x1;
}
inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11); reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
} }
inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; }
return (reg->DATA >> 31) & 0x1;
}
// APB3SPI_STATUS // APB3SPI_STATUS
inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; }
return reg->STATUS; static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; }
} static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; }
inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
return (reg->STATUS >> 0) & 0x3f;
}
inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
return (reg->STATUS >> 16) & 0x3f;
}
// APB3SPI_CONFIG // APB3SPI_CONFIG
inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; }
return reg->CONFIG; static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; }
} static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = value;
}
inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0); reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
return (reg->CONFIG >> 4) & 0x3; static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4); reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
} }
// APB3SPI_INTR // APB3SPI_INTR
inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; }
return reg->INTR; static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; }
} static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; }
inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); }
reg->INTR = value; static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; }
} static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); }
inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; }
return (reg->INTR >> 0) & 0x1; static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); }
} static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; }
inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){ static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); }
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; }
}
inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 1) & 0x1;
}
inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 8) & 0x1;
}
inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 9) & 0x1;
}
inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
return (reg->INTR >> 16) & 0x1;
}
// APB3SPI_SCLK_CONFIG // APB3SPI_SCLK_CONFIG
inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; }
return reg->SCLK_CONFIG; static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; }
} static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; }
inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) {
reg->SCLK_CONFIG = value;
}
inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0); reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_SSGEN_SETUP // APB3SPI_SSGEN_SETUP
inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; }
return reg->SSGEN_SETUP; static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; }
} static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; }
inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_SETUP = value;
}
inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0); reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_SSGEN_HOLD // APB3SPI_SSGEN_HOLD
inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; }
return reg->SSGEN_HOLD; static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; }
} static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; }
inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_HOLD = value;
}
inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0); reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_SSGEN_DISABLE // APB3SPI_SSGEN_DISABLE
inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; }
return reg->SSGEN_DISABLE; static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; }
} static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; }
inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) {
reg->SSGEN_DISABLE = value;
}
inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0); reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_SSGEN_ACTIVE_HIGH // APB3SPI_SSGEN_ACTIVE_HIGH
inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; }
return reg->SSGEN_ACTIVE_HIGH; static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; }
} static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) {
inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_ACTIVE_HIGH = value;
}
inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1; return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
} }
inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){ static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) {
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
} }
// APB3SPI_XIP_ENABLE // APB3SPI_XIP_ENABLE
inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; }
return reg->XIP_ENABLE; static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; }
} static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; }
inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_ENABLE = value;
}
inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
return (reg->XIP_ENABLE >> 0) & 0x1;
}
inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0); reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
} }
// APB3SPI_XIP_CONFIG // APB3SPI_XIP_CONFIG
inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; }
return reg->XIP_CONFIG; static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; }
} static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; }
inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = value;
}
inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 0) & 0xff;
}
inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0); reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
} }
inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; }
return (reg->XIP_CONFIG >> 8) & 0x1; static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8); reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
} }
inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; }
return (reg->XIP_CONFIG >> 16) & 0xff; static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16); reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
} }
inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; }
return (reg->XIP_CONFIG >> 24) & 0xf; static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24); reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
} }
// APB3SPI_XIP_MODE // APB3SPI_XIP_MODE
inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; }
return reg->XIP_MODE; static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; }
} static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; }
inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = value;
}
inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 0) & 0x3;
}
inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0); reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; }
return (reg->XIP_MODE >> 8) & 0x3; static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8); reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
} }
inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; }
return (reg->XIP_MODE >> 16) & 0x3; static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16); reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
} }
inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; }
return (reg->XIP_MODE >> 24) & 0x3; static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24); reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
} }
// APB3SPI_XIP_WRITE // APB3SPI_XIP_WRITE
inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; }
reg->XIP_WRITE = value; static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0); reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
} }
// APB3SPI_XIP_READ_WRITE // APB3SPI_XIP_READ_WRITE
inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){ static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; }
reg->XIP_READ_WRITE = value; static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) {
}
inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0); reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
} }
// APB3SPI_XIP_READ // APB3SPI_XIP_READ
inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){ static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; }
return reg->XIP_READ; static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; }
}
inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
return (reg->XIP_READ >> 0) & 0xff;
}
#endif /* _BSP_APB3SPI_H */ #endif /* _BSP_APB3SPI_H */

208
include/ehrenberg/devices/gen/camera.h
View File

@ -125,212 +125,132 @@ typedef struct {
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS) #define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
// CAMERA_PIXEL // CAMERA_PIXEL
inline uint32_t get_camera_pixel(volatile camera_t* reg){ static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; }
return (reg->PIXEL >> 0) & 0xffffffff; static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) {
}
inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0); reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
} }
// CAMERA_CONFIG // CAMERA_CONFIG
inline uint32_t get_camera_config(volatile camera_t* reg){ static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; }
return reg->CONFIG; static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; }
} static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
inline void set_camera_config(volatile camera_t* reg, uint32_t value){ static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = value;
}
inline uint32_t get_camera_config_output_curr(volatile camera_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0); reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg){ static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; }
return (reg->CONFIG >> 2) & 0x3; static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2); reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
} }
inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg){ static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; }
return (reg->CONFIG >> 4) & 0x3; static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4); reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
} }
inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg){ static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; }
return (reg->CONFIG >> 6) & 0x3; static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6); reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
} }
inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg){ static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; }
return (reg->CONFIG >> 8) & 0xff; static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8); reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
} }
inline uint32_t get_camera_config_high_speed(volatile camera_t* reg){ static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; }
return (reg->CONFIG >> 16) & 0x1; static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16); reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
} }
inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg){ static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; }
return (reg->CONFIG >> 17) & 0x1; static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17); reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
} }
inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg){ static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; }
return (reg->CONFIG >> 18) & 0x3; static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18); reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
} }
inline uint32_t get_camera_config_vref(volatile camera_t* reg){ static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; }
return (reg->CONFIG >> 20) & 0x3; static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20); reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
} }
inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg){ static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; }
return (reg->CONFIG >> 22) & 0x3; static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22); reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
} }
inline uint32_t get_camera_config_output_mode(volatile camera_t* reg){ static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; }
return (reg->CONFIG >> 24) & 0x1; static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24); reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
} }
inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg){ static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; }
return (reg->CONFIG >> 25) & 0x1; static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25); reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
} }
inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg){ static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; }
return (reg->CONFIG >> 26) & 0x1; static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26); reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
} }
inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg){ static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; }
return (reg->CONFIG >> 27) & 0x1f; static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27); reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
} }
// CAMERA_CONFIG2 // CAMERA_CONFIG2
inline uint32_t get_camera_config2(volatile camera_t* reg){ static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; }
return reg->CONFIG2; static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; }
} static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; }
inline void set_camera_config2(volatile camera_t* reg, uint32_t value){ static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = value;
}
inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg){
return (reg->CONFIG2 >> 0) & 0x1;
}
inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value){
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0); reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg){ static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; }
return (reg->CONFIG2 >> 1) & 0x1; static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value){
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1); reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
} }
// CAMERA_DATA_SIZE // CAMERA_DATA_SIZE
inline uint32_t get_camera_data_size(volatile camera_t* reg){ static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; }
return reg->DATA_SIZE; static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; }
} static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; }
inline void set_camera_data_size(volatile camera_t* reg, uint32_t value){ static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) {
reg->DATA_SIZE = value;
}
inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg){
return (reg->DATA_SIZE >> 0) & 0x3;
}
inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value){
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0); reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
} }
// CAMERA_START // CAMERA_START
inline uint32_t get_camera_start(volatile camera_t* reg){ static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; }
return reg->START; static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; }
} static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; }
inline void set_camera_start(volatile camera_t* reg, uint32_t value){ static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) {
reg->START = value;
}
inline uint32_t get_camera_start_start(volatile camera_t* reg){
return (reg->START >> 0) & 0x1;
}
inline void set_camera_start_start(volatile camera_t* reg, uint8_t value){
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0); reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
} }
// CAMERA_STATUS // CAMERA_STATUS
inline uint32_t get_camera_status(volatile camera_t* reg){ static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; }
return reg->STATUS; static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; }
}
inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
// CAMERA_CAMERA_CLOCK_CTRL // CAMERA_CAMERA_CLOCK_CTRL
inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){ static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; }
return reg->CAMERA_CLOCK_CTRL; static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; }
} static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; }
inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){ static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) {
reg->CAMERA_CLOCK_CTRL = value;
}
inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
}
inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value){
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0); reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
} }
// CAMERA_IE // CAMERA_IE
inline uint32_t get_camera_ie(volatile camera_t* reg){ static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; }
return reg->IE; static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; }
} static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; }
inline void set_camera_ie(volatile camera_t* reg, uint32_t value){ static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) {
reg->IE = value;
}
inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){ static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; }
return (reg->IE >> 1) & 0x1; static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
} }
// CAMERA_IP // CAMERA_IP
inline uint32_t get_camera_ip(volatile camera_t* reg){ static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; }
return reg->IP; static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; }
} static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; }
inline void set_camera_ip(volatile camera_t* reg, uint32_t value){ static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = value;
}
inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0); reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){ static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; }
return (reg->IP >> 1) & 0x1; static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) {
}
inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1); reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
} }

280
include/ehrenberg/devices/gen/dma.h
View File

@ -168,286 +168,174 @@ typedef struct {
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS) #define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
// DMA_CONTROL // DMA_CONTROL
inline uint32_t get_dma_control(volatile dma_t* reg){ static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; }
return reg->CONTROL; static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; }
} static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; }
inline void set_dma_control(volatile dma_t* reg, uint32_t value){ static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = value;
}
inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0); reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){ static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; }
return (reg->CONTROL >> 1) & 0x1; static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) {
}
inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1); reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
} }
// DMA_STATUS // DMA_STATUS
inline uint32_t get_dma_status(volatile dma_t* reg){ static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; }
return reg->STATUS; static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; }
} static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; }
inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
// DMA_IE // DMA_IE
inline uint32_t get_dma_ie(volatile dma_t* reg){ static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; }
return reg->IE; static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; }
} static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; }
inline void set_dma_ie(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = value;
}
inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){ static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; }
return (reg->IE >> 1) & 0x1; static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
}
inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
} }
inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){ static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; }
return (reg->IE >> 2) & 0x1; static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
}
inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2); reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
} }
inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){ static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; }
return (reg->IE >> 3) & 0x1; static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
}
inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3); reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
} }
// DMA_IP // DMA_IP
inline uint32_t get_dma_ip(volatile dma_t* reg){ static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; }
return reg->IP; static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; }
} static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; }
inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){ static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; }
return (reg->IP >> 0) & 0x1; static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; }
}
inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 1) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 2) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 3) & 0x1;
}
// DMA_CH0_EVENT // DMA_CH0_EVENT
inline uint32_t get_dma_ch0_event(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; }
return reg->CH0_EVENT; static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; }
} static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; }
inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = value;
}
inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
return (reg->CH0_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0); reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; }
return (reg->CH0_EVENT >> 31) & 0x1; static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) {
}
inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31); reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
} }
// DMA_CH0_TRANSFER // DMA_CH0_TRANSFER
inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; }
return reg->CH0_TRANSFER; static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; }
} static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; }
inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH0_TRANSFER = value;
}
inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0); reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; }
return (reg->CH0_TRANSFER >> 2) & 0x3ff; static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
}
inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2); reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
} }
inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; }
return (reg->CH0_TRANSFER >> 12) & 0xfffff; static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12); reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH0_SRC_START_ADDR // DMA_CH0_SRC_START_ADDR
inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; }
return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
// DMA_CH0_SRC_ADDR_INC // DMA_CH0_SRC_ADDR_INC
inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; }
return reg->CH0_SRC_ADDR_INC; static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; }
} static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; }
inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0); reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; }
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH0_DST_START_ADDR // DMA_CH0_DST_START_ADDR
inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; }
return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
// DMA_CH0_DST_ADDR_INC // DMA_CH0_DST_ADDR_INC
inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; }
return reg->CH0_DST_ADDR_INC; static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; }
} static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; }
inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0); reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){ static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; }
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH1_EVENT // DMA_CH1_EVENT
inline uint32_t get_dma_ch1_event(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; }
return reg->CH1_EVENT; static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; }
} static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; }
inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = value;
}
inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
return (reg->CH1_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0); reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; }
return (reg->CH1_EVENT >> 31) & 0x1; static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) {
}
inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31); reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
} }
// DMA_CH1_TRANSFER // DMA_CH1_TRANSFER
inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; }
return reg->CH1_TRANSFER; static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; }
} static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; }
inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH1_TRANSFER = value;
}
inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0); reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; }
return (reg->CH1_TRANSFER >> 2) & 0x3ff; static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) {
}
inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2); reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
} }
inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; }
return (reg->CH1_TRANSFER >> 12) & 0xfffff; static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12); reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH1_SRC_START_ADDR // DMA_CH1_SRC_START_ADDR
inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; }
return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
// DMA_CH1_SRC_ADDR_INC // DMA_CH1_SRC_ADDR_INC
inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; }
return reg->CH1_SRC_ADDR_INC; static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; }
} static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; }
inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_SRC_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0); reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; }
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH1_DST_START_ADDR // DMA_CH1_DST_START_ADDR
inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; }
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
// DMA_CH1_DST_ADDR_INC // DMA_CH1_DST_ADDR_INC
inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; }
return reg->CH1_DST_ADDR_INC; static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; }
} static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; }
inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){ static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0); reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){ static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; }
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) {
}
inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }

290
include/ehrenberg/devices/gen/gpio.h
View File

@ -198,304 +198,196 @@ typedef struct {
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS) #define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
// GPIO_VALUE // GPIO_VALUE
inline uint32_t get_gpio_value(volatile gpio_t* reg){ static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; }
return (reg->VALUE >> 0) & 0xffffffff;
}
// GPIO_WRITE // GPIO_WRITE
inline uint32_t get_gpio_write(volatile gpio_t* reg){ static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; }
return (reg->WRITE >> 0) & 0xffffffff; static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); }
}
inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_WRITEENABLE // GPIO_WRITEENABLE
inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){ static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; }
return (reg->WRITEENABLE >> 0) & 0xffffffff; static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) {
}
inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0); reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_PULLUP // GPIO_PULLUP
inline uint32_t get_gpio_pullup(volatile gpio_t* reg){ static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; }
return (reg->PULLUP >> 0) & 0xffffffff; static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) {
}
inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value){
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0); reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_PULDOWN // GPIO_PULDOWN
inline uint32_t get_gpio_puldown(volatile gpio_t* reg){ static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; }
return (reg->PULDOWN >> 0) & 0xffffffff; static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) {
}
inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value){
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0); reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_DRIVESTRENGTH_0 // GPIO_DRIVESTRENGTH_0
inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; }
return reg->DRIVESTRENGTH_0; static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; }
} static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; }
inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value){ static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = value;
}
inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; }
return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
} }
inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; }
return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
} }
inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; }
return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
} }
inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; }
return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
} }
inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; }
return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
} }
inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; }
return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
} }
inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; }
return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28); reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_DRIVESTRENGTH_1 // GPIO_DRIVESTRENGTH_1
inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; }
return reg->DRIVESTRENGTH_1; static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; }
} static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; }
inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value){ static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = value;
}
inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; }
return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
} }
inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; }
return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
} }
inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; }
return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
} }
inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; }
return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
} }
inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; }
return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
} }
inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; }
return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
} }
inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; }
return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28); reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_DRIVESTRENGTH_2 // GPIO_DRIVESTRENGTH_2
inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; }
return reg->DRIVESTRENGTH_2; static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; }
} static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; }
inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value){ static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = value;
}
inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; }
return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
} }
inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; }
return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
} }
inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; }
return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
} }
inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; }
return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
} }
inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; }
return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
} }
inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; }
return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
} }
inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; }
return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_DRIVESTRENGTH_3 // GPIO_DRIVESTRENGTH_3
inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; }
return reg->DRIVESTRENGTH_3; static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; }
} static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; }
inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value){ static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = value;
}
inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; }
return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
} }
inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; }
return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
} }
inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; }
return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
} }
inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; }
return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
} }
inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; }
return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
} }
inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; }
return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
} }
inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg){ static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; }
return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) {
}
inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28); reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_IE // GPIO_IE
inline uint32_t get_gpio_ie(volatile gpio_t* reg){ static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; }
return (reg->IE >> 0) & 0xffffffff; static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); }
}
inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IP // GPIO_IP
inline uint32_t get_gpio_ip(volatile gpio_t* reg){ static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; }
return (reg->IP >> 0) & 0xffffffff; static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); }
}
inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
}
// GPIO_IRQ_TRIGGER // GPIO_IRQ_TRIGGER
inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){ static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; }
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) {
}
inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0); reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_IRQ_TYPE // GPIO_IRQ_TYPE
inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){ static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; }
return (reg->IRQ_TYPE >> 0) & 0xffffffff; static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) {
}
inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0); reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_BOOT_SEL // GPIO_BOOT_SEL
inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){ static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; }
return reg->BOOT_SEL; static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; }
}
inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
return (reg->BOOT_SEL >> 0) & 0x7;
}
#endif /* _BSP_GPIO_H */ #endif /* _BSP_GPIO_H */

164
include/ehrenberg/devices/gen/i2s.h
View File

@ -109,162 +109,92 @@ typedef struct {
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS) #define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
// I2S_LEFT_CH // I2S_LEFT_CH
inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){ static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; }
return (reg->LEFT_CH >> 0) & 0xffffffff;
}
// I2S_RIGHT_CH // I2S_RIGHT_CH
inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){ static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; }
return (reg->RIGHT_CH >> 0) & 0xffffffff;
}
// I2S_CONTROL // I2S_CONTROL
inline uint32_t get_i2s_control(volatile i2s_t* reg){ static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; }
return reg->CONTROL; static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; }
} static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; }
inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){ static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); }
reg->CONTROL = value; static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; }
} static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) {
inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
return (reg->CONTROL >> 0) & 0x3;
}
inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
return (reg->CONTROL >> 2) & 0x1;
}
inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2); reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
} }
inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){ static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; }
return (reg->CONTROL >> 3) & 0x1; static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) {
}
inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3); reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
} }
inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){ static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; }
return (reg->CONTROL >> 4) & 0x1; static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) {
}
inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4); reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
} }
inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){ static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; }
return (reg->CONTROL >> 5) & 0x3; static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) {
}
inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5); reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
} }
inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){ static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; }
return (reg->CONTROL >> 7) & 0x7; static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) {
}
inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7); reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
} }
// I2S_STATUS // I2S_STATUS
inline uint32_t get_i2s_status(volatile i2s_t* reg){ static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; }
return reg->STATUS; static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; }
} static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; }
inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){ static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; }
reg->STATUS = value; static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; }
} static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; }
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){ static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; }
return (reg->STATUS >> 0) & 0x1; static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) {
}
inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
return (reg->STATUS >> 2) & 0x1;
}
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
return (reg->STATUS >> 3) & 0x1;
}
inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg){
return (reg->STATUS >> 4) & 0x1;
}
inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value){
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4); reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
} }
inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg){ static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; }
return (reg->STATUS >> 5) & 0x1; static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) {
}
inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value){
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5); reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
} }
// I2S_I2S_CLOCK_CTRL // I2S_I2S_CLOCK_CTRL
inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){ static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; }
return reg->I2S_CLOCK_CTRL; static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; }
} static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; }
inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){ static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) {
reg->I2S_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0); reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
} }
// I2S_PDM_CLOCK_CTRL // I2S_PDM_CLOCK_CTRL
inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){ static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; }
return reg->PDM_CLOCK_CTRL; static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; }
} static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; }
inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){ static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) {
reg->PDM_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
}
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value){
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0); reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
} }
// I2S_PDM_FILTER_CTRL // I2S_PDM_FILTER_CTRL
inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg){ static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; }
return reg->PDM_FILTER_CTRL; static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; }
} static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; }
inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value){ static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) {
reg->PDM_FILTER_CTRL = value;
}
inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg){
return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff;
}
inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value){
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0); reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
} }
// I2S_IE // I2S_IE
inline uint32_t get_i2s_ie(volatile i2s_t* reg){ static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; }
return reg->IE; static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; }
} static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; }
inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){ static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = value;
}
inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0); reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){ static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; }
return (reg->IE >> 1) & 0x1; static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) {
}
inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
} }
// I2S_IP // I2S_IP
inline uint32_t get_i2s_ip(volatile i2s_t* reg){ static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; }
return reg->IP; static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; }
} static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; }
inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 1) & 0x1;
}
#endif /* _BSP_I2S_H */ #endif /* _BSP_I2S_H */

112
include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
View File

@ -31,176 +31,200 @@ typedef struct {
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK) \
<< MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_MASK) \
<< MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_ACK_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS 1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK_PENDING_RESPONSE_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7(V) \
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7_OFFS)
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_SEND = value; reg->REG_SEND = value;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0); reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_HEADER; return reg->REG_HEADER;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_HEADER = value; reg->REG_HEADER = value;
} }
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 0) & 0xf; return (reg->REG_HEADER >> 0) & 0xf;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg,
uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0); reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
} }
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 4) & 0xf; return (reg->REG_HEADER >> 4) & 0xf;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg,
uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4); reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
} }
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(
volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 8) & 0x7; return (reg->REG_HEADER >> 8) & 0x7;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg,
uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8); reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
} }
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_HEADER >> 11) & 0x3; return (reg->REG_HEADER >> 11) & 0x3;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg,
uint8_t value) {
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11); reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_ACK; return reg->REG_ACK;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_ACK = value; reg->REG_ACK = value;
} }
inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) {
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0); reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_ACK >> 1) & 0x1; return (reg->REG_ACK >> 1) & 0x1;
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return reg->REG_RECV_ID; return reg->REG_RECV_ID;
} }
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_RECV_ID >> 0) & 0xf; return (reg->REG_RECV_ID >> 0) & 0xf;
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg){ static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) {
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7 // MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){ static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
} }

75
include/ehrenberg/devices/gen/msgif.h
View File

@ -43,7 +43,8 @@ typedef struct {
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8 #define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7 #define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS) #define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) \
((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11 #define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 11
#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3 #define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
@ -94,103 +95,81 @@ typedef struct {
#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS) #define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
// MSGIF_REG_SEND // MSGIF_REG_SEND
inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value) { reg->REG_SEND = value; }
reg->REG_SEND = value; static inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value) {
}
inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value){
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0); reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
} }
// MSGIF_REG_HEADER // MSGIF_REG_HEADER
inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){ static inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg) { return reg->REG_HEADER; }
return reg->REG_HEADER; static inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value) { reg->REG_HEADER = value; }
} static inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg) { return (reg->REG_HEADER >> 0) & 0xf; }
inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value) {
reg->REG_HEADER = value;
}
inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
return (reg->REG_HEADER >> 0) & 0xf;
}
inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0); reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
} }
inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){ static inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg) { return (reg->REG_HEADER >> 4) & 0xf; }
return (reg->REG_HEADER >> 4) & 0xf; static inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value) {
}
inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4); reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
} }
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){ static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg) { return (reg->REG_HEADER >> 8) & 0x7; }
return (reg->REG_HEADER >> 8) & 0x7; static inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value) {
}
inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8); reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
} }
inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){ static inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg) { return (reg->REG_HEADER >> 11) & 0x3; }
return (reg->REG_HEADER >> 11) & 0x3; static inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value) {
}
inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11); reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
} }
// MSGIF_REG_ACK // MSGIF_REG_ACK
inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value) { reg->REG_ACK = value; }
reg->REG_ACK = value; static inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value) {
}
inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value){
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0); reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
} }
// MSGIF_REG_RECV_ID // MSGIF_REG_RECV_ID
inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg){ static inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg) { return reg->REG_RECV_ID; }
return reg->REG_RECV_ID; static inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg) { return (reg->REG_RECV_ID >> 0) & 0xf; }
}
inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg){
return (reg->REG_RECV_ID >> 0) & 0xf;
}
// MSGIF_REG_RECV_PAYLOAD // MSGIF_REG_RECV_PAYLOAD
inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg){ static inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg) { return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; }
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
}
// MSGIF_REG_PAYLOAD_0 // MSGIF_REG_PAYLOAD_0
inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MSGIF_REG_PAYLOAD_1 // MSGIF_REG_PAYLOAD_1
inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MSGIF_REG_PAYLOAD_2 // MSGIF_REG_PAYLOAD_2
inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MSGIF_REG_PAYLOAD_3 // MSGIF_REG_PAYLOAD_3
inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MSGIF_REG_PAYLOAD_4 // MSGIF_REG_PAYLOAD_4
inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MSGIF_REG_PAYLOAD_5 // MSGIF_REG_PAYLOAD_5
inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MSGIF_REG_PAYLOAD_6 // MSGIF_REG_PAYLOAD_6
inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
} }
// MSGIF_REG_PAYLOAD_7 // MSGIF_REG_PAYLOAD_7
inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value){ static inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value) {
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
} }

70
include/ehrenberg/devices/gen/sysctrl.h
View File

@ -51,71 +51,43 @@ typedef struct {
#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS) #define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
// SYSCTRL_SYSCTRL // SYSCTRL_SYSCTRL
inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg) { return reg->SYSCTRL; }
return reg->SYSCTRL; static inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value) { reg->SYSCTRL = value; }
} static inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg) { return (reg->SYSCTRL >> 0) & 0x3; }
inline void set_sysctrl_sysctrl(volatile sysctrl_t* reg, uint32_t value){ static inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value) {
reg->SYSCTRL = value;
}
inline uint32_t get_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg){
return (reg->SYSCTRL >> 0) & 0x3;
}
inline void set_sysctrl_sysctrl_cc0_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0); reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 0)) | (value << 0);
} }
inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg) { return (reg->SYSCTRL >> 2) & 0x3; }
return (reg->SYSCTRL >> 2) & 0x3; static inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value) {
}
inline void set_sysctrl_sysctrl_cc1_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2); reg->SYSCTRL = (reg->SYSCTRL & ~(0x3U << 2)) | (value << 2);
} }
inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg) { return (reg->SYSCTRL >> 4) & 0x1; }
return (reg->SYSCTRL >> 4) & 0x1; static inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value) {
}
inline void set_sysctrl_sysctrl_mem_reset(volatile sysctrl_t* reg, uint8_t value){
reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4); reg->SYSCTRL = (reg->SYSCTRL & ~(0x1U << 4)) | (value << 4);
} }
// SYSCTRL_PLLCTRL // SYSCTRL_PLLCTRL
inline uint32_t get_sysctrl_pllctrl(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_pllctrl(volatile sysctrl_t* reg) { return reg->PLLCTRL; }
return reg->PLLCTRL; static inline void set_sysctrl_pllctrl(volatile sysctrl_t* reg, uint32_t value) { reg->PLLCTRL = value; }
} static inline uint32_t get_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 0) & 0x3f; }
inline void set_sysctrl_pllctrl(volatile sysctrl_t* reg, uint32_t value){ static inline void set_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg, uint8_t value) {
reg->PLLCTRL = value;
}
inline uint32_t get_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg){
return (reg->PLLCTRL >> 0) & 0x3f;
}
inline void set_sysctrl_pllctrl_p_counter(volatile sysctrl_t* reg, uint8_t value){
reg->PLLCTRL = (reg->PLLCTRL & ~(0x3fU << 0)) | (value << 0); reg->PLLCTRL = (reg->PLLCTRL & ~(0x3fU << 0)) | (value << 0);
} }
inline uint32_t get_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 6) & 0x3; }
return (reg->PLLCTRL >> 6) & 0x3; static inline void set_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg, uint8_t value) {
}
inline void set_sysctrl_pllctrl_s_counter(volatile sysctrl_t* reg, uint8_t value){
reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 6)) | (value << 6); reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 6)) | (value << 6);
} }
inline uint32_t get_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 8) & 0x3; }
return (reg->PLLCTRL >> 8) & 0x3; static inline void set_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg, uint8_t value) {
}
inline void set_sysctrl_pllctrl_clk_sel(volatile sysctrl_t* reg, uint8_t value){
reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 8)) | (value << 8); reg->PLLCTRL = (reg->PLLCTRL & ~(0x3U << 8)) | (value << 8);
} }
inline uint32_t get_sysctrl_pllctrl_locked(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_pllctrl_locked(volatile sysctrl_t* reg) { return (reg->PLLCTRL >> 31) & 0x1; }
return (reg->PLLCTRL >> 31) & 0x1;
}
// SYSCTRL_AXI_BACKUP // SYSCTRL_AXI_BACKUP
inline uint32_t get_sysctrl_axi_backup(volatile sysctrl_t* reg){ static inline uint32_t get_sysctrl_axi_backup(volatile sysctrl_t* reg) { return reg->AXI_BACKUP; }
return reg->AXI_BACKUP; static inline void set_sysctrl_axi_backup(volatile sysctrl_t* reg, uint32_t value) { reg->AXI_BACKUP = value; }
} static inline uint32_t get_sysctrl_axi_backup_page(volatile sysctrl_t* reg) { return (reg->AXI_BACKUP >> 0) & 0x1f; }
inline void set_sysctrl_axi_backup(volatile sysctrl_t* reg, uint32_t value){ static inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value) {
reg->AXI_BACKUP = value;
}
inline uint32_t get_sysctrl_axi_backup_page(volatile sysctrl_t* reg){
return (reg->AXI_BACKUP >> 0) & 0x1f;
}
inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0); reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
} }

74
include/ehrenberg/devices/gen/timercounter.h
View File

@ -59,83 +59,53 @@ typedef struct {
#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS) #define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
// TIMERCOUNTER_PRESCALER // TIMERCOUNTER_PRESCALER
inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; }
return reg->PRESCALER; static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; }
} static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; }
inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){ static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) {
reg->PRESCALER = value;
}
inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
return (reg->PRESCALER >> 0) & 0xffff;
}
inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0); reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
} }
// TIMERCOUNTER_T0_CTRL // TIMERCOUNTER_T0_CTRL
inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; }
return reg->T0_CTRL; static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; }
} static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; }
inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){ static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = value;
}
inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0); reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; }
return (reg->T0_CTRL >> 3) & 0x3; static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
}
inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3); reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
} }
// TIMERCOUNTER_T0_OVERFLOW // TIMERCOUNTER_T0_OVERFLOW
inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; }
return (reg->T0_OVERFLOW >> 0) & 0xffffffff; static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) {
}
inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
} }
// TIMERCOUNTER_T0_COUNTER // TIMERCOUNTER_T0_COUNTER
inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; }
return (reg->T0_COUNTER >> 0) & 0xffffffff;
}
// TIMERCOUNTER_T1_CTRL // TIMERCOUNTER_T1_CTRL
inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; }
return reg->T1_CTRL; static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; }
} static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; }
inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){ static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = value;
}
inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0); reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; }
return (reg->T1_CTRL >> 3) & 0x3; static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
}
inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3); reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
} }
// TIMERCOUNTER_T1_OVERFLOW // TIMERCOUNTER_T1_OVERFLOW
inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; }
return (reg->T1_OVERFLOW >> 0) & 0xffffffff; static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) {
}
inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
} }
// TIMERCOUNTER_T1_COUNTER // TIMERCOUNTER_T1_COUNTER
inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg){ static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; }
return (reg->T1_COUNTER >> 0) & 0xffffffff;
}
#endif /* _BSP_TIMERCOUNTER_H */ #endif /* _BSP_TIMERCOUNTER_H */

142
include/ehrenberg/devices/gen/uart.h
View File

@ -101,135 +101,75 @@ typedef struct {
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS) #define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG // UART_RX_TX_REG
inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){ static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
return reg->RX_TX_REG; static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
} static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){ static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = value;
}
inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
return (reg->RX_TX_REG >> 0) & 0xff;
}
inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0); reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
} }
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){ static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
return (reg->RX_TX_REG >> 14) & 0x1; static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
} static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
return (reg->RX_TX_REG >> 15) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
return (reg->RX_TX_REG >> 16) & 0x1;
}
// UART_INT_CTRL_REG // UART_INT_CTRL_REG
inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){ static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
return reg->INT_CTRL_REG; static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
} static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){ static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = value;
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 0) & 0x1;
}
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0); reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
} }
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){ static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
return (reg->INT_CTRL_REG >> 1) & 0x1; static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
}
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1); reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
} }
inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){ static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
return (reg->INT_CTRL_REG >> 2) & 0x1; static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
}
inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2); reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
} }
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){ static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
return (reg->INT_CTRL_REG >> 8) & 0x1; static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
} static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 10) & 0x1;
}
// UART_CLK_DIVIDER_REG // UART_CLK_DIVIDER_REG
inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){ static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
return reg->CLK_DIVIDER_REG; static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
} static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){ static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = value;
}
inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
}
inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0); reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
} }
// UART_FRAME_CONFIG_REG // UART_FRAME_CONFIG_REG
inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){ static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
return reg->FRAME_CONFIG_REG; static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
} static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){ static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = value;
}
inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0); reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
} }
inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){ static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
return (reg->FRAME_CONFIG_REG >> 3) & 0x3; static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
}
inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3); reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
} }
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){ static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
return (reg->FRAME_CONFIG_REG >> 5) & 0x1; static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
}
inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5); reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
} }
// UART_STATUS_REG // UART_STATUS_REG
inline uint32_t get_uart_status_reg(volatile uart_t* reg){ static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
return reg->STATUS_REG; static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
} static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){ static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
reg->STATUS_REG = value; static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
} static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){ static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
return (reg->STATUS_REG >> 0) & 0x1;
}
inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
return (reg->STATUS_REG >> 1) & 0x1;
}
inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
return (reg->STATUS_REG >> 8) & 0x1;
}
inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
return (reg->STATUS_REG >> 9) & 0x1;
}
inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9); reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
} }
inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){ static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
return (reg->STATUS_REG >> 10) & 0x1; static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
}
inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10); reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
} }
inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){ static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
return (reg->STATUS_REG >> 11) & 0x1; static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
}
inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11); reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
} }

3
include/ehrenberg/devices/gpio.h
View File

@ -2,9 +2,10 @@
#define _DEVICES_GPIO_H #define _DEVICES_GPIO_H
#include <stdint.h> #include <stdint.h>
#include "gen/gpio.h" #include "gen/gpio.h"
inline void gpio_init(volatile gpio_t* reg) { static inline void gpio_init(volatile gpio_t* reg) {
set_gpio_write(reg, 0); set_gpio_write(reg, 0);
set_gpio_writeEnable(reg, 0); set_gpio_writeEnable(reg, 0);
} }

3
include/ehrenberg/devices/interrupt.h
View File

@ -5,7 +5,6 @@
#define irq_t void* #define irq_t void*
inline void irq_init(volatile irq_t* reg){ static inline void irq_init(volatile irq_t* reg) {}
}
#endif /* _DEVICES_INTERRUPT_H */ #endif /* _DEVICES_INTERRUPT_H */

13
include/ehrenberg/devices/timer.h
View File

@ -2,18 +2,13 @@
#define _DEVICES_TIMER_H #define _DEVICES_TIMER_H
#include <stdint.h> #include <stdint.h>
#include "gen/timercounter.h" #include "gen/timercounter.h"
inline void prescaler_init(timercounter_t* reg, uint16_t value){ static inline void prescaler_init(timercounter_t *reg, uint16_t value) { set_timercounter_prescaler(reg, value); }
set_timercounter_prescaler(reg, value);
}
inline void timer_t0__init(timercounter_t *reg){ static inline void timer_t0__init(timercounter_t *reg) { set_timercounter_t0_overflow(reg, 0xffffffff); }
set_timercounter_t0_overflow(reg, 0xffffffff);
}
inline void timer_t1__init(timercounter_t *reg){ static inline void timer_t1__init(timercounter_t *reg) { set_timercounter_t1_overflow(reg, 0xffffffff); }
set_timercounter_t1_overflow(reg, 0xffffffff);
}
#endif /* _DEVICES_TIMER_H */ #endif /* _DEVICES_TIMER_H */