Firmware/MNRS-BM-BSP
9
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

fixes inline declarations of functions

Browse Source
This commit is contained in:
Eyck Jentzsch
2025-04-13 18:13:31 +02:00
parent c73bc9e144
commit e1ea5a98d6
14 changed files with 1107 additions and 1733 deletions
Download Patch File Download Diff File Expand all files Collapse all files

204
include/ehrenberg/devices/gen/uart.h
View File

@@ -1,11 +1,11 @@
/*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
*
* SPDX-License-Identifier: Apache-2.0
*
* Generated at 2024-08-02 08:46:07 UTC
* by peakrdl_mnrs version 1.2.7
*/
#ifndef _BSP_UART_H
#define _BSP_UART_H
@@ -13,12 +13,12 @@
#include <stdint.h>
typedef struct {
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
}uart_t;
volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG;
} uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff
@@ -100,137 +100,77 @@ typedef struct {
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
//UART_RX_TX_REG
inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
return reg->RX_TX_REG;
// UART_RX_TX_REG
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; }
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; }
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
}
inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
reg->RX_TX_REG = value;
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; }
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
// UART_INT_CTRL_REG
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
return (reg->RX_TX_REG >> 0) & 0xff;
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; }
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; }
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
return (reg->RX_TX_REG >> 14) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
return (reg->RX_TX_REG >> 15) & 0x1;
}
inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
return (reg->RX_TX_REG >> 16) & 0x1;
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
// UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
//UART_INT_CTRL_REG
inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
return reg->INT_CTRL_REG;
// UART_FRAME_CONFIG_REG
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; }
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; }
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
reg->INT_CTRL_REG = value;
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; }
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 0) & 0x1;
}
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 1) & 0x1;
}
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 2) & 0x1;
}
inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 8) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 10) & 0x1;
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; }
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
//UART_CLK_DIVIDER_REG
inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
return reg->CLK_DIVIDER_REG;
// UART_STATUS_REG
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; }
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; }
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = value;
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; }
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
}
inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
}
//UART_FRAME_CONFIG_REG
inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
return reg->FRAME_CONFIG_REG;
}
inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
reg->FRAME_CONFIG_REG = value;
}
inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
}
inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
}
inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
//UART_STATUS_REG
inline uint32_t get_uart_status_reg(volatile uart_t* reg){
return reg->STATUS_REG;
}
inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
reg->STATUS_REG = value;
}
inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
return (reg->STATUS_REG >> 0) & 0x1;
}
inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
return (reg->STATUS_REG >> 1) & 0x1;
}
inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
return (reg->STATUS_REG >> 8) & 0x1;
}
inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
return (reg->STATUS_REG >> 9) & 0x1;
}
inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 10) & 0x1;
}
inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
}
inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 11) & 0x1;
}
inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; }
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
}
#endif /* _BSP_UART_H */