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adapts to updated uart register layout

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This commit is contained in:
Florian Kriebel
2025-07-01 12:07:11 +02:00
parent b375ff4a72
commit d642f80972
14 changed files with 1518 additions and 955 deletions
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92
include/ehrenberg/devices/gen/aclint.h
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@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-08-02 08:46:07 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.7 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_ACLINT_H #ifndef _BSP_ACLINT_H
#define _BSP_ACLINT_H #define _BSP_ACLINT_H
@ -13,14 +13,14 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t MSIP0; volatile uint32_t MSIP0;
uint8_t fill0[16380]; uint8_t fill0[16380];
volatile uint32_t MTIMECMP0LO; volatile uint32_t MTIMECMP0LO;
volatile uint32_t MTIMECMP0HI; volatile uint32_t MTIMECMP0HI;
uint8_t fill1[32752]; uint8_t fill1[32752];
volatile uint32_t MTIME_LO; volatile uint32_t MTIME_LO;
volatile uint32_t MTIME_HI; volatile uint32_t MTIME_HI;
} aclint_t; }aclint_t;
#define ACLINT_MSIP0_OFFS 0 #define ACLINT_MSIP0_OFFS 0
#define ACLINT_MSIP0_MASK 0x1 #define ACLINT_MSIP0_MASK 0x1
@ -42,34 +42,50 @@ typedef struct {
#define ACLINT_MTIME_HI_MASK 0xffffffff #define ACLINT_MTIME_HI_MASK 0xffffffff
#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS) #define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
// ACLINT_MSIP0 //ACLINT_MSIP0
static inline uint32_t get_aclint_msip0(volatile aclint_t* reg) { return reg->MSIP0; } inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
static inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value) { reg->MSIP0 = value; } return reg->MSIP0;
static inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg) { return (reg->MSIP0 >> 0) & 0x1; } }
static inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value) { reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0); } inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){
reg->MSIP0 = value;
// ACLINT_MTIMECMP0LO }
static inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff; } inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
static inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value) { return (reg->MSIP0 >> 0) & 0x1;
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
} }
// ACLINT_MTIMECMP0HI //ACLINT_MTIMECMP0LO
static inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff; } inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){
static inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value) { return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIME_LO //ACLINT_MTIMECMP0HI
static inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg) { return (reg->MTIME_LO >> 0) & 0xffffffff; } inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){
static inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value) { return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
} }
// ACLINT_MTIME_HI //ACLINT_MTIME_LO
static inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg) { return (reg->MTIME_HI >> 0) & 0xffffffff; } inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){
static inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value) { return (reg->MTIME_LO >> 0) & 0xffffffff;
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
} }
#endif /* _BSP_ACLINT_H */ //ACLINT_MTIME_HI
inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){
return (reg->MTIME_HI >> 0) & 0xffffffff;
}
inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_ACLINT_H */

410
include/ehrenberg/devices/gen/apb3spi.h
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@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2025-02-17 15:56:47 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_APB3SPI_H #ifndef _BSP_APB3SPI_H
#define _BSP_APB3SPI_H #define _BSP_APB3SPI_H
@ -13,25 +13,25 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t DATA; volatile uint32_t DATA;
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t CONFIG; volatile uint32_t CONFIG;
volatile uint32_t INTR; volatile uint32_t INTR;
uint8_t fill0[16]; uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG; volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP; volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD; volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE; volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH; volatile uint32_t SSGEN_ACTIVE_HIGH;
uint8_t fill1[12]; uint8_t fill1[12];
volatile uint32_t XIP_ENABLE; volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG; volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE; volatile uint32_t XIP_MODE;
uint8_t fill2[4]; uint8_t fill2[4];
volatile uint32_t XIP_WRITE; volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE; volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ; volatile uint32_t XIP_READ;
} apb3spi_t; }apb3spi_t;
#define APB3SPI_DATA_DATA_OFFS 0 #define APB3SPI_DATA_DATA_OFFS 0
#define APB3SPI_DATA_DATA_MASK 0xff #define APB3SPI_DATA_DATA_MASK 0xff
@ -106,7 +106,7 @@ typedef struct {
#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS) #define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0 #define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1 #define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0xf
#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS) #define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
#define APB3SPI_XIP_ENABLE_OFFS 0 #define APB3SPI_XIP_ENABLE_OFFS 0
@ -157,154 +157,274 @@ typedef struct {
#define APB3SPI_XIP_READ_MASK 0xff #define APB3SPI_XIP_READ_MASK 0xff
#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS) #define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
// APB3SPI_DATA //APB3SPI_DATA
static inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg) { return reg->DATA; } inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){
static inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value) { reg->DATA = value; } return reg->DATA;
static inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0); }
static inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg) { return (reg->DATA >> 8) & 0x1; }
static inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8); }
static inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg) { return (reg->DATA >> 9) & 0x1; }
static inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg) { return (reg->DATA >> 11) & 0x1; }
static inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value) {
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
} }
static inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg) { return (reg->DATA >> 31) & 0x1; } inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){
reg->DATA = value;
// APB3SPI_STATUS
static inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg) { return reg->STATUS; }
static inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg) { return (reg->STATUS >> 0) & 0x3f; }
static inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg) { return (reg->STATUS >> 16) & 0x3f; }
// APB3SPI_CONFIG
static inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg) { return reg->CONFIG; }
static inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value) { reg->CONFIG = value; }
static inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
} }
static inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg) { return (reg->CONFIG >> 4) & 0x3; } inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){
static inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value) { reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4); }
inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
return (reg->DATA >> 8) & 0x1;
}
inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
return (reg->DATA >> 9) & 0x1;
}
inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_data_ssgen(volatile apb3spi_t* reg){
return (reg->DATA >> 11) & 0x1;
}
inline void set_apb3spi_data_ssgen(volatile apb3spi_t* reg, uint8_t value){
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
}
inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
return (reg->DATA >> 31) & 0x1;
} }
// APB3SPI_INTR //APB3SPI_STATUS
static inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg) { return reg->INTR; } inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
static inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value) { reg->INTR = value; } return reg->STATUS;
static inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 0) & 0x1; } }
static inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0); } inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
static inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg) { return (reg->INTR >> 1) & 0x1; } return (reg->STATUS >> 0) & 0x3f;
static inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1); } }
static inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 8) & 0x1; } inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
static inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8); } return (reg->STATUS >> 16) & 0x3f;
static inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg) { return (reg->INTR >> 9) & 0x1; }
static inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value) { reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9); }
static inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg) { return (reg->INTR >> 16) & 0x1; }
// APB3SPI_SCLK_CONFIG
static inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg) { return reg->SCLK_CONFIG; }
static inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value) { reg->SCLK_CONFIG = value; }
static inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg) { return (reg->SCLK_CONFIG >> 0) & 0xfff; }
static inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value) {
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_SSGEN_SETUP //APB3SPI_CONFIG
static inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg) { return reg->SSGEN_SETUP; } inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){
static inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_SETUP = value; } return reg->CONFIG;
static inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_SETUP >> 0) & 0xfff; } }
static inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value) { inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0); reg->CONFIG = value;
}
inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
return (reg->CONFIG >> 0) & 0x3;
}
inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){
return (reg->CONFIG >> 4) & 0x3;
}
inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
} }
// APB3SPI_SSGEN_HOLD //APB3SPI_INTR
static inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg) { return reg->SSGEN_HOLD; } inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){
static inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_HOLD = value; } return reg->INTR;
static inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_HOLD >> 0) & 0xfff; } }
static inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value) { inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0); reg->INTR = value;
}
inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 0) & 0x1;
}
inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
return (reg->INTR >> 1) & 0x1;
}
inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 8) & 0x1;
}
inline void set_apb3spi_intr_tx_ip(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
return (reg->INTR >> 9) & 0x1;
}
inline void set_apb3spi_intr_rx_ip(volatile apb3spi_t* reg, uint8_t value){
reg->INTR = (reg->INTR & ~(0x1U << 9)) | (value << 9);
}
inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
return (reg->INTR >> 16) & 0x1;
} }
// APB3SPI_SSGEN_DISABLE //APB3SPI_SCLK_CONFIG
static inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg) { return reg->SSGEN_DISABLE; } inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
static inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_DISABLE = value; } return reg->SCLK_CONFIG;
static inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg) { return (reg->SSGEN_DISABLE >> 0) & 0xfff; } }
static inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value) { inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0); reg->SCLK_CONFIG = value;
}
inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
return (reg->SCLK_CONFIG >> 0) & 0xfff;
}
inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_SSGEN_ACTIVE_HIGH //APB3SPI_SSGEN_SETUP
static inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg) { return reg->SSGEN_ACTIVE_HIGH; } inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
static inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value) { reg->SSGEN_ACTIVE_HIGH = value; } return reg->SSGEN_SETUP;
static inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg) {
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
} }
static inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value) { inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); reg->SSGEN_SETUP = value;
}
inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_SETUP >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_XIP_ENABLE //APB3SPI_SSGEN_HOLD
static inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg) { return reg->XIP_ENABLE; } inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
static inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_ENABLE = value; } return reg->SSGEN_HOLD;
static inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg) { return (reg->XIP_ENABLE >> 0) & 0x1; } }
static inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value) { inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0); reg->SSGEN_HOLD = value;
}
inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
return (reg->SSGEN_HOLD >> 0) & 0xfff;
}
inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
} }
// APB3SPI_XIP_CONFIG //APB3SPI_SSGEN_DISABLE
static inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg) { return reg->XIP_CONFIG; } inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
static inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_CONFIG = value; } return reg->SSGEN_DISABLE;
static inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 0) & 0xff; }
static inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
} }
static inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 8) & 0x1; } inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){
static inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value) { reg->SSGEN_DISABLE = value;
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
} }
static inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 16) & 0xff; } inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
static inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value) { return (reg->SSGEN_DISABLE >> 0) & 0xfff;
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
} }
static inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg) { return (reg->XIP_CONFIG >> 24) & 0xf; } inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
static inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value) { reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
} }
// APB3SPI_XIP_MODE //APB3SPI_SSGEN_ACTIVE_HIGH
static inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg) { return reg->XIP_MODE; } inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
static inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_MODE = value; } return reg->SSGEN_ACTIVE_HIGH;
static inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 0) & 0x3; }
static inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value) {
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
} }
static inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 8) & 0x3; } inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
static inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value) { reg->SSGEN_ACTIVE_HIGH = value;
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
} }
static inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 16) & 0x3; } inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
static inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value) { return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0xf;
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
} }
static inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg) { return (reg->XIP_MODE >> 24) & 0x3; } inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
static inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value) { reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0xfU << 0)) | (value << 0);
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
} }
// APB3SPI_XIP_WRITE //APB3SPI_XIP_ENABLE
static inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_WRITE = value; } inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
static inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value) { return reg->XIP_ENABLE;
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0); }
inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_ENABLE = value;
}
inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
return (reg->XIP_ENABLE >> 0) & 0x1;
}
inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
} }
// APB3SPI_XIP_READ_WRITE //APB3SPI_XIP_CONFIG
static inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value) { reg->XIP_READ_WRITE = value; } inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){
static inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value) { return reg->XIP_CONFIG;
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0); }
inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_CONFIG = value;
}
inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 0) & 0xff;
}
inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 8) & 0x1;
}
inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 16) & 0xff;
}
inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){
return (reg->XIP_CONFIG >> 24) & 0xf;
}
inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
} }
// APB3SPI_XIP_READ //APB3SPI_XIP_MODE
static inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg) { return reg->XIP_READ; } inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){
static inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg) { return (reg->XIP_READ >> 0) & 0xff; } return reg->XIP_MODE;
}
inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_MODE = value;
}
inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 0) & 0x3;
}
inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 8) & 0x3;
}
inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
}
inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 16) & 0x3;
}
inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
}
inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){
return (reg->XIP_MODE >> 24) & 0x3;
}
inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
}
//APB3SPI_XIP_WRITE
inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_WRITE = value;
}
inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
}
//APB3SPI_XIP_READ_WRITE
inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){
reg->XIP_READ_WRITE = value;
}
inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
}
//APB3SPI_XIP_READ
inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
return reg->XIP_READ;
}
inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
return (reg->XIP_READ >> 0) & 0xff;
}
#endif /* _BSP_APB3SPI_H */ #endif /* _BSP_APB3SPI_H */

307
include/ehrenberg/devices/gen/camera.h
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2025 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2025-02-28 17:25:03 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_CAMERA_H #ifndef _BSP_CAMERA_H
#define _BSP_CAMERA_H #define _BSP_CAMERA_H
@ -13,16 +13,16 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t PIXEL; volatile uint32_t PIXEL;
volatile uint32_t CONFIG; volatile uint32_t CONFIG;
volatile uint32_t CONFIG2; volatile uint32_t CONFIG2;
volatile uint32_t DATA_SIZE; volatile uint32_t DATA_SIZE;
volatile uint32_t START; volatile uint32_t START;
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t CAMERA_CLOCK_CTRL; volatile uint32_t CAMERA_CLOCK_CTRL;
volatile uint32_t IE; volatile uint32_t IE;
volatile uint32_t IP; volatile uint32_t IP;
} camera_t; }camera_t;
#define CAMERA_PIXEL_OFFS 0 #define CAMERA_PIXEL_OFFS 0
#define CAMERA_PIXEL_MASK 0xffffffff #define CAMERA_PIXEL_MASK 0xffffffff
@ -124,134 +124,211 @@ typedef struct {
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1 #define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS) #define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
// CAMERA_PIXEL //CAMERA_PIXEL
static inline uint32_t get_camera_pixel(volatile camera_t* reg) { return (reg->PIXEL >> 0) & 0xffffffff; } inline uint32_t get_camera_pixel(volatile camera_t* reg){
static inline void set_camera_pixel(volatile camera_t* reg, uint32_t value) { return (reg->PIXEL >> 0) & 0xffffffff;
reg->PIXEL = (reg->PIXEL & ~(0xffffffffU << 0)) | (value << 0);
} }
// CAMERA_CONFIG //CAMERA_CONFIG
static inline uint32_t get_camera_config(volatile camera_t* reg) { return reg->CONFIG; } inline uint32_t get_camera_config(volatile camera_t* reg){
static inline void set_camera_config(volatile camera_t* reg, uint32_t value) { reg->CONFIG = value; } return reg->CONFIG;
static inline uint32_t get_camera_config_output_curr(volatile camera_t* reg) { return (reg->CONFIG >> 0) & 0x3; }
static inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value) {
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
} }
static inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg) { return (reg->CONFIG >> 2) & 0x3; } inline void set_camera_config(volatile camera_t* reg, uint32_t value){
static inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value) { reg->CONFIG = value;
reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
} }
static inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg) { return (reg->CONFIG >> 4) & 0x3; } inline uint32_t get_camera_config_output_curr(volatile camera_t* reg){
static inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value) { return (reg->CONFIG >> 0) & 0x3;
reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
} }
static inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg) { return (reg->CONFIG >> 6) & 0x3; } inline void set_camera_config_output_curr(volatile camera_t* reg, uint8_t value){
static inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
} }
static inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg) { return (reg->CONFIG >> 8) & 0xff; } inline uint32_t get_camera_config_offset_ramp(volatile camera_t* reg){
static inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value) { return (reg->CONFIG >> 2) & 0x3;
reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
} }
static inline uint32_t get_camera_config_high_speed(volatile camera_t* reg) { return (reg->CONFIG >> 16) & 0x1; } inline void set_camera_config_offset_ramp(volatile camera_t* reg, uint8_t value){
static inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 2)) | (value << 2);
reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
} }
static inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg) { return (reg->CONFIG >> 17) & 0x1; } inline uint32_t get_camera_config_ramp_gain(volatile camera_t* reg){
static inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value) { return (reg->CONFIG >> 4) & 0x3;
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
} }
static inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg) { return (reg->CONFIG >> 18) & 0x3; } inline void set_camera_config_ramp_gain(volatile camera_t* reg, uint8_t value){
static inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
} }
static inline uint32_t get_camera_config_vref(volatile camera_t* reg) { return (reg->CONFIG >> 20) & 0x3; } inline uint32_t get_camera_config_vrst_pix(volatile camera_t* reg){
static inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value) { return (reg->CONFIG >> 6) & 0x3;
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
} }
static inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg) { return (reg->CONFIG >> 22) & 0x3; } inline void set_camera_config_vrst_pix(volatile camera_t* reg, uint8_t value){
static inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x3U << 6)) | (value << 6);
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
} }
static inline uint32_t get_camera_config_output_mode(volatile camera_t* reg) { return (reg->CONFIG >> 24) & 0x1; } inline uint32_t get_camera_config_rows_in_reset(volatile camera_t* reg){
static inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value) { return (reg->CONFIG >> 8) & 0xff;
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
} }
static inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg) { return (reg->CONFIG >> 25) & 0x1; } inline void set_camera_config_rows_in_reset(volatile camera_t* reg, uint8_t value){
static inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0xffU << 8)) | (value << 8);
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
} }
static inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg) { return (reg->CONFIG >> 26) & 0x1; } inline uint32_t get_camera_config_high_speed(volatile camera_t* reg){
static inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value) { return (reg->CONFIG >> 16) & 0x1;
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
} }
static inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg) { return (reg->CONFIG >> 27) & 0x1f; } inline void set_camera_config_high_speed(volatile camera_t* reg, uint8_t value){
static inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value) { reg->CONFIG = (reg->CONFIG & ~(0x1U << 16)) | (value << 16);
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27); }
inline uint32_t get_camera_config_idle_mode(volatile camera_t* reg){
return (reg->CONFIG >> 17) & 0x1;
}
inline void set_camera_config_idle_mode(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 17)) | (value << 17);
}
inline uint32_t get_camera_config_cvc_curr(volatile camera_t* reg){
return (reg->CONFIG >> 18) & 0x3;
}
inline void set_camera_config_cvc_curr(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 18)) | (value << 18);
}
inline uint32_t get_camera_config_vref(volatile camera_t* reg){
return (reg->CONFIG >> 20) & 0x3;
}
inline void set_camera_config_vref(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 20)) | (value << 20);
}
inline uint32_t get_camera_config_mclk_mode(volatile camera_t* reg){
return (reg->CONFIG >> 22) & 0x3;
}
inline void set_camera_config_mclk_mode(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x3U << 22)) | (value << 22);
}
inline uint32_t get_camera_config_output_mode(volatile camera_t* reg){
return (reg->CONFIG >> 24) & 0x1;
}
inline void set_camera_config_output_mode(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 24)) | (value << 24);
}
inline uint32_t get_camera_config_cds_gain(volatile camera_t* reg){
return (reg->CONFIG >> 25) & 0x1;
}
inline void set_camera_config_cds_gain(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 25)) | (value << 25);
}
inline uint32_t get_camera_config_bias_curr_increase(volatile camera_t* reg){
return (reg->CONFIG >> 26) & 0x1;
}
inline void set_camera_config_bias_curr_increase(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1U << 26)) | (value << 26);
}
inline uint32_t get_camera_config_rows_delay(volatile camera_t* reg){
return (reg->CONFIG >> 27) & 0x1f;
}
inline void set_camera_config_rows_delay(volatile camera_t* reg, uint8_t value){
reg->CONFIG = (reg->CONFIG & ~(0x1fU << 27)) | (value << 27);
} }
// CAMERA_CONFIG2 //CAMERA_CONFIG2
static inline uint32_t get_camera_config2(volatile camera_t* reg) { return reg->CONFIG2; } inline uint32_t get_camera_config2(volatile camera_t* reg){
static inline void set_camera_config2(volatile camera_t* reg, uint32_t value) { reg->CONFIG2 = value; } return reg->CONFIG2;
static inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg) { return (reg->CONFIG2 >> 0) & 0x1; }
static inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value) {
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg) { return (reg->CONFIG2 >> 1) & 0x1; } inline void set_camera_config2(volatile camera_t* reg, uint32_t value){
static inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value) { reg->CONFIG2 = value;
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1); }
inline uint32_t get_camera_config2_auto_idle(volatile camera_t* reg){
return (reg->CONFIG2 >> 0) & 0x1;
}
inline void set_camera_config2_auto_idle(volatile camera_t* reg, uint8_t value){
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_config2_auto_discard_frame(volatile camera_t* reg){
return (reg->CONFIG2 >> 1) & 0x1;
}
inline void set_camera_config2_auto_discard_frame(volatile camera_t* reg, uint8_t value){
reg->CONFIG2 = (reg->CONFIG2 & ~(0x1U << 1)) | (value << 1);
} }
// CAMERA_DATA_SIZE //CAMERA_DATA_SIZE
static inline uint32_t get_camera_data_size(volatile camera_t* reg) { return reg->DATA_SIZE; } inline uint32_t get_camera_data_size(volatile camera_t* reg){
static inline void set_camera_data_size(volatile camera_t* reg, uint32_t value) { reg->DATA_SIZE = value; } return reg->DATA_SIZE;
static inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg) { return (reg->DATA_SIZE >> 0) & 0x3; } }
static inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value) { inline void set_camera_data_size(volatile camera_t* reg, uint32_t value){
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0); reg->DATA_SIZE = value;
}
inline uint32_t get_camera_data_size_data_size(volatile camera_t* reg){
return (reg->DATA_SIZE >> 0) & 0x3;
}
inline void set_camera_data_size_data_size(volatile camera_t* reg, uint8_t value){
reg->DATA_SIZE = (reg->DATA_SIZE & ~(0x3U << 0)) | (value << 0);
} }
// CAMERA_START //CAMERA_START
static inline uint32_t get_camera_start(volatile camera_t* reg) { return reg->START; } inline uint32_t get_camera_start(volatile camera_t* reg){
static inline void set_camera_start(volatile camera_t* reg, uint32_t value) { reg->START = value; } return reg->START;
static inline uint32_t get_camera_start_start(volatile camera_t* reg) { return (reg->START >> 0) & 0x1; } }
static inline void set_camera_start_start(volatile camera_t* reg, uint8_t value) { inline void set_camera_start(volatile camera_t* reg, uint32_t value){
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0); reg->START = value;
}
inline uint32_t get_camera_start_start(volatile camera_t* reg){
return (reg->START >> 0) & 0x1;
}
inline void set_camera_start_start(volatile camera_t* reg, uint8_t value){
reg->START = (reg->START & ~(0x1U << 0)) | (value << 0);
} }
// CAMERA_STATUS //CAMERA_STATUS
static inline uint32_t get_camera_status(volatile camera_t* reg) { return reg->STATUS; } inline uint32_t get_camera_status(volatile camera_t* reg){
static inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg) { return (reg->STATUS >> 0) & 0x1; } return reg->STATUS;
}
// CAMERA_CAMERA_CLOCK_CTRL inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
static inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg) { return reg->CAMERA_CLOCK_CTRL; } return (reg->STATUS >> 0) & 0x1;
static inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value) { reg->CAMERA_CLOCK_CTRL = value; }
static inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg) { return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff; }
static inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value) {
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
} }
// CAMERA_IE //CAMERA_CAMERA_CLOCK_CTRL
static inline uint32_t get_camera_ie(volatile camera_t* reg) { return reg->IE; } inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
static inline void set_camera_ie(volatile camera_t* reg, uint32_t value) { reg->IE = value; } return reg->CAMERA_CLOCK_CTRL;
static inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg) { return (reg->IE >> 1) & 0x1; } inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
static inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value) { reg->CAMERA_CLOCK_CTRL = value;
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); }
inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfff;
}
inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint16_t value){
reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffU << 0)) | (value << 0);
} }
// CAMERA_IP //CAMERA_IE
static inline uint32_t get_camera_ip(volatile camera_t* reg) { return reg->IP; } inline uint32_t get_camera_ie(volatile camera_t* reg){
static inline void set_camera_ip(volatile camera_t* reg, uint32_t value) { reg->IP = value; } return reg->IE;
static inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg) { return (reg->IP >> 0) & 0x1; }
static inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value) {
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg) { return (reg->IP >> 1) & 0x1; } inline void set_camera_ie(volatile camera_t* reg, uint32_t value){
static inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value) { reg->IE = value;
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1); }
inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
//CAMERA_IP
inline uint32_t get_camera_ip(volatile camera_t* reg){
return reg->IP;
}
inline void set_camera_ip(volatile camera_t* reg, uint32_t value){
reg->IP = value;
}
inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){
return (reg->IP >> 1) & 0x1;
}
inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
} }
#endif /* _BSP_CAMERA_H */ #endif /* _BSP_CAMERA_H */

424
include/ehrenberg/devices/gen/dma.h
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-08-02 08:46:07 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.7 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_DMA_H #ifndef _BSP_DMA_H
#define _BSP_DMA_H #define _BSP_DMA_H
@ -13,23 +13,23 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t CONTROL; volatile uint32_t CONTROL;
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t IE; volatile uint32_t IE;
volatile uint32_t IP; volatile uint32_t IP;
volatile uint32_t CH0_EVENT; volatile uint32_t CH0_EVENT;
volatile uint32_t CH0_TRANSFER; volatile uint32_t CH0_TRANSFER;
volatile uint32_t CH0_SRC_START_ADDR; volatile uint32_t CH0_SRC_START_ADDR;
volatile uint32_t CH0_SRC_ADDR_INC; volatile uint32_t CH0_SRC_ADDR_INC;
volatile uint32_t CH0_DST_START_ADDR; volatile uint32_t CH0_DST_START_ADDR;
volatile uint32_t CH0_DST_ADDR_INC; volatile uint32_t CH0_DST_ADDR_INC;
volatile uint32_t CH1_EVENT; volatile uint32_t CH1_EVENT;
volatile uint32_t CH1_TRANSFER; volatile uint32_t CH1_TRANSFER;
volatile uint32_t CH1_SRC_START_ADDR; volatile uint32_t CH1_SRC_START_ADDR;
volatile uint32_t CH1_SRC_ADDR_INC; volatile uint32_t CH1_SRC_ADDR_INC;
volatile uint32_t CH1_DST_START_ADDR; volatile uint32_t CH1_DST_START_ADDR;
volatile uint32_t CH1_DST_ADDR_INC; volatile uint32_t CH1_DST_ADDR_INC;
} dma_t; }dma_t;
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0 #define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1 #define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
@ -167,176 +167,288 @@ typedef struct {
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff #define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS) #define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
// DMA_CONTROL //DMA_CONTROL
static inline uint32_t get_dma_control(volatile dma_t* reg) { return reg->CONTROL; } inline uint32_t get_dma_control(volatile dma_t* reg){
static inline void set_dma_control(volatile dma_t* reg, uint32_t value) { reg->CONTROL = value; } return reg->CONTROL;
static inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 0) & 0x1; }
static inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg) { return (reg->CONTROL >> 1) & 0x1; } inline void set_dma_control(volatile dma_t* reg, uint32_t value){
static inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value) { reg->CONTROL = value;
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1); }
inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
return (reg->CONTROL >> 1) & 0x1;
}
inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
} }
// DMA_STATUS //DMA_STATUS
static inline uint32_t get_dma_status(volatile dma_t* reg) { return reg->STATUS; } inline uint32_t get_dma_status(volatile dma_t* reg){
static inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg) { return (reg->STATUS >> 0) & 0x1; } return reg->STATUS;
static inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg) { return (reg->STATUS >> 1) & 0x1; }
// DMA_IE
static inline uint32_t get_dma_ie(volatile dma_t* reg) { return reg->IE; }
static inline void set_dma_ie(volatile dma_t* reg, uint32_t value) { reg->IE = value; }
static inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 1) & 0x1; } inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
static inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value) { return (reg->STATUS >> 0) & 0x1;
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
} }
static inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg) { return (reg->IE >> 2) & 0x1; } inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
static inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value) { return (reg->STATUS >> 1) & 0x1;
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg) { return (reg->IE >> 3) & 0x1; }
static inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
} }
// DMA_IP //DMA_IE
static inline uint32_t get_dma_ip(volatile dma_t* reg) { return reg->IP; } inline uint32_t get_dma_ie(volatile dma_t* reg){
static inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 0) & 0x1; } return reg->IE;
static inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 1) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg) { return (reg->IP >> 2) & 0x1; }
static inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg) { return (reg->IP >> 3) & 0x1; }
// DMA_CH0_EVENT
static inline uint32_t get_dma_ch0_event(volatile dma_t* reg) { return reg->CH0_EVENT; }
static inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value) { reg->CH0_EVENT = value; }
static inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg) { return (reg->CH0_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg) { return (reg->CH0_EVENT >> 31) & 0x1; } inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
static inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value) { reg->IE = value;
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31); }
inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
return (reg->IE >> 2) & 0x1;
}
inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
return (reg->IE >> 3) & 0x1;
}
inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
} }
// DMA_CH0_TRANSFER //DMA_IP
static inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg) { return reg->CH0_TRANSFER; } inline uint32_t get_dma_ip(volatile dma_t* reg){
static inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value; } return reg->IP;
static inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 2) & 0x3ff; } inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
static inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value) { return (reg->IP >> 0) & 0x1;
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
} }
static inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg) { return (reg->CH0_TRANSFER >> 12) & 0xfffff; } inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
static inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value) { return (reg->IP >> 1) & 0x1;
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12); }
inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
return (reg->IP >> 2) & 0x1;
}
inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
return (reg->IP >> 3) & 0x1;
} }
// DMA_CH0_SRC_START_ADDR //DMA_CH0_EVENT
static inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff; } inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
static inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value) { return reg->CH0_EVENT;
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
reg->CH0_EVENT = value;
}
inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
return (reg->CH0_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
return (reg->CH0_EVENT >> 31) & 0x1;
}
inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
} }
// DMA_CH0_SRC_ADDR_INC //DMA_CH0_TRANSFER
static inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg) { return reg->CH0_SRC_ADDR_INC; } inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
static inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value; } return reg->CH0_TRANSFER;
static inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff; } inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
static inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) { reg->CH0_TRANSFER = value;
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); }
inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
return (reg->CH0_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH0_DST_START_ADDR //DMA_CH0_SRC_START_ADDR
static inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg) { return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff; } inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
static inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value) { return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
// DMA_CH0_DST_ADDR_INC //DMA_CH0_SRC_ADDR_INC
static inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg) { return reg->CH0_DST_ADDR_INC; } inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
static inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH0_DST_ADDR_INC = value; } return reg->CH0_SRC_ADDR_INC;
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff; } inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
static inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) { reg->CH0_SRC_ADDR_INC = value;
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); }
inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH1_EVENT //DMA_CH0_DST_START_ADDR
static inline uint32_t get_dma_ch1_event(volatile dma_t* reg) { return reg->CH1_EVENT; } inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
static inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value) { reg->CH1_EVENT = value; } return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
static inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg) { return (reg->CH1_EVENT >> 0) & 0x1f; }
static inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value) {
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg) { return (reg->CH1_EVENT >> 31) & 0x1; } inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
static inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value) { reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
} }
// DMA_CH1_TRANSFER //DMA_CH0_DST_ADDR_INC
static inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg) { return reg->CH1_TRANSFER; } inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
static inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value; } return reg->CH0_DST_ADDR_INC;
static inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 0) & 0x3; }
static inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value) {
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 2) & 0x3ff; } inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
static inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value) { reg->CH0_DST_ADDR_INC = value;
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
} }
static inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg) { return (reg->CH1_TRANSFER >> 12) & 0xfffff; } inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
static inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value) { return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12); }
inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH1_SRC_START_ADDR //DMA_CH1_EVENT
static inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff; } inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
static inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value) { return reg->CH1_EVENT;
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
reg->CH1_EVENT = value;
}
inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
return (reg->CH1_EVENT >> 0) & 0x1f;
}
inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
return (reg->CH1_EVENT >> 31) & 0x1;
}
inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
} }
// DMA_CH1_SRC_ADDR_INC //DMA_CH1_TRANSFER
static inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg) { return reg->CH1_SRC_ADDR_INC; } inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
static inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value; } return reg->CH1_TRANSFER;
static inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg) { return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff; } inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
static inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value) { reg->CH1_TRANSFER = value;
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); }
inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 0) & 0x3;
}
inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 2) & 0x3ff;
}
inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
}
inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
return (reg->CH1_TRANSFER >> 12) & 0xfffff;
}
inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
} }
// DMA_CH1_DST_START_ADDR //DMA_CH1_SRC_START_ADDR
static inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg) { return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff; } inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
static inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value) { return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
} }
// DMA_CH1_DST_ADDR_INC //DMA_CH1_SRC_ADDR_INC
static inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg) { return reg->CH1_DST_ADDR_INC; } inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
static inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value) { reg->CH1_DST_ADDR_INC = value; } return reg->CH1_SRC_ADDR_INC;
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff; }
static inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value) {
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
} }
static inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg) { return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff; } inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
static inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value) { reg->CH1_SRC_ADDR_INC = value;
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12); }
inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
} }
#endif /* _BSP_DMA_H */ //DMA_CH1_DST_START_ADDR
inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
}
inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
}
//DMA_CH1_DST_ADDR_INC
inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
return reg->CH1_DST_ADDR_INC;
}
inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = value;
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
}
inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
}
inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
}
inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
}
#endif /* _BSP_DMA_H */

468
include/ehrenberg/devices/gen/gpio.h
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-12-06 09:43:24 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_GPIO_H #ifndef _BSP_GPIO_H
#define _BSP_GPIO_H #define _BSP_GPIO_H
@ -13,21 +13,21 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t VALUE; volatile uint32_t VALUE;
volatile uint32_t WRITE; volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE; volatile uint32_t WRITEENABLE;
volatile uint32_t PULLUP; volatile uint32_t PULLUP;
volatile uint32_t PULDOWN; volatile uint32_t PULDOWN;
volatile uint32_t DRIVESTRENGTH_0; volatile uint32_t DRIVESTRENGTH_0;
volatile uint32_t DRIVESTRENGTH_1; volatile uint32_t DRIVESTRENGTH_1;
volatile uint32_t DRIVESTRENGTH_2; volatile uint32_t DRIVESTRENGTH_2;
volatile uint32_t DRIVESTRENGTH_3; volatile uint32_t DRIVESTRENGTH_3;
volatile uint32_t IE; volatile uint32_t IE;
volatile uint32_t IP; volatile uint32_t IP;
volatile uint32_t IRQ_TRIGGER; volatile uint32_t IRQ_TRIGGER;
volatile uint32_t IRQ_TYPE; volatile uint32_t IRQ_TYPE;
volatile uint32_t BOOT_SEL; volatile uint32_t BOOT_SEL;
} gpio_t; }gpio_t;
#define GPIO_VALUE_OFFS 0 #define GPIO_VALUE_OFFS 0
#define GPIO_VALUE_MASK 0xffffffff #define GPIO_VALUE_MASK 0xffffffff
@ -197,197 +197,305 @@ typedef struct {
#define GPIO_BOOT_SEL_MASK 0x7 #define GPIO_BOOT_SEL_MASK 0x7
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS) #define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
// GPIO_VALUE //GPIO_VALUE
static inline uint32_t get_gpio_value(volatile gpio_t* reg) { return (reg->VALUE >> 0) & 0xffffffff; } inline uint32_t get_gpio_value(volatile gpio_t* reg){
return (reg->VALUE >> 0) & 0xffffffff;
// GPIO_WRITE
static inline uint32_t get_gpio_write(volatile gpio_t* reg) { return (reg->WRITE >> 0) & 0xffffffff; }
static inline void set_gpio_write(volatile gpio_t* reg, uint32_t value) { reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0); }
// GPIO_WRITEENABLE
static inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg) { return (reg->WRITEENABLE >> 0) & 0xffffffff; }
static inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value) {
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_PULLUP //GPIO_WRITE
static inline uint32_t get_gpio_pullup(volatile gpio_t* reg) { return (reg->PULLUP >> 0) & 0xffffffff; } inline uint32_t get_gpio_write(volatile gpio_t* reg){
static inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value) { return (reg->WRITE >> 0) & 0xffffffff;
reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_PULDOWN //GPIO_WRITEENABLE
static inline uint32_t get_gpio_puldown(volatile gpio_t* reg) { return (reg->PULDOWN >> 0) & 0xffffffff; } inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){
static inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value) { return (reg->WRITEENABLE >> 0) & 0xffffffff;
reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
} }
// GPIO_DRIVESTRENGTH_0 //GPIO_PULLUP
static inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_0; } inline uint32_t get_gpio_pullup(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_0 = value; } return (reg->PULLUP >> 0) & 0xffffffff;
static inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
} }
static inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7; } inline void set_gpio_pullup(volatile gpio_t* reg, uint32_t value){
static inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value) { reg->PULLUP = (reg->PULLUP & ~(0xffffffffU << 0)) | (value << 0);
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_0 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_DRIVESTRENGTH_1 //GPIO_PULDOWN
static inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_1; } inline uint32_t get_gpio_puldown(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_1 = value; } return (reg->PULDOWN >> 0) & 0xffffffff;
static inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
} }
static inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7; } inline void set_gpio_puldown(volatile gpio_t* reg, uint32_t value){
static inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value) { reg->PULDOWN = (reg->PULDOWN & ~(0xffffffffU << 0)) | (value << 0);
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
}
static inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
}
static inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 12) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
}
static inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 16) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
}
static inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 20) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
}
static inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 24) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
}
static inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_1 >> 28) & 0x7; }
static inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_DRIVESTRENGTH_2 //GPIO_DRIVESTRENGTH_0
static inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_2; } inline uint32_t get_gpio_driveStrength_0(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_2 = value; } return reg->DRIVESTRENGTH_0;
static inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
} }
static inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 4) & 0x7; } inline void set_gpio_driveStrength_0(volatile gpio_t* reg, uint32_t value){
static inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = value;
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
} }
static inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 8) & 0x7; } inline uint32_t get_gpio_driveStrength_0_pin_0(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value) { return (reg->DRIVESTRENGTH_0 >> 0) & 0x7;
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
} }
static inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 12) & 0x7; } inline void set_gpio_driveStrength_0_pin_0(volatile gpio_t* reg, uint8_t value){
static inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 0)) | (value << 0);
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
} }
static inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 16) & 0x7; } inline uint32_t get_gpio_driveStrength_0_pin_1(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value) { return (reg->DRIVESTRENGTH_0 >> 4) & 0x7;
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
} }
static inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 20) & 0x7; } inline void set_gpio_driveStrength_0_pin_1(volatile gpio_t* reg, uint8_t value){
static inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 4)) | (value << 4);
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
} }
static inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 24) & 0x7; } inline uint32_t get_gpio_driveStrength_0_pin_2(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value) { return (reg->DRIVESTRENGTH_0 >> 8) & 0x7;
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
} }
static inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_2 >> 28) & 0x7; } inline void set_gpio_driveStrength_0_pin_2(volatile gpio_t* reg, uint8_t value){
static inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 8)) | (value << 8);
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28); }
inline uint32_t get_gpio_driveStrength_0_pin_3(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_3(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_0_pin_4(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_4(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_0_pin_5(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_5(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_0_pin_6(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_6(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_0_pin_7(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_0 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_0_pin_7(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_0 = (reg->DRIVESTRENGTH_0 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_DRIVESTRENGTH_3 //GPIO_DRIVESTRENGTH_1
static inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg) { return reg->DRIVESTRENGTH_3; } inline uint32_t get_gpio_driveStrength_1(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value) { reg->DRIVESTRENGTH_3 = value; } return reg->DRIVESTRENGTH_1;
static inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 0) & 0x7; }
static inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value) {
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
} }
static inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 4) & 0x7; } inline void set_gpio_driveStrength_1(volatile gpio_t* reg, uint32_t value){
static inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = value;
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
} }
static inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 8) & 0x7; } inline uint32_t get_gpio_driveStrength_1_pin_8(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value) { return (reg->DRIVESTRENGTH_1 >> 0) & 0x7;
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
} }
static inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 12) & 0x7; } inline void set_gpio_driveStrength_1_pin_8(volatile gpio_t* reg, uint8_t value){
static inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 0)) | (value << 0);
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
} }
static inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 16) & 0x7; } inline uint32_t get_gpio_driveStrength_1_pin_9(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value) { return (reg->DRIVESTRENGTH_1 >> 4) & 0x7;
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
} }
static inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 20) & 0x7; } inline void set_gpio_driveStrength_1_pin_9(volatile gpio_t* reg, uint8_t value){
static inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 4)) | (value << 4);
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
} }
static inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 24) & 0x7; } inline uint32_t get_gpio_driveStrength_1_pin_10(volatile gpio_t* reg){
static inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value) { return (reg->DRIVESTRENGTH_1 >> 8) & 0x7;
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
} }
static inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg) { return (reg->DRIVESTRENGTH_3 >> 28) & 0x7; } inline void set_gpio_driveStrength_1_pin_10(volatile gpio_t* reg, uint8_t value){
static inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value) { reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 8)) | (value << 8);
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28); }
inline uint32_t get_gpio_driveStrength_1_pin_11(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_11(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_1_pin_12(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_12(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_1_pin_13(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_13(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_1_pin_14(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_14(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_1_pin_15(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_1 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_1_pin_15(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_1 = (reg->DRIVESTRENGTH_1 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_IE //GPIO_DRIVESTRENGTH_2
static inline uint32_t get_gpio_ie(volatile gpio_t* reg) { return (reg->IE >> 0) & 0xffffffff; } inline uint32_t get_gpio_driveStrength_2(volatile gpio_t* reg){
static inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value) { reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0); } return reg->DRIVESTRENGTH_2;
}
// GPIO_IP inline void set_gpio_driveStrength_2(volatile gpio_t* reg, uint32_t value){
static inline uint32_t get_gpio_ip(volatile gpio_t* reg) { return (reg->IP >> 0) & 0xffffffff; } reg->DRIVESTRENGTH_2 = value;
static inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value) { reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0); } }
inline uint32_t get_gpio_driveStrength_2_pin_16(volatile gpio_t* reg){
// GPIO_IRQ_TRIGGER return (reg->DRIVESTRENGTH_2 >> 0) & 0x7;
static inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg) { return (reg->IRQ_TRIGGER >> 0) & 0xffffffff; } }
static inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value) { inline void set_gpio_driveStrength_2_pin_16(volatile gpio_t* reg, uint8_t value){
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0); reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_gpio_driveStrength_2_pin_17(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 4) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_17(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 4)) | (value << 4);
}
inline uint32_t get_gpio_driveStrength_2_pin_18(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 8) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_18(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_gpio_driveStrength_2_pin_19(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_19(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_2_pin_20(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_20(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_2_pin_21(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_21(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_2_pin_22(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_22(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_2_pin_23(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_2 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_2_pin_23(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_2 = (reg->DRIVESTRENGTH_2 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_IRQ_TYPE //GPIO_DRIVESTRENGTH_3
static inline uint32_t get_gpio_irq_type(volatile gpio_t* reg) { return (reg->IRQ_TYPE >> 0) & 0xffffffff; } inline uint32_t get_gpio_driveStrength_3(volatile gpio_t* reg){
static inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value) { return reg->DRIVESTRENGTH_3;
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_gpio_driveStrength_3(volatile gpio_t* reg, uint32_t value){
reg->DRIVESTRENGTH_3 = value;
}
inline uint32_t get_gpio_driveStrength_3_pin_24(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 0) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_24(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_gpio_driveStrength_3_pin_25(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 4) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_25(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 4)) | (value << 4);
}
inline uint32_t get_gpio_driveStrength_3_pin_26(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 8) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_26(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 8)) | (value << 8);
}
inline uint32_t get_gpio_driveStrength_3_pin_27(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 12) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_27(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 12)) | (value << 12);
}
inline uint32_t get_gpio_driveStrength_3_pin_28(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 16) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_28(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 16)) | (value << 16);
}
inline uint32_t get_gpio_driveStrength_3_pin_29(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 20) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_29(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 20)) | (value << 20);
}
inline uint32_t get_gpio_driveStrength_3_pin_30(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 24) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_30(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 24)) | (value << 24);
}
inline uint32_t get_gpio_driveStrength_3_pin_31(volatile gpio_t* reg){
return (reg->DRIVESTRENGTH_3 >> 28) & 0x7;
}
inline void set_gpio_driveStrength_3_pin_31(volatile gpio_t* reg, uint8_t value){
reg->DRIVESTRENGTH_3 = (reg->DRIVESTRENGTH_3 & ~(0x7U << 28)) | (value << 28);
} }
// GPIO_BOOT_SEL //GPIO_IE
static inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg) { return reg->BOOT_SEL; } inline uint32_t get_gpio_ie(volatile gpio_t* reg){
static inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg) { return (reg->BOOT_SEL >> 0) & 0x7; } return (reg->IE >> 0) & 0xffffffff;
}
inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IP
inline uint32_t get_gpio_ip(volatile gpio_t* reg){
return (reg->IP >> 0) & 0xffffffff;
}
inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IRQ_TRIGGER
inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
}
inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IRQ_TYPE
inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){
return (reg->IRQ_TYPE >> 0) & 0xffffffff;
}
inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_BOOT_SEL
inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){
return reg->BOOT_SEL;
}
inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
return (reg->BOOT_SEL >> 0) & 0x7;
}
#endif /* _BSP_GPIO_H */ #endif /* _BSP_GPIO_H */

254
include/ehrenberg/devices/gen/i2s.h
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-12-28 11:01:24 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_I2S_H #ifndef _BSP_I2S_H
#define _BSP_I2S_H #define _BSP_I2S_H
@ -13,16 +13,16 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t LEFT_CH; volatile uint32_t LEFT_CH;
volatile uint32_t RIGHT_CH; volatile uint32_t RIGHT_CH;
volatile uint32_t CONTROL; volatile uint32_t CONTROL;
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t I2S_CLOCK_CTRL; volatile uint32_t I2S_CLOCK_CTRL;
volatile uint32_t PDM_CLOCK_CTRL; volatile uint32_t PDM_CLOCK_CTRL;
volatile uint32_t PDM_FILTER_CTRL; volatile uint32_t PDM_FILTER_CTRL;
volatile uint32_t IE; volatile uint32_t IE;
volatile uint32_t IP; volatile uint32_t IP;
} i2s_t; }i2s_t;
#define I2S_LEFT_CH_OFFS 0 #define I2S_LEFT_CH_OFFS 0
#define I2S_LEFT_CH_MASK 0xffffffff #define I2S_LEFT_CH_MASK 0xffffffff
@ -108,93 +108,163 @@ typedef struct {
#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1 #define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS) #define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
// I2S_LEFT_CH //I2S_LEFT_CH
static inline uint32_t get_i2s_left_ch(volatile i2s_t* reg) { return (reg->LEFT_CH >> 0) & 0xffffffff; } inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
return (reg->LEFT_CH >> 0) & 0xffffffff;
// I2S_RIGHT_CH
static inline uint32_t get_i2s_right_ch(volatile i2s_t* reg) { return (reg->RIGHT_CH >> 0) & 0xffffffff; }
// I2S_CONTROL
static inline uint32_t get_i2s_control(volatile i2s_t* reg) { return reg->CONTROL; }
static inline void set_i2s_control(volatile i2s_t* reg, uint32_t value) { reg->CONTROL = value; }
static inline uint32_t get_i2s_control_mode(volatile i2s_t* reg) { return (reg->CONTROL >> 0) & 0x3; }
static inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value) { reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0); }
static inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg) { return (reg->CONTROL >> 2) & 0x1; }
static inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg) { return (reg->CONTROL >> 3) & 0x1; }
static inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
static inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg) { return (reg->CONTROL >> 4) & 0x1; }
static inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg) { return (reg->CONTROL >> 5) & 0x3; }
static inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
static inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg) { return (reg->CONTROL >> 7) & 0x7; }
static inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value) {
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
} }
// I2S_STATUS //I2S_RIGHT_CH
static inline uint32_t get_i2s_status(volatile i2s_t* reg) { return reg->STATUS; } inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
static inline void set_i2s_status(volatile i2s_t* reg, uint32_t value) { reg->STATUS = value; } return (reg->RIGHT_CH >> 0) & 0xffffffff;
static inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg) { return (reg->STATUS >> 0) & 0x1; }
static inline uint32_t get_i2s_status_active(volatile i2s_t* reg) { return (reg->STATUS >> 1) & 0x1; }
static inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg) { return (reg->STATUS >> 2) & 0x1; }
static inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg) { return (reg->STATUS >> 3) & 0x1; }
static inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 4) & 0x1; }
static inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
}
static inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg) { return (reg->STATUS >> 5) & 0x1; }
static inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value) {
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
} }
// I2S_I2S_CLOCK_CTRL //I2S_CONTROL
static inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg) { return reg->I2S_CLOCK_CTRL; } inline uint32_t get_i2s_control(volatile i2s_t* reg){
static inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->I2S_CLOCK_CTRL = value; } return reg->CONTROL;
static inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff; } }
static inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value) { inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0); reg->CONTROL = value;
}
inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
return (reg->CONTROL >> 0) & 0x3;
}
inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
}
inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
return (reg->CONTROL >> 2) & 0x1;
}
inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
return (reg->CONTROL >> 3) & 0x1;
}
inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
}
inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
return (reg->CONTROL >> 4) & 0x1;
}
inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
return (reg->CONTROL >> 5) & 0x3;
}
inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
return (reg->CONTROL >> 7) & 0x7;
}
inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
} }
// I2S_PDM_CLOCK_CTRL //I2S_STATUS
static inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg) { return reg->PDM_CLOCK_CTRL; } inline uint32_t get_i2s_status(volatile i2s_t* reg){
static inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_CLOCK_CTRL = value; } return reg->STATUS;
static inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg) { return (reg->PDM_CLOCK_CTRL >> 0) & 0xff; } }
static inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value) { inline void set_i2s_status(volatile i2s_t* reg, uint32_t value){
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0); reg->STATUS = value;
}
inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
return (reg->STATUS >> 2) & 0x1;
}
inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
return (reg->STATUS >> 3) & 0x1;
}
inline uint32_t get_i2s_status_left_overflow(volatile i2s_t* reg){
return (reg->STATUS >> 4) & 0x1;
}
inline void set_i2s_status_left_overflow(volatile i2s_t* reg, uint8_t value){
reg->STATUS = (reg->STATUS & ~(0x1U << 4)) | (value << 4);
}
inline uint32_t get_i2s_status_right_overflow(volatile i2s_t* reg){
return (reg->STATUS >> 5) & 0x1;
}
inline void set_i2s_status_right_overflow(volatile i2s_t* reg, uint8_t value){
reg->STATUS = (reg->STATUS & ~(0x1U << 5)) | (value << 5);
} }
// I2S_PDM_FILTER_CTRL //I2S_I2S_CLOCK_CTRL
static inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg) { return reg->PDM_FILTER_CTRL; } inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
static inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value) { reg->PDM_FILTER_CTRL = value; } return reg->I2S_CLOCK_CTRL;
static inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg) { return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff; } }
static inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value) { inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0); reg->I2S_CLOCK_CTRL = value;
}
inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
}
inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
} }
// I2S_IE //I2S_PDM_CLOCK_CTRL
static inline uint32_t get_i2s_ie(volatile i2s_t* reg) { return reg->IE; } inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
static inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value) { reg->IE = value; } return reg->PDM_CLOCK_CTRL;
static inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 0) & 0x1; }
static inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value) {
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg) { return (reg->IE >> 1) & 0x1; } inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
static inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value) { reg->PDM_CLOCK_CTRL = value;
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1); }
inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
return (reg->PDM_CLOCK_CTRL >> 0) & 0xff;
}
inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint8_t value){
reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0xffU << 0)) | (value << 0);
} }
// I2S_IP //I2S_PDM_FILTER_CTRL
static inline uint32_t get_i2s_ip(volatile i2s_t* reg) { return reg->IP; } inline uint32_t get_i2s_pdm_filter_ctrl(volatile i2s_t* reg){
static inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 0) & 0x1; } return reg->PDM_FILTER_CTRL;
static inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg) { return (reg->IP >> 1) & 0x1; } }
inline void set_i2s_pdm_filter_ctrl(volatile i2s_t* reg, uint32_t value){
reg->PDM_FILTER_CTRL = value;
}
inline uint32_t get_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg){
return (reg->PDM_FILTER_CTRL >> 0) & 0x3ff;
}
inline void set_i2s_pdm_filter_ctrl_decimationFactor(volatile i2s_t* reg, uint16_t value){
reg->PDM_FILTER_CTRL = (reg->PDM_FILTER_CTRL & ~(0x3ffU << 0)) | (value << 0);
}
//I2S_IE
inline uint32_t get_i2s_ie(volatile i2s_t* reg){
return reg->IE;
}
inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
reg->IE = value;
}
inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 0) & 0x1;
}
inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
return (reg->IE >> 1) & 0x1;
}
inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
}
//I2S_IP
inline uint32_t get_i2s_ip(volatile i2s_t* reg){
return reg->IP;
}
inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 0) & 0x1;
}
inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
return (reg->IP >> 1) & 0x1;
}
#endif /* _BSP_I2S_H */ #endif /* _BSP_I2S_H */

91
include/ehrenberg/devices/gen/mkcontrolclusterstreamcontroller.h
View File

@ -3,7 +3,7 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2025-05-05 14:06:05 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
@ -34,23 +34,19 @@ typedef struct {
volatile uint32_t REG_PAYLOAD_12; volatile uint32_t REG_PAYLOAD_12;
volatile uint32_t REG_PAYLOAD_13; volatile uint32_t REG_PAYLOAD_13;
volatile uint32_t REG_PAYLOAD_14; volatile uint32_t REG_PAYLOAD_14;
volatile uint32_t REG_PAYLOAD_15; }mkcontrolclusterstreamcontroller_t;
} mkcontrolclusterstreamcontroller_t;
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK 0x1
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) \ #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) \ #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_ID_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS 4
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) \ #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_MESSAGE_LENGTH_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_OFFS 8
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7 #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
@ -136,155 +132,146 @@ typedef struct {
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS) #define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14_OFFS)
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS 0
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK 0xffffffff
#define MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15(V) ((V & MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_MASK) << MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15_OFFS)
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_SEND
static inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_SEND = value; reg->REG_SEND = value;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_SEND_SEND(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0); reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_HEADER
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg){
return reg->REG_HEADER; return reg->REG_HEADER;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_HEADER(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_HEADER = value; reg->REG_HEADER = value;
} }
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
return (reg->REG_HEADER >> 0) & 0xf; return (reg->REG_HEADER >> 0) & 0xf;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_ID(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0); reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 0)) | (value << 0);
} }
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg){
return (reg->REG_HEADER >> 4) & 0xf; return (reg->REG_HEADER >> 4) & 0xf;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_MESSAGE_LENGTH(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4); reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 4)) | (value << 4);
} }
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg){
return (reg->REG_HEADER >> 8) & 0x7; return (reg->REG_HEADER >> 8) & 0x7;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_COMPONENT(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8); reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 8)) | (value << 8);
} }
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg){
return (reg->REG_HEADER >> 11) & 0x3; return (reg->REG_HEADER >> 11) & 0x3;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_HEADER_RECIPIENT_CLUSTER(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11); reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 11)) | (value << 11);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_ACK
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg){
return reg->REG_ACK; return reg->REG_ACK;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_ACK = value; reg->REG_ACK = value;
} }
static inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_ACK_ACK(volatile mkcontrolclusterstreamcontroller_t* reg, uint8_t value){
reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0); reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_ACK_PENDING_RESPONSE(volatile mkcontrolclusterstreamcontroller_t* reg){
return (reg->REG_ACK >> 1) & 0x1; return (reg->REG_ACK >> 1) & 0x1;
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_ID
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
return reg->REG_RECV_ID; return reg->REG_RECV_ID;
} }
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_ID_RECV_ID(volatile mkcontrolclusterstreamcontroller_t* reg){
return (reg->REG_RECV_ID >> 0) & 0xf; return (reg->REG_RECV_ID >> 0) & 0xf;
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_RECV_PAYLOAD
static inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg) { inline uint32_t get_mkcontrolclusterstreamcontroller_REG_RECV_PAYLOAD(volatile mkcontrolclusterstreamcontroller_t* reg){
return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff; return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_0
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_0(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_1
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_1(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_2
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_2(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_3
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_3(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_4
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_4(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_5
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_5(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_6
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_6(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_7
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_7(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_8
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_8(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_8 = (reg->REG_PAYLOAD_8 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_9
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_9(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_9 = (reg->REG_PAYLOAD_9 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_10
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_10(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_10 = (reg->REG_PAYLOAD_10 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_11
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_11(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_11 = (reg->REG_PAYLOAD_11 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_12
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_12(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_12 = (reg->REG_PAYLOAD_12 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_13
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_13(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_13 = (reg->REG_PAYLOAD_13 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14 //MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_14
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) { inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_14(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value){
reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0); reg->REG_PAYLOAD_14 = (reg->REG_PAYLOAD_14 & ~(0xffffffffU << 0)) | (value << 0);
} }
//MKCONTROLCLUSTERSTREAMCONTROLLER_REG_PAYLOAD_15
static inline void set_mkcontrolclusterstreamcontroller_REG_PAYLOAD_15(volatile mkcontrolclusterstreamcontroller_t* reg, uint32_t value) {
reg->REG_PAYLOAD_15 = (reg->REG_PAYLOAD_15 & ~(0xffffffffU << 0)) | (value << 0);
}
#endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */ #endif /* _BSP_MKCONTROLCLUSTERSTREAMCONTROLLER_H */

22
include/ehrenberg/devices/gen/sysctrl.h
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@ -3,7 +3,7 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2025-06-23 15:39:49 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
@ -16,7 +16,6 @@ typedef struct {
volatile uint32_t SYSCTRL; volatile uint32_t SYSCTRL;
volatile uint32_t PLLCTRL; volatile uint32_t PLLCTRL;
volatile uint32_t AXI_BACKUP; volatile uint32_t AXI_BACKUP;
volatile uint32_t FMCDIV;
}sysctrl_t; }sysctrl_t;
#define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0 #define SYSCTRL_SYSCTRL_CC0_RESET_OFFS 0
@ -51,14 +50,6 @@ typedef struct {
#define SYSCTRL_AXI_BACKUP_MASK 0x1f #define SYSCTRL_AXI_BACKUP_MASK 0x1f
#define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS) #define SYSCTRL_AXI_BACKUP(V) ((V & SYSCTRL_AXI_BACKUP_MASK) << SYSCTRL_AXI_BACKUP_OFFS)
#define SYSCTRL_FMCDIV_FMCDIVVALID_OFFS 0
#define SYSCTRL_FMCDIV_FMCDIVVALID_MASK 0x1
#define SYSCTRL_FMCDIV_FMCDIVVALID(V) ((V & SYSCTRL_FMCDIV_FMCDIVVALID_MASK) << SYSCTRL_FMCDIV_FMCDIVVALID_OFFS)
#define SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS 1
#define SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK 0xf
#define SYSCTRL_FMCDIV_FMCDIVFACTOR(V) ((V & SYSCTRL_FMCDIV_FMCDIVFACTOR_MASK) << SYSCTRL_FMCDIV_FMCDIVFACTOR_OFFS)
//SYSCTRL_SYSCTRL //SYSCTRL_SYSCTRL
inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){ inline uint32_t get_sysctrl_sysctrl(volatile sysctrl_t* reg){
return reg->SYSCTRL; return reg->SYSCTRL;
@ -128,15 +119,4 @@ inline void set_sysctrl_axi_backup_page(volatile sysctrl_t* reg, uint8_t value){
reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0); reg->AXI_BACKUP = (reg->AXI_BACKUP & ~(0x1fU << 0)) | (value << 0);
} }
//SYSCTRL_FMCDIV
inline void set_sysctrl_fmcdiv(volatile sysctrl_t* reg, uint32_t value){
reg->FMCDIV = value;
}
inline void set_sysctrl_fmcdiv_fmcDivValid(volatile sysctrl_t* reg, uint8_t value){
reg->FMCDIV = (reg->FMCDIV & ~(0x1U << 0)) | (value << 0);
}
inline void set_sysctrl_fmcdiv_fmcDivFactor(volatile sysctrl_t* reg, uint8_t value){
reg->FMCDIV = (reg->FMCDIV & ~(0xfU << 1)) | (value << 1);
}
#endif /* _BSP_SYSCTRL_H */ #endif /* _BSP_SYSCTRL_H */

136
include/ehrenberg/devices/gen/timercounter.h
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@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-12-26 18:07:07 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.9 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_TIMERCOUNTER_H #ifndef _BSP_TIMERCOUNTER_H
#define _BSP_TIMERCOUNTER_H #define _BSP_TIMERCOUNTER_H
@ -13,14 +13,14 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t PRESCALER; volatile uint32_t PRESCALER;
volatile uint32_t T0_CTRL; volatile uint32_t T0_CTRL;
volatile uint32_t T0_OVERFLOW; volatile uint32_t T0_OVERFLOW;
volatile uint32_t T0_COUNTER; volatile uint32_t T0_COUNTER;
volatile uint32_t T1_CTRL; volatile uint32_t T1_CTRL;
volatile uint32_t T1_OVERFLOW; volatile uint32_t T1_OVERFLOW;
volatile uint32_t T1_COUNTER; volatile uint32_t T1_COUNTER;
} timercounter_t; }timercounter_t;
#define TIMERCOUNTER_PRESCALER_OFFS 0 #define TIMERCOUNTER_PRESCALER_OFFS 0
#define TIMERCOUNTER_PRESCALER_MASK 0xffff #define TIMERCOUNTER_PRESCALER_MASK 0xffff
@ -58,54 +58,84 @@ typedef struct {
#define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff #define TIMERCOUNTER_T1_COUNTER_MASK 0xffffffff
#define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS) #define TIMERCOUNTER_T1_COUNTER(V) ((V & TIMERCOUNTER_T1_COUNTER_MASK) << TIMERCOUNTER_T1_COUNTER_OFFS)
// TIMERCOUNTER_PRESCALER //TIMERCOUNTER_PRESCALER
static inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg) { return reg->PRESCALER; } inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
static inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value) { reg->PRESCALER = value; } return reg->PRESCALER;
static inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg) { return (reg->PRESCALER >> 0) & 0xffff; } }
static inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value) { inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0); reg->PRESCALER = value;
}
inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
return (reg->PRESCALER >> 0) & 0xffff;
}
inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
} }
// TIMERCOUNTER_T0_CTRL //TIMERCOUNTER_T0_CTRL
static inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg) { return reg->T0_CTRL; } inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){
static inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T0_CTRL = value; } return reg->T0_CTRL;
static inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
} }
static inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg) { return (reg->T0_CTRL >> 3) & 0x3; } inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){
static inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value) { reg->T0_CTRL = value;
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3); }
inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){
return (reg->T0_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
} }
// TIMERCOUNTER_T0_OVERFLOW //TIMERCOUNTER_T0_OVERFLOW
static inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff; } inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){
static inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value) { return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
} }
// TIMERCOUNTER_T0_COUNTER //TIMERCOUNTER_T0_COUNTER
static inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg) { return (reg->T0_COUNTER >> 0) & 0xffffffff; } inline uint32_t get_timercounter_t0_counter(volatile timercounter_t* reg){
return (reg->T0_COUNTER >> 0) & 0xffffffff;
// TIMERCOUNTER_T1_CTRL
static inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg) { return reg->T1_CTRL; }
static inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value) { reg->T1_CTRL = value; }
static inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 0) & 0x7; }
static inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
static inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg) { return (reg->T1_CTRL >> 3) & 0x3; }
static inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value) {
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
} }
// TIMERCOUNTER_T1_OVERFLOW //TIMERCOUNTER_T1_CTRL
static inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg) { return (reg->T1_OVERFLOW >> 0) & 0xffffffff; } inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){
static inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value) { return reg->T1_CTRL;
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0); }
inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){
reg->T1_CTRL = value;
}
inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 0) & 0x7;
}
inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){
return (reg->T1_CTRL >> 3) & 0x3;
}
inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
} }
// TIMERCOUNTER_T1_COUNTER //TIMERCOUNTER_T1_OVERFLOW
static inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg) { return (reg->T1_COUNTER >> 0) & 0xffffffff; } inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
}
inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
}
//TIMERCOUNTER_T1_COUNTER
inline uint32_t get_timercounter_t1_counter(volatile timercounter_t* reg){
return (reg->T1_COUNTER >> 0) & 0xffffffff;
}
#endif /* _BSP_TIMERCOUNTER_H */ #endif /* _BSP_TIMERCOUNTER_H */

253
include/ehrenberg/devices/gen/uart.h
View File

@ -1,11 +1,11 @@
/* /*
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH * Copyright (c) 2023 - 2025 MINRES Technologies GmbH
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-08-02 08:46:07 UTC * Generated at 2025-07-01 11:20:43 UTC
* by peakrdl_mnrs version 1.2.7 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_UART_H #ifndef _BSP_UART_H
#define _BSP_UART_H #define _BSP_UART_H
@ -13,28 +13,16 @@
#include <stdint.h> #include <stdint.h>
typedef struct { typedef struct {
volatile uint32_t RX_TX_REG; volatile uint32_t RX_TX_REG;
volatile uint32_t INT_CTRL_REG; volatile uint32_t INT_CTRL_REG;
volatile uint32_t CLK_DIVIDER_REG; volatile uint32_t CLK_DIVIDER_REG;
volatile uint32_t FRAME_CONFIG_REG; volatile uint32_t FRAME_CONFIG_REG;
volatile uint32_t STATUS_REG; volatile uint32_t STATUS_REG;
} uart_t; }uart_t;
#define UART_RX_TX_REG_DATA_OFFS 0 #define UART_RX_TX_REG_OFFS 0
#define UART_RX_TX_REG_DATA_MASK 0xff #define UART_RX_TX_REG_MASK 0xff
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS) #define UART_RX_TX_REG(V) ((V & UART_RX_TX_REG_MASK) << UART_RX_TX_REG_OFFS)
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
#define UART_RX_TX_REG_TX_FREE_OFFS 15
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0 #define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1 #define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
@ -76,101 +64,176 @@ typedef struct {
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1 #define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS) #define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
#define UART_STATUS_REG_READ_ERROR_OFFS 0 #define UART_STATUS_REG_RX_AVAIL_OFFS 0
#define UART_STATUS_REG_RX_AVAIL_MASK 0x1
#define UART_STATUS_REG_RX_AVAIL(V) ((V & UART_STATUS_REG_RX_AVAIL_MASK) << UART_STATUS_REG_RX_AVAIL_OFFS)
#define UART_STATUS_REG_TX_FREE_OFFS 1
#define UART_STATUS_REG_TX_FREE_MASK 0x1
#define UART_STATUS_REG_TX_FREE(V) ((V & UART_STATUS_REG_TX_FREE_MASK) << UART_STATUS_REG_TX_FREE_OFFS)
#define UART_STATUS_REG_TX_EMPTY_OFFS 2
#define UART_STATUS_REG_TX_EMPTY_MASK 0x1
#define UART_STATUS_REG_TX_EMPTY(V) ((V & UART_STATUS_REG_TX_EMPTY_MASK) << UART_STATUS_REG_TX_EMPTY_OFFS)
#define UART_STATUS_REG_READ_ERROR_OFFS 8
#define UART_STATUS_REG_READ_ERROR_MASK 0x1 #define UART_STATUS_REG_READ_ERROR_MASK 0x1
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS) #define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
#define UART_STATUS_REG_STALL_OFFS 1 #define UART_STATUS_REG_STALL_OFFS 9
#define UART_STATUS_REG_STALL_MASK 0x1 #define UART_STATUS_REG_STALL_MASK 0x1
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS) #define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
#define UART_STATUS_REG_BREAK_LINE_OFFS 8 #define UART_STATUS_REG_BREAK_LINE_OFFS 16
#define UART_STATUS_REG_BREAK_LINE_MASK 0x1 #define UART_STATUS_REG_BREAK_LINE_MASK 0x1
#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS) #define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9 #define UART_STATUS_REG_BREAK_DETECTED_OFFS 17
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1 #define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS) #define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
#define UART_STATUS_REG_SET_BREAK_OFFS 10 #define UART_STATUS_REG_SET_BREAK_OFFS 18
#define UART_STATUS_REG_SET_BREAK_MASK 0x1 #define UART_STATUS_REG_SET_BREAK_MASK 0x1
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS) #define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11 #define UART_STATUS_REG_CLEAR_BREAK_OFFS 19
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1 #define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS) #define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
// UART_RX_TX_REG //UART_RX_TX_REG
static inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg) { return reg->RX_TX_REG; } inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
static inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value) { reg->RX_TX_REG = value; } return reg->RX_TX_REG;
static inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg) { return (reg->RX_TX_REG >> 0) & 0xff; }
static inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value) {
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
} }
static inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg) { return (reg->RX_TX_REG >> 14) & 0x1; } inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
static inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg) { return (reg->RX_TX_REG >> 15) & 0x1; } reg->RX_TX_REG = value;
static inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg) { return (reg->RX_TX_REG >> 16) & 0x1; }
// UART_INT_CTRL_REG
static inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg) { return reg->INT_CTRL_REG; }
static inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value) { reg->INT_CTRL_REG = value; }
static inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 0) & 0x1; }
static inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value) {
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
} }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 1) & 0x1; } inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
static inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value) { return (reg->RX_TX_REG >> 0) & 0xff;
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
} }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 2) & 0x1; } inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
static inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value) { reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
static inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 8) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 9) & 0x1; }
static inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg) { return (reg->INT_CTRL_REG >> 10) & 0x1; }
// UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg) { return reg->CLK_DIVIDER_REG; }
static inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value) { reg->CLK_DIVIDER_REG = value; }
static inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff; }
static inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value) {
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
} }
// UART_FRAME_CONFIG_REG //UART_INT_CTRL_REG
static inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg) { return reg->FRAME_CONFIG_REG; } inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
static inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value) { reg->FRAME_CONFIG_REG = value; } return reg->INT_CTRL_REG;
static inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 0) & 0x7; }
static inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value) {
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
} }
static inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 3) & 0x3; } inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
static inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value) { reg->INT_CTRL_REG = value;
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
} }
static inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg) { return (reg->FRAME_CONFIG_REG >> 5) & 0x1; } inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
static inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value) { return (reg->INT_CTRL_REG >> 0) & 0x1;
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5); }
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 1) & 0x1;
}
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 2) & 0x1;
}
inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
}
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 8) & 0x1;
}
inline void set_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg, uint8_t value){
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 8)) | (value << 8);
}
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 9) & 0x1;
}
inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
return (reg->INT_CTRL_REG >> 10) & 0x1;
} }
// UART_STATUS_REG //UART_CLK_DIVIDER_REG
static inline uint32_t get_uart_status_reg(volatile uart_t* reg) { return reg->STATUS_REG; } inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
static inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value) { reg->STATUS_REG = value; } return reg->CLK_DIVIDER_REG;
static inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg) { return (reg->STATUS_REG >> 0) & 0x1; }
static inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg) { return (reg->STATUS_REG >> 1) & 0x1; }
static inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg) { return (reg->STATUS_REG >> 8) & 0x1; }
static inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg) { return (reg->STATUS_REG >> 9) & 0x1; }
static inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value) {
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
} }
static inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 10) & 0x1; } inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
static inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value) { reg->CLK_DIVIDER_REG = value;
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
} }
static inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg) { return (reg->STATUS_REG >> 11) & 0x1; } inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
static inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value) { return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11); }
inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
} }
#endif /* _BSP_UART_H */ //UART_FRAME_CONFIG_REG
inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
return reg->FRAME_CONFIG_REG;
}
inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
reg->FRAME_CONFIG_REG = value;
}
inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
}
inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
}
inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
}
inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
}
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
}
inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
}
//UART_STATUS_REG
inline uint32_t get_uart_status_reg(volatile uart_t* reg){
return reg->STATUS_REG;
}
inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
reg->STATUS_REG = value;
}
inline uint32_t get_uart_status_reg_rx_avail(volatile uart_t* reg){
return (reg->STATUS_REG >> 0) & 0x1;
}
inline uint32_t get_uart_status_reg_tx_free(volatile uart_t* reg){
return (reg->STATUS_REG >> 1) & 0x1;
}
inline uint32_t get_uart_status_reg_tx_empty(volatile uart_t* reg){
return (reg->STATUS_REG >> 2) & 0x1;
}
inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
return (reg->STATUS_REG >> 8) & 0x1;
}
inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
return (reg->STATUS_REG >> 9) & 0x1;
}
inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
return (reg->STATUS_REG >> 16) & 0x1;
}
inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
return (reg->STATUS_REG >> 17) & 0x1;
}
inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 17)) | (value << 17);
}
inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 18) & 0x1;
}
inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 18)) | (value << 18);
}
inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
return (reg->STATUS_REG >> 19) & 0x1;
}
inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 19)) | (value << 19);
}
#endif /* _BSP_UART_H */

8
include/ehrenberg/devices/uart.h
View File

@ -5,19 +5,19 @@
#include "gen/uart.h" #include "gen/uart.h"
static inline uint32_t uart_get_tx_free(volatile uart_t* reg){ static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
return get_uart_rx_tx_reg_tx_free(reg); return get_uart_status_reg_tx_free(reg);
} }
static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){ static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
return get_uart_rx_tx_reg_tx_empty(reg); return get_uart_status_reg_tx_empty(reg);
} }
static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){ static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
return get_uart_rx_tx_reg_rx_avail(reg); return get_uart_status_reg_rx_avail(reg);
} }
static inline void uart_write(volatile uart_t* reg, uint8_t data){ static inline void uart_write(volatile uart_t* reg, uint8_t data){
while(get_uart_rx_tx_reg_tx_free(reg) == 0); while(get_uart_status_reg_tx_free(reg) == 0);
set_uart_rx_tx_reg_data(reg, data); set_uart_rx_tx_reg_data(reg, data);
} }

2
libwrap/sys/puts.c
View File

@ -19,7 +19,7 @@ int __wrap_puts(const char *s) {
#endif #endif
while (*s != '\0') { while (*s != '\0') {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp) #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart) == 0) while (get_uart_status_reg_tx_free(uart) == 0)
; ;
uart_write(uart, *s); uart_write(uart, *s);
#elif defined(BOARD_iss) #elif defined(BOARD_iss)

2
libwrap/sys/read.c
View File

@ -35,7 +35,7 @@ ssize_t __wrap_read(int fd, void *ptr, size_t len) {
if (isatty(fd)) { if (isatty(fd)) {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp) #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) && for (current = (uint8_t *)ptr; (current < ((uint8_t *)ptr) + len) &&
(get_uart_rx_tx_reg_rx_avail(uart) > 0); (get_uart_status_reg_rx_avail(uart) > 0);
current++) { current++) {
*current = uart_read(uart); *current = uart_read(uart);
result++; result++;

4
libwrap/sys/write.c
View File

@ -40,11 +40,11 @@ ssize_t __wrap_write(int fd, const void *ptr, size_t len) {
if (isatty(fd)) { if (isatty(fd)) {
for (size_t jj = 0; jj < len; jj++) { for (size_t jj = 0; jj < len; jj++) {
#if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp) #if defined(BOARD_ehrenberg) || defined(BOARD_tgc_vp)
while (get_uart_rx_tx_reg_tx_free(uart) == 0) while (get_uart_status_reg_tx_free(uart) == 0)
; ;
uart_write(uart, current[jj]); uart_write(uart, current[jj]);
if (current[jj] == '\n') { if (current[jj] == '\n') {
while (get_uart_rx_tx_reg_tx_free(uart) == 0) while (get_uart_status_reg_tx_free(uart) == 0)
; ;
uart_write(uart, '\r'); uart_write(uart, '\r');
} }