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updates gpio registers

This commit is contained in:
Eyck Jentzsch 2024-08-09 14:20:00 +02:00
parent 785cf20e8e
commit d621264ef7
1 changed files with 67 additions and 2 deletions
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69
include/ehrenberg/devices/gen/gpio.h
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@ -3,8 +3,8 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-08-02 08:46:07 UTC * Generated at 2024-08-09 14:18:51 UTC
* by peakrdl_mnrs version 1.2.7 * by peakrdl_mnrs version 1.2.8
*/ */
#ifndef _BSP_GPIO_H #ifndef _BSP_GPIO_H
@ -16,6 +16,11 @@ typedef struct __attribute((__packed__)) {
volatile uint32_t VALUE; volatile uint32_t VALUE;
volatile uint32_t WRITE; volatile uint32_t WRITE;
volatile uint32_t WRITEENABLE; volatile uint32_t WRITEENABLE;
volatile uint32_t IE;
volatile uint32_t IP;
volatile uint32_t IRQ_TRIGGER;
volatile uint32_t IRQ_TYPE;
volatile uint32_t BOOT_SEL;
}gpio_t; }gpio_t;
#define GPIO_VALUE_OFFS 0 #define GPIO_VALUE_OFFS 0
@ -30,6 +35,26 @@ typedef struct __attribute((__packed__)) {
#define GPIO_WRITEENABLE_MASK 0xffffffff #define GPIO_WRITEENABLE_MASK 0xffffffff
#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS) #define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
#define GPIO_IE_OFFS 0
#define GPIO_IE_MASK 0xffffffff
#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
#define GPIO_IP_OFFS 0
#define GPIO_IP_MASK 0xffffffff
#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
#define GPIO_IRQ_TRIGGER_OFFS 0
#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
#define GPIO_IRQ_TYPE_OFFS 0
#define GPIO_IRQ_TYPE_MASK 0xffffffff
#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
#define GPIO_BOOT_SEL_OFFS 0
#define GPIO_BOOT_SEL_MASK 0x7
#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
//GPIO_VALUE //GPIO_VALUE
inline uint32_t get_gpio_value(volatile gpio_t* reg){ inline uint32_t get_gpio_value(volatile gpio_t* reg){
return (reg->VALUE >> 0) & 0xffffffff; return (reg->VALUE >> 0) & 0xffffffff;
@ -51,4 +76,44 @@ inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0); reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
} }
//GPIO_IE
inline uint32_t get_gpio_ie(volatile gpio_t* reg){
return (reg->IE >> 0) & 0xffffffff;
}
inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IP
inline uint32_t get_gpio_ip(volatile gpio_t* reg){
return (reg->IP >> 0) & 0xffffffff;
}
inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IRQ_TRIGGER
inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){
return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
}
inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_IRQ_TYPE
inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){
return (reg->IRQ_TYPE >> 0) & 0xffffffff;
}
inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
}
//GPIO_BOOT_SEL
inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){
return reg->BOOT_SEL;
}
inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
return (reg->BOOT_SEL >> 0) & 0x7;
}
#endif /* _BSP_GPIO_H */ #endif /* _BSP_GPIO_H */