Firmware/MNRS-BM-BSP
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adds mask for ssid number

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Eyck Jentzsch 2025-04-06 19:36:37 +02:00
parent 39969f0e29
commit c88caf9906
1 changed files with 53 additions and 45 deletions
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98
include/ehrenberg/devices/qspi.h
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@ -1,18 +1,18 @@
#ifndef _DEVICES_QSPI_H #ifndef _DEVICES_QSPI_H
#define _DEVICES_QSPI_H #define _DEVICES_QSPI_H
#include <stdint.h>
#include "gen/apb3spi.h" #include "gen/apb3spi.h"
#include <stdint.h>
#define qspi_t apb3spi_t #define qspi_t apb3spi_t
typedef struct { typedef struct {
uint32_t cpol; uint32_t cpol;
uint32_t cpha; uint32_t cpha;
uint32_t mode; uint32_t mode;
uint32_t clkDivider; uint32_t clkDivider;
uint32_t ssSetup; uint32_t ssSetup;
uint32_t ssHold; uint32_t ssHold;
uint32_t ssDisable; uint32_t ssDisable;
} spi_cfg; } spi_cfg;
#define SPI_CMD_WRITE (1 << 8) #define SPI_CMD_WRITE (1 << 8)
@ -26,57 +26,65 @@ typedef struct {
#define SPI_STATUS_CMD_INT_FLAG = (1 << 8) #define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
#define SPI_STATUS_RSP_INT_FLAG = (1 << 9) #define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
static inline void spi_configure(volatile qspi_t* qspi, spi_cfg *config){ static inline void spi_configure(volatile qspi_t *qspi, spi_cfg *config) {
set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4)); set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) |
set_apb3spi_sclk_config(qspi, config->clkDivider); (config->mode << 4));
set_apb3spi_ssgen_setup(qspi, config->ssSetup); set_apb3spi_sclk_config(qspi, config->clkDivider);
set_apb3spi_ssgen_hold(qspi, config->ssHold); set_apb3spi_ssgen_setup(qspi, config->ssSetup);
set_apb3spi_ssgen_disable(qspi, config->ssDisable); set_apb3spi_ssgen_hold(qspi, config->ssHold);
set_apb3spi_ssgen_disable(qspi, config->ssDisable);
} }
static inline void spi_init(volatile qspi_t* spi){ static inline void spi_init(volatile qspi_t *spi) {
spi_cfg spiCfg; spi_cfg spiCfg;
spiCfg.cpol = 0; spiCfg.cpol = 0;
spiCfg.cpha = 0; spiCfg.cpha = 0;
spiCfg.mode = 0; spiCfg.mode = 0;
spiCfg.clkDivider = 2; spiCfg.clkDivider = 2;
spiCfg.ssSetup = 2; spiCfg.ssSetup = 2;
spiCfg.ssHold = 2; spiCfg.ssHold = 2;
spiCfg.ssDisable = 2; spiCfg.ssDisable = 2;
spi_configure(spi, &spiCfg); spi_configure(spi, &spiCfg);
} }
static inline uint32_t spi_cmd_avail(volatile qspi_t* qspi){ static inline uint32_t spi_cmd_avail(volatile qspi_t *qspi) {
return qspi->STATUS & 0xFFFF; return qspi->STATUS & 0xFFFF;
} }
static inline uint32_t spi_rsp_occupied(volatile qspi_t* qspi){ static inline uint32_t spi_rsp_occupied(volatile qspi_t *qspi) {
return qspi->STATUS >> 16; return qspi->STATUS >> 16;
} }
static inline void spi_write(volatile qspi_t* qspi, uint8_t data){ static inline void spi_write(volatile qspi_t *qspi, uint8_t data) {
while(spi_cmd_avail(qspi) == 0); while (spi_cmd_avail(qspi) == 0)
qspi->DATA = data | SPI_CMD_WRITE; ;
qspi->DATA = data | SPI_CMD_WRITE;
} }
static inline uint8_t spi_read(volatile qspi_t* qspi){ static inline uint8_t spi_read(volatile qspi_t *qspi) {
while(spi_cmd_avail(qspi) == 0); while (spi_cmd_avail(qspi) == 0)
qspi->DATA = SPI_CMD_READ; ;
while(spi_rsp_occupied(qspi) == 0); qspi->DATA = SPI_CMD_READ;
while((qspi->DATA & 0x80000000)==0); while (spi_rsp_occupied(qspi) == 0)
return qspi->DATA; ;
while ((qspi->DATA & 0x80000000) == 0)
;
return qspi->DATA;
} }
static inline void spi_select(volatile qspi_t* qspi, uint32_t slaveId){ static inline void spi_select(volatile qspi_t *qspi, uint32_t slaveId) {
while(spi_cmd_avail(qspi) == 0); while (spi_cmd_avail(qspi) == 0)
qspi->DATA = slaveId | 0x80 | SPI_CMD_SS; ;
qspi->DATA = (slaveId & 0x3) | 0x80 | SPI_CMD_SS;
} }
static inline void spi_deselect(volatile qspi_t* qspi, uint32_t slaveId){ static inline void spi_deselect(volatile qspi_t *qspi, uint32_t slaveId) {
while(spi_cmd_avail(qspi) == 0); while (spi_cmd_avail(qspi) == 0)
qspi->DATA = slaveId | SPI_CMD_SS; ;
qspi->DATA = (slaveId & 0x3) | SPI_CMD_SS;
} }
static inline void spi_wait_tx_idle(volatile qspi_t* qspi){ static inline void spi_wait_tx_idle(volatile qspi_t *qspi) {
while(spi_cmd_avail(qspi) < 0x20); while (spi_cmd_avail(qspi) < 0x20)
;
} }
#endif /* _DEVICES_QSPI_H */ #endif /* _DEVICES_QSPI_H */