adds improved firmware headers for peripherals
This commit is contained in:
parent
7218dcfa69
commit
baddcf17af
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@ -3,8 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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* Generated at 2024-03-28 09:32:44 UTC
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* by peakrdl_mnrs version 1.2.4
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*/
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#ifndef _BSP_APB3ACLINT_H
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@ -14,40 +14,72 @@
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typedef struct __attribute((__packed__)) {
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volatile uint32_t MSIP0;
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uint8_t fill0 [16380];
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volatile uint32_t MTIMECMP0LO;
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volatile uint32_t MTIMECMP0HI;
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uint8_t fill0 [32752];
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volatile uint32_t MTIME_LO;
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volatile uint32_t MTIME_HI;
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}apb3aclint_t;
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inline uint32_t get_aclint_msip0(volatile apb3aclint_t *reg){
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#define ACLINT_MSIP0_OFFS 0
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#define ACLINT_MSIP0_MASK 0x1
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#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
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#define ACLINT_MTIMECMP0LO_OFFS 0
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#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
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#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
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#define ACLINT_MTIMECMP0HI_OFFS 0
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#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
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#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
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#define ACLINT_MTIME_LO_OFFS 0
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#define ACLINT_MTIME_LO_MASK 0xffffffff
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#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
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#define ACLINT_MTIME_HI_OFFS 0
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#define ACLINT_MTIME_HI_MASK 0xffffffff
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#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
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//ACLINT_MSIP0
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inline uint32_t get_aclint_msip0(volatile apb3aclint_t* reg){
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return (reg->MSIP0 >> 0) & 0x1;
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}
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inline void set_aclint_msip0(volatile apb3aclint_t *reg, uint8_t value){
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inline void set_aclint_msip0(volatile apb3aclint_t* reg, uint8_t value){
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reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t *reg){
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//ACLINT_MTIMECMP0LO
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inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t* reg){
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return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t *reg, uint32_t value){
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inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t* reg, uint32_t value){
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reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t *reg){
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//ACLINT_MTIMECMP0HI
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inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t* reg){
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return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t *reg, uint32_t value){
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inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t* reg, uint32_t value){
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reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t *reg){
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//ACLINT_MTIME_LO
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inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t* reg){
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return (reg->MTIME_LO >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtime_lo(volatile apb3aclint_t *reg, uint32_t value){
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inline void set_aclint_mtime_lo(volatile apb3aclint_t* reg, uint32_t value){
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reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t *reg){
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//ACLINT_MTIME_HI
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inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t* reg){
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return (reg->MTIME_HI >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtime_hi(volatile apb3aclint_t *reg, uint32_t value){
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inline void set_aclint_mtime_hi(volatile apb3aclint_t* reg, uint32_t value){
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reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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#endif /* _BSP_APB3ACLINT_H */
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@ -3,8 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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* Generated at 2024-03-28 09:32:44 UTC
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* by peakrdl_mnrs version 1.2.4
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*/
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#ifndef _BSP_APB3GPIO_H
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@ -18,19 +18,37 @@ typedef struct __attribute((__packed__)) {
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volatile uint32_t WRITEENABLE;
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}apb3gpio_t;
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inline uint32_t get_gpio_value(volatile apb3gpio_t *reg){
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#define GPIO_VALUE_OFFS 0
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#define GPIO_VALUE_MASK 0xffffffff
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#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
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#define GPIO_WRITE_OFFS 0
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#define GPIO_WRITE_MASK 0xffffffff
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#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
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#define GPIO_WRITEENABLE_OFFS 0
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#define GPIO_WRITEENABLE_MASK 0xffffffff
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#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
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//GPIO_VALUE
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inline uint32_t get_gpio_value(volatile apb3gpio_t* reg){
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return (reg->VALUE >> 0) & 0xffffffff;
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}
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inline uint32_t get_gpio_write(volatile apb3gpio_t *reg){
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//GPIO_WRITE
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inline uint32_t get_gpio_write(volatile apb3gpio_t* reg){
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return (reg->WRITE >> 0) & 0xffffffff;
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}
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inline void set_gpio_write(volatile apb3gpio_t *reg, uint32_t value){
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inline void set_gpio_write(volatile apb3gpio_t* reg, uint32_t value){
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reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t *reg){
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//GPIO_WRITEENABLE
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inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t* reg){
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return (reg->WRITEENABLE >> 0) & 0xffffffff;
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}
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inline void set_gpio_writeEnable(volatile apb3gpio_t *reg, uint32_t value){
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inline void set_gpio_writeEnable(volatile apb3gpio_t* reg, uint32_t value){
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reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
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}
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#endif /* _BSP_APB3GPIO_H */
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@ -3,8 +3,8 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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* Generated at 2024-03-28 09:32:44 UTC
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* by peakrdl_mnrs version 1.2.4
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*/
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#ifndef _BSP_APB3IRQCTRL_H
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@ -17,16 +17,28 @@ typedef struct __attribute((__packed__)) {
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volatile uint32_t MASKSREG;
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}apb3irqctrl_t;
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inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t *reg){
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#define IRQ_PENDINGSREG_OFFS 0
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#define IRQ_PENDINGSREG_MASK 0xf
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#define IRQ_PENDINGSREG(V) ((V & IRQ_PENDINGSREG_MASK) << IRQ_PENDINGSREG_OFFS)
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#define IRQ_MASKSREG_OFFS 0
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#define IRQ_MASKSREG_MASK 0xf
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#define IRQ_MASKSREG(V) ((V & IRQ_MASKSREG_MASK) << IRQ_MASKSREG_OFFS)
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//IRQ_PENDINGSREG
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inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t* reg){
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return (reg->PENDINGSREG >> 0) & 0xf;
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}
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inline void set_irq_pendingsReg(volatile apb3irqctrl_t *reg, uint8_t value){
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inline void set_irq_pendingsReg(volatile apb3irqctrl_t* reg, uint8_t value){
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reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
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}
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inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t *reg){
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//IRQ_MASKSREG
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inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t* reg){
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return (reg->MASKSREG >> 0) & 0xf;
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}
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inline void set_irq_masksReg(volatile apb3irqctrl_t *reg, uint8_t value){
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inline void set_irq_masksReg(volatile apb3irqctrl_t* reg, uint8_t value){
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reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
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}
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#endif /* _BSP_APB3IRQCTRL_H */
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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* Generated at 2024-03-28 09:32:44 UTC
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* by peakrdl_mnrs version 1.2.4
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*/
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#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
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@ -17,28 +17,108 @@ typedef struct __attribute((__packed__)) {
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volatile uint32_t STATUS;
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volatile uint32_t CONFIG;
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volatile uint32_t INTR;
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uint32_t fill0[4];
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uint8_t fill0 [16];
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volatile uint32_t SCLK_CONFIG;
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volatile uint32_t SSGEN_SETUP;
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volatile uint32_t SSGEN_HOLD;
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volatile uint32_t SSGEN_DISABLE;
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volatile uint32_t SSGEN_ACTIVE_HIGH;
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uint32_t fill1[3];
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uint8_t fill0 [12];
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volatile uint32_t XIP_ENABLE;
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volatile uint32_t XIP_CONFIG;
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volatile uint32_t XIP_MODE;
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uint32_t fill2[1];
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uint8_t fill0 [4];
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volatile uint32_t XIP_WRITE;
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volatile uint32_t XIP_READ_WRITE;
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volatile uint32_t XIP_READ;
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}apb3spixdrmasterctrl_t;
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#define SPI_DATA_DATA_OFFS 0
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#define SPI_DATA_DATA_MASK 0xff
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#define SPI_DATA_DATA(V) ((V & SPI_DATA_DATA_MASK) << SPI_DATA_DATA_OFFS)
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#define SPI_DATA_WRITE_OFFS 8
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#define SPI_DATA_WRITE_MASK 0x1
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#define SPI_DATA_WRITE(V) ((V & SPI_DATA_WRITE_MASK) << SPI_DATA_WRITE_OFFS)
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#define SPI_DATA_READ_OFFS 9
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#define SPI_DATA_READ_MASK 0x1
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#define SPI_DATA_READ(V) ((V & SPI_DATA_READ_MASK) << SPI_DATA_READ_OFFS)
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#define SPI_DATA_KIND_OFFS 11
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#define SPI_DATA_KIND_MASK 0x1
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#define SPI_DATA_KIND(V) ((V & SPI_DATA_KIND_MASK) << SPI_DATA_KIND_OFFS)
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#define SPI_DATA_RX_DATA_INVALID_OFFS 31
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#define SPI_DATA_RX_DATA_INVALID_MASK 0x1
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#define SPI_DATA_RX_DATA_INVALID(V) ((V & SPI_DATA_RX_DATA_INVALID_MASK) << SPI_DATA_RX_DATA_INVALID_OFFS)
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#define SPI_STATUS_TX_FREE_OFFS 0
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#define SPI_STATUS_TX_FREE_MASK 0x3f
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#define SPI_STATUS_TX_FREE(V) ((V & SPI_STATUS_TX_FREE_MASK) << SPI_STATUS_TX_FREE_OFFS)
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#define SPI_STATUS_RX_AVAIL_OFFS 16
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#define SPI_STATUS_RX_AVAIL_MASK 0x3f
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#define SPI_STATUS_RX_AVAIL(V) ((V & SPI_STATUS_RX_AVAIL_MASK) << SPI_STATUS_RX_AVAIL_OFFS)
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#define SPI_CONFIG_KIND_OFFS 0
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#define SPI_CONFIG_KIND_MASK 0x3
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#define SPI_CONFIG_KIND(V) ((V & SPI_CONFIG_KIND_MASK) << SPI_CONFIG_KIND_OFFS)
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#define SPI_CONFIG_MODE_OFFS 4
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#define SPI_CONFIG_MODE_MASK 0x7
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#define SPI_CONFIG_MODE(V) ((V & SPI_CONFIG_MODE_MASK) << SPI_CONFIG_MODE_OFFS)
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#define SPI_INTR_TX_IE_OFFS 0
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#define SPI_INTR_TX_IE_MASK 0x1
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#define SPI_INTR_TX_IE(V) ((V & SPI_INTR_TX_IE_MASK) << SPI_INTR_TX_IE_OFFS)
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#define SPI_INTR_RX_IE_OFFS 1
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#define SPI_INTR_RX_IE_MASK 0x1
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#define SPI_INTR_RX_IE(V) ((V & SPI_INTR_RX_IE_MASK) << SPI_INTR_RX_IE_OFFS)
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#define SPI_INTR_TX_IP_OFFS 8
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#define SPI_INTR_TX_IP_MASK 0x1
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#define SPI_INTR_TX_IP(V) ((V & SPI_INTR_TX_IP_MASK) << SPI_INTR_TX_IP_OFFS)
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#define SPI_INTR_RX_IP_OFFS 9
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#define SPI_INTR_RX_IP_MASK 0x1
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#define SPI_INTR_RX_IP(V) ((V & SPI_INTR_RX_IP_MASK) << SPI_INTR_RX_IP_OFFS)
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#define SPI_INTR_TX_ACTIVE_OFFS 16
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#define SPI_INTR_TX_ACTIVE_MASK 0x1
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#define SPI_INTR_TX_ACTIVE(V) ((V & SPI_INTR_TX_ACTIVE_MASK) << SPI_INTR_TX_ACTIVE_OFFS)
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#define SPI_SCLK_CONFIG_OFFS 0
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#define SPI_SCLK_CONFIG_MASK 0xfff
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#define SPI_SCLK_CONFIG(V) ((V & SPI_SCLK_CONFIG_MASK) << SPI_SCLK_CONFIG_OFFS)
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#define SPI_SSGEN_SETUP_OFFS 0
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#define SPI_SSGEN_SETUP_MASK 0xfff
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#define SPI_SSGEN_SETUP(V) ((V & SPI_SSGEN_SETUP_MASK) << SPI_SSGEN_SETUP_OFFS)
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#define SPI_SSGEN_HOLD_OFFS 0
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#define SPI_SSGEN_HOLD_MASK 0xfff
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#define SPI_SSGEN_HOLD(V) ((V & SPI_SSGEN_HOLD_MASK) << SPI_SSGEN_HOLD_OFFS)
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#define SPI_SSGEN_DISABLE_OFFS 0
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#define SPI_SSGEN_DISABLE_MASK 0xfff
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#define SPI_SSGEN_DISABLE(V) ((V & SPI_SSGEN_DISABLE_MASK) << SPI_SSGEN_DISABLE_OFFS)
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#define SPI_SSGEN_ACTIVE_HIGH_OFFS 0
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#define SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
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#define SPI_SSGEN_ACTIVE_HIGH(V) ((V & SPI_SSGEN_ACTIVE_HIGH_MASK) << SPI_SSGEN_ACTIVE_HIGH_OFFS)
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#define SPI_XIP_ENABLE_OFFS 0
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#define SPI_XIP_ENABLE_MASK 0x1
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#define SPI_XIP_ENABLE(V) ((V & SPI_XIP_ENABLE_MASK) << SPI_XIP_ENABLE_OFFS)
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#define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
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#define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
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#define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
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#define SPI_XIP_CONFIG_ENABLE_OFFS 8
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#define SPI_XIP_CONFIG_ENABLE_MASK 1
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#define SPI_XIP_CONFIG_ENABLE_MASK 0x1
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#define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
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#define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
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@ -49,166 +129,254 @@ typedef struct __attribute((__packed__)) {
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#define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
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#define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
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inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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#define SPI_XIP_MODE_INSTRUCTION_OFFS 0
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#define SPI_XIP_MODE_INSTRUCTION_MASK 0x7
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#define SPI_XIP_MODE_INSTRUCTION(V) ((V & SPI_XIP_MODE_INSTRUCTION_MASK) << SPI_XIP_MODE_INSTRUCTION_OFFS)
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#define SPI_XIP_MODE_ADDRESS_OFFS 8
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#define SPI_XIP_MODE_ADDRESS_MASK 0x7
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#define SPI_XIP_MODE_ADDRESS(V) ((V & SPI_XIP_MODE_ADDRESS_MASK) << SPI_XIP_MODE_ADDRESS_OFFS)
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#define SPI_XIP_MODE_DUMMY_OFFS 16
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#define SPI_XIP_MODE_DUMMY_MASK 0x7
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#define SPI_XIP_MODE_DUMMY(V) ((V & SPI_XIP_MODE_DUMMY_MASK) << SPI_XIP_MODE_DUMMY_OFFS)
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#define SPI_XIP_MODE_PAYLOAD_OFFS 24
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#define SPI_XIP_MODE_PAYLOAD_MASK 0x7
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#define SPI_XIP_MODE_PAYLOAD(V) ((V & SPI_XIP_MODE_PAYLOAD_MASK) << SPI_XIP_MODE_PAYLOAD_OFFS)
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#define SPI_XIP_WRITE_OFFS 0
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#define SPI_XIP_WRITE_MASK 0xff
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#define SPI_XIP_WRITE(V) ((V & SPI_XIP_WRITE_MASK) << SPI_XIP_WRITE_OFFS)
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#define SPI_XIP_READ_WRITE_OFFS 0
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#define SPI_XIP_READ_WRITE_MASK 0xff
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#define SPI_XIP_READ_WRITE(V) ((V & SPI_XIP_READ_WRITE_MASK) << SPI_XIP_READ_WRITE_OFFS)
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#define SPI_XIP_READ_OFFS 0
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#define SPI_XIP_READ_MASK 0xff
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#define SPI_XIP_READ(V) ((V & SPI_XIP_READ_MASK) << SPI_XIP_READ_OFFS)
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//SPI_DATA
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inline uint32_t get_spi_data(volatile apb3spixdrmasterctrl_t* reg){
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return reg->DATA;
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}
|
||||
inline void set_spi_data(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
|
||||
reg->DATA = value;
|
||||
}
|
||||
inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->DATA >> 8) & 0x1;
|
||||
}
|
||||
inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->DATA >> 9) & 0x1;
|
||||
}
|
||||
inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->DATA >> 11) & 0x1;
|
||||
}
|
||||
inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->DATA >> 31) & 0x1;
|
||||
}
|
||||
inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_STATUS
|
||||
inline uint32_t get_spi_status(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return reg->STATUS;
|
||||
}
|
||||
inline void set_spi_status(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
|
||||
reg->STATUS = value;
|
||||
}
|
||||
inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->STATUS >> 0) & 0x3f;
|
||||
}
|
||||
inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->STATUS >> 16) & 0x3f;
|
||||
}
|
||||
inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_CONFIG
|
||||
inline uint32_t get_spi_config(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return reg->CONFIG;
|
||||
}
|
||||
inline void set_spi_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
|
||||
reg->CONFIG = value;
|
||||
}
|
||||
inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->CONFIG >> 0) & 0x3;
|
||||
}
|
||||
inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->CONFIG >> 4) & 0x7;
|
||||
}
|
||||
inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
|
||||
}
|
||||
inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_INTR
|
||||
inline uint32_t get_spi_intr(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return reg->INTR;
|
||||
}
|
||||
inline void set_spi_intr(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
|
||||
reg->INTR = value;
|
||||
}
|
||||
inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->INTR >> 0) & 0x1;
|
||||
}
|
||||
inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->INTR >> 1) & 0x1;
|
||||
}
|
||||
inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->INTR >> 8) & 0x1;
|
||||
}
|
||||
inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->INTR >> 9) & 0x1;
|
||||
}
|
||||
inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->INTR >> 16) & 0x1;
|
||||
}
|
||||
inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_SCLK_CONFIG
|
||||
inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->SCLK_CONFIG >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
|
||||
inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
|
||||
reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_SSGEN_SETUP
|
||||
inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->SSGEN_SETUP >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
|
||||
inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
|
||||
reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_SSGEN_HOLD
|
||||
inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->SSGEN_HOLD >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
|
||||
inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
|
||||
reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_SSGEN_DISABLE
|
||||
inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->SSGEN_DISABLE >> 0) & 0xfff;
|
||||
}
|
||||
inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
|
||||
inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
|
||||
reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_SSGEN_ACTIVE_HIGH
|
||||
inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
|
||||
}
|
||||
inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_XIP_ENABLE
|
||||
inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_ENABLE >> 0) & 0x1;
|
||||
}
|
||||
inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg){
|
||||
return reg->XIP_CONFIG;
|
||||
|
||||
//SPI_XIP_CONFIG
|
||||
inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return reg->XIP_CONFIG;
|
||||
}
|
||||
inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t *reg, uint32_t value){
|
||||
reg->XIP_CONFIG = value;
|
||||
inline void set_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
|
||||
reg->XIP_CONFIG = value;
|
||||
}
|
||||
inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_CONFIG >> 0) & 0xff;
|
||||
}
|
||||
inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_CONFIG >> 8) & 0x1;
|
||||
}
|
||||
inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
|
||||
}
|
||||
inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_CONFIG >> 16) & 0xff;
|
||||
}
|
||||
inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
|
||||
}
|
||||
inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_CONFIG >> 24) & 0xf;
|
||||
}
|
||||
inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
|
||||
}
|
||||
inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_XIP_MODE
|
||||
inline uint32_t get_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return reg->XIP_MODE;
|
||||
}
|
||||
inline void set_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
|
||||
reg->XIP_MODE = value;
|
||||
}
|
||||
inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_MODE >> 0) & 0x7;
|
||||
}
|
||||
inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_MODE >> 8) & 0x7;
|
||||
}
|
||||
inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
|
||||
}
|
||||
inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_MODE >> 16) & 0x7;
|
||||
}
|
||||
inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
|
||||
}
|
||||
inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg){
|
||||
inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_MODE >> 24) & 0x7;
|
||||
}
|
||||
inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
|
||||
}
|
||||
inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
|
||||
//SPI_XIP_WRITE
|
||||
inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
|
||||
|
||||
//SPI_XIP_READ_WRITE
|
||||
inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
|
||||
reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){
|
||||
|
||||
//SPI_XIP_READ
|
||||
inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t* reg){
|
||||
return (reg->XIP_READ >> 0) & 0xff;
|
||||
}
|
||||
|
||||
#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */
|
||||
|
|
@ -3,8 +3,8 @@
|
|||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-02-19 14:24:37 UTC
|
||||
* by peakrdl_mnrs version 1.2.2
|
||||
* Generated at 2024-03-28 09:32:44 UTC
|
||||
* by peakrdl_mnrs version 1.2.4
|
||||
*/
|
||||
|
||||
#ifndef _BSP_APB3TIMER_H
|
||||
|
|
@ -22,52 +22,114 @@ typedef struct __attribute((__packed__)) {
|
|||
volatile uint32_t T1_VALUE;
|
||||
}apb3timer_t;
|
||||
|
||||
inline uint32_t get_timer_prescaler(volatile apb3timer_t *reg){
|
||||
#define TIMER_PRESCALER_OFFS 0
|
||||
#define TIMER_PRESCALER_MASK 0xffff
|
||||
#define TIMER_PRESCALER(V) ((V & TIMER_PRESCALER_MASK) << TIMER_PRESCALER_OFFS)
|
||||
|
||||
#define TIMER_T0_CTRL_ENABLE_OFFS 0
|
||||
#define TIMER_T0_CTRL_ENABLE_MASK 0x7
|
||||
#define TIMER_T0_CTRL_ENABLE(V) ((V & TIMER_T0_CTRL_ENABLE_MASK) << TIMER_T0_CTRL_ENABLE_OFFS)
|
||||
|
||||
#define TIMER_T0_CTRL_CLEAR_OFFS 3
|
||||
#define TIMER_T0_CTRL_CLEAR_MASK 0x3
|
||||
#define TIMER_T0_CTRL_CLEAR(V) ((V & TIMER_T0_CTRL_CLEAR_MASK) << TIMER_T0_CTRL_CLEAR_OFFS)
|
||||
|
||||
#define TIMER_T0_OVERFLOW_OFFS 0
|
||||
#define TIMER_T0_OVERFLOW_MASK 0xffffffff
|
||||
#define TIMER_T0_OVERFLOW(V) ((V & TIMER_T0_OVERFLOW_MASK) << TIMER_T0_OVERFLOW_OFFS)
|
||||
|
||||
#define TIMER_T0_VALUE_OFFS 0
|
||||
#define TIMER_T0_VALUE_MASK 0xffffffff
|
||||
#define TIMER_T0_VALUE(V) ((V & TIMER_T0_VALUE_MASK) << TIMER_T0_VALUE_OFFS)
|
||||
|
||||
#define TIMER_T1_CTRL_ENABLE_OFFS 0
|
||||
#define TIMER_T1_CTRL_ENABLE_MASK 0x7
|
||||
#define TIMER_T1_CTRL_ENABLE(V) ((V & TIMER_T1_CTRL_ENABLE_MASK) << TIMER_T1_CTRL_ENABLE_OFFS)
|
||||
|
||||
#define TIMER_T1_CTRL_CLEAR_OFFS 3
|
||||
#define TIMER_T1_CTRL_CLEAR_MASK 0x3
|
||||
#define TIMER_T1_CTRL_CLEAR(V) ((V & TIMER_T1_CTRL_CLEAR_MASK) << TIMER_T1_CTRL_CLEAR_OFFS)
|
||||
|
||||
#define TIMER_T1_OVERFLOW_OFFS 0
|
||||
#define TIMER_T1_OVERFLOW_MASK 0xffffffff
|
||||
#define TIMER_T1_OVERFLOW(V) ((V & TIMER_T1_OVERFLOW_MASK) << TIMER_T1_OVERFLOW_OFFS)
|
||||
|
||||
#define TIMER_T1_VALUE_OFFS 0
|
||||
#define TIMER_T1_VALUE_MASK 0xffffffff
|
||||
#define TIMER_T1_VALUE(V) ((V & TIMER_T1_VALUE_MASK) << TIMER_T1_VALUE_OFFS)
|
||||
|
||||
//TIMER_PRESCALER
|
||||
inline uint32_t get_timer_prescaler(volatile apb3timer_t* reg){
|
||||
return (reg->PRESCALER >> 0) & 0xffff;
|
||||
}
|
||||
inline void set_timer_prescaler(volatile apb3timer_t *reg, uint16_t value){
|
||||
inline void set_timer_prescaler(volatile apb3timer_t* reg, uint16_t value){
|
||||
reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t *reg){
|
||||
|
||||
//TIMER_T0_CTRL
|
||||
inline uint32_t get_timer_t0_ctrl(volatile apb3timer_t* reg){
|
||||
return reg->T0_CTRL;
|
||||
}
|
||||
inline void set_timer_t0_ctrl(volatile apb3timer_t* reg, uint32_t value){
|
||||
reg->T0_CTRL = value;
|
||||
}
|
||||
inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t* reg){
|
||||
return (reg->T0_CTRL >> 0) & 0x7;
|
||||
}
|
||||
inline void set_timer_t0_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
|
||||
inline void set_timer_t0_ctrl_enable(volatile apb3timer_t* reg, uint8_t value){
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t *reg){
|
||||
inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t* reg){
|
||||
return (reg->T0_CTRL >> 3) & 0x3;
|
||||
}
|
||||
inline void set_timer_t0_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
|
||||
inline void set_timer_t0_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
inline uint32_t get_timer_t0_overflow(volatile apb3timer_t *reg){
|
||||
|
||||
//TIMER_T0_OVERFLOW
|
||||
inline uint32_t get_timer_t0_overflow(volatile apb3timer_t* reg){
|
||||
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_timer_t0_overflow(volatile apb3timer_t *reg, uint32_t value){
|
||||
inline void set_timer_t0_overflow(volatile apb3timer_t* reg, uint32_t value){
|
||||
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t0_value(volatile apb3timer_t *reg){
|
||||
|
||||
//TIMER_T0_VALUE
|
||||
inline uint32_t get_timer_t0_value(volatile apb3timer_t* reg){
|
||||
return (reg->T0_VALUE >> 0) & 0xffffffff;
|
||||
}
|
||||
inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t *reg){
|
||||
|
||||
//TIMER_T1_CTRL
|
||||
inline uint32_t get_timer_t1_ctrl(volatile apb3timer_t* reg){
|
||||
return reg->T1_CTRL;
|
||||
}
|
||||
inline void set_timer_t1_ctrl(volatile apb3timer_t* reg, uint32_t value){
|
||||
reg->T1_CTRL = value;
|
||||
}
|
||||
inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t* reg){
|
||||
return (reg->T1_CTRL >> 0) & 0x7;
|
||||
}
|
||||
inline void set_timer_t1_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
|
||||
inline void set_timer_t1_ctrl_enable(volatile apb3timer_t* reg, uint8_t value){
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t *reg){
|
||||
inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t* reg){
|
||||
return (reg->T1_CTRL >> 3) & 0x3;
|
||||
}
|
||||
inline void set_timer_t1_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
|
||||
inline void set_timer_t1_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
inline uint32_t get_timer_t1_overflow(volatile apb3timer_t *reg){
|
||||
|
||||
//TIMER_T1_OVERFLOW
|
||||
inline uint32_t get_timer_t1_overflow(volatile apb3timer_t* reg){
|
||||
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_timer_t1_overflow(volatile apb3timer_t *reg, uint32_t value){
|
||||
inline void set_timer_t1_overflow(volatile apb3timer_t* reg, uint32_t value){
|
||||
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t1_value(volatile apb3timer_t *reg){
|
||||
|
||||
//TIMER_T1_VALUE
|
||||
inline uint32_t get_timer_t1_value(volatile apb3timer_t* reg){
|
||||
return (reg->T1_VALUE >> 0) & 0xffffffff;
|
||||
}
|
||||
|
||||
#endif /* _BSP_APB3TIMER_H */
|
||||
|
|
@ -3,8 +3,8 @@
|
|||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-02-19 14:24:37 UTC
|
||||
* by peakrdl_mnrs version 1.2.2
|
||||
* Generated at 2024-03-28 09:32:44 UTC
|
||||
* by peakrdl_mnrs version 1.2.4
|
||||
*/
|
||||
|
||||
#ifndef _BSP_APB3UART_H
|
||||
|
|
@ -20,85 +20,187 @@ typedef struct __attribute((__packed__)) {
|
|||
volatile uint32_t STATUS_REG;
|
||||
}apb3uart_t;
|
||||
|
||||
inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t *reg){
|
||||
#define UART_RX_TX_REG_DATA_OFFS 0
|
||||
#define UART_RX_TX_REG_DATA_MASK 0xff
|
||||
#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
|
||||
#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
|
||||
#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
|
||||
|
||||
#define UART_RX_TX_REG_TX_FREE_OFFS 15
|
||||
#define UART_RX_TX_REG_TX_FREE_MASK 0x1
|
||||
#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
|
||||
#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
|
||||
|
||||
#define UART_CLK_DIVIDER_REG_OFFS 0
|
||||
#define UART_CLK_DIVIDER_REG_MASK 0xfffff
|
||||
#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7
|
||||
#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
|
||||
#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
|
||||
#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
|
||||
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
|
||||
#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_READ_ERROR_OFFS 0
|
||||
#define UART_STATUS_REG_READ_ERROR_MASK 0x1
|
||||
#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_STALL_OFFS 1
|
||||
#define UART_STATUS_REG_STALL_MASK 0x1
|
||||
#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_OFFS 8
|
||||
#define UART_STATUS_REG_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK(V) ((V & UART_STATUS_REG_BREAK_MASK) << UART_STATUS_REG_BREAK_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
|
||||
#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
|
||||
#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_SET_BREAK_OFFS 10
|
||||
#define UART_STATUS_REG_SET_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
|
||||
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
|
||||
#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
|
||||
#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
|
||||
|
||||
//UART_RX_TX_REG
|
||||
inline uint32_t get_uart_rx_tx_reg(volatile apb3uart_t* reg){
|
||||
return reg->RX_TX_REG;
|
||||
}
|
||||
inline void set_uart_rx_tx_reg(volatile apb3uart_t* reg, uint32_t value){
|
||||
reg->RX_TX_REG = value;
|
||||
}
|
||||
inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t* reg){
|
||||
return (reg->RX_TX_REG >> 0) & 0xff;
|
||||
}
|
||||
inline void set_uart_rx_tx_reg_data(volatile apb3uart_t *reg, uint8_t value){
|
||||
inline void set_uart_rx_tx_reg_data(volatile apb3uart_t* reg, uint8_t value){
|
||||
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t* reg){
|
||||
return (reg->RX_TX_REG >> 14) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t* reg){
|
||||
return (reg->RX_TX_REG >> 15) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg){
|
||||
|
||||
//UART_INT_CTRL_REG
|
||||
inline uint32_t get_uart_int_ctrl_reg(volatile apb3uart_t* reg){
|
||||
return reg->INT_CTRL_REG;
|
||||
}
|
||||
inline void set_uart_int_ctrl_reg(volatile apb3uart_t* reg, uint32_t value){
|
||||
reg->INT_CTRL_REG = value;
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t* reg){
|
||||
return (reg->INT_CTRL_REG >> 0) & 0x1;
|
||||
}
|
||||
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg, uint8_t value){
|
||||
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t* reg, uint8_t value){
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t* reg){
|
||||
return (reg->INT_CTRL_REG >> 1) & 0x1;
|
||||
}
|
||||
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg, uint8_t value){
|
||||
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t* reg, uint8_t value){
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t* reg){
|
||||
return (reg->INT_CTRL_REG >> 8) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t* reg){
|
||||
return (reg->INT_CTRL_REG >> 9) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t *reg){
|
||||
|
||||
//UART_CLK_DIVIDER_REG
|
||||
inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t* reg){
|
||||
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
|
||||
}
|
||||
inline void set_uart_clk_divider_reg(volatile apb3uart_t *reg, uint32_t value){
|
||||
inline void set_uart_clk_divider_reg(volatile apb3uart_t* reg, uint32_t value){
|
||||
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg){
|
||||
|
||||
//UART_FRAME_CONFIG_REG
|
||||
inline uint32_t get_uart_frame_config_reg(volatile apb3uart_t* reg){
|
||||
return reg->FRAME_CONFIG_REG;
|
||||
}
|
||||
inline void set_uart_frame_config_reg(volatile apb3uart_t* reg, uint32_t value){
|
||||
reg->FRAME_CONFIG_REG = value;
|
||||
}
|
||||
inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t* reg){
|
||||
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
|
||||
}
|
||||
inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg, uint8_t value){
|
||||
inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t* reg, uint8_t value){
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t* reg){
|
||||
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
|
||||
}
|
||||
inline void set_uart_frame_config_reg_parity(volatile apb3uart_t *reg, uint8_t value){
|
||||
inline void set_uart_frame_config_reg_parity(volatile apb3uart_t* reg, uint8_t value){
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t* reg){
|
||||
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
|
||||
}
|
||||
inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg, uint8_t value){
|
||||
inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t* reg, uint8_t value){
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t *reg){
|
||||
|
||||
//UART_STATUS_REG
|
||||
inline uint32_t get_uart_status_reg(volatile apb3uart_t* reg){
|
||||
return reg->STATUS_REG;
|
||||
}
|
||||
inline void set_uart_status_reg(volatile apb3uart_t* reg, uint32_t value){
|
||||
reg->STATUS_REG = value;
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t* reg){
|
||||
return (reg->STATUS_REG >> 0) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t* reg){
|
||||
return (reg->STATUS_REG >> 1) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_break(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_status_reg_break(volatile apb3uart_t* reg){
|
||||
return (reg->STATUS_REG >> 8) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t *reg){
|
||||
inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t* reg){
|
||||
return (reg->STATUS_REG >> 9) & 0x1;
|
||||
}
|
||||
inline void set_uart_status_reg_break_detected(volatile apb3uart_t *reg, uint8_t value){
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inline void set_uart_status_reg_break_detected(volatile apb3uart_t* reg, uint8_t value){
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reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
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}
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inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t *reg){
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inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t* reg){
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return (reg->STATUS_REG >> 10) & 0x1;
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||||
}
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inline void set_uart_status_reg_set_break(volatile apb3uart_t *reg, uint8_t value){
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inline void set_uart_status_reg_set_break(volatile apb3uart_t* reg, uint8_t value){
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reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
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||||
}
|
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inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t *reg){
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inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t* reg){
|
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return (reg->STATUS_REG >> 11) & 0x1;
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||||
}
|
||||
inline void set_uart_status_reg_clear_break(volatile apb3uart_t *reg, uint8_t value){
|
||||
inline void set_uart_status_reg_clear_break(volatile apb3uart_t* reg, uint8_t value){
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
|
||||
#endif /* _BSP_APB3UART_H */
|
||||
Loading…
Reference in New Issue