adds improved firmware headers for peripherals

include/ehrenberg/devices/gen/Apb3AClint.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-02-19 14:24:37 UTC 
+* Generated at 2024-03-28 09:32:44 UTC 
-* by peakrdl_mnrs version 1.2.2
+* by peakrdl_mnrs version 1.2.4
 */
 
 #ifndef _BSP_APB3ACLINT_H
@@ -14,40 +14,72 @@
 
 typedef struct __attribute((__packed__)) {
     volatile uint32_t MSIP0;
+    uint8_t fill0 [16380];
     volatile uint32_t MTIMECMP0LO;
     volatile uint32_t MTIMECMP0HI;
+    uint8_t fill0 [32752];
     volatile uint32_t MTIME_LO;
     volatile uint32_t MTIME_HI;
 }apb3aclint_t;
 
+#define ACLINT_MSIP0_OFFS 0
+#define ACLINT_MSIP0_MASK 0x1
+#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
+
+#define ACLINT_MTIMECMP0LO_OFFS 0
+#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
+#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
+
+#define ACLINT_MTIMECMP0HI_OFFS 0
+#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
+#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
+
+#define ACLINT_MTIME_LO_OFFS 0
+#define ACLINT_MTIME_LO_MASK 0xffffffff
+#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
+
+#define ACLINT_MTIME_HI_OFFS 0
+#define ACLINT_MTIME_HI_MASK 0xffffffff
+#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
+
+//ACLINT_MSIP0
 inline uint32_t get_aclint_msip0(volatile apb3aclint_t* reg){
     return (reg->MSIP0 >> 0) & 0x1;
 }
 inline void set_aclint_msip0(volatile apb3aclint_t* reg, uint8_t value){
     reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
 }
+
+//ACLINT_MTIMECMP0LO
 inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t* reg){
     return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
 }
 inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t* reg, uint32_t value){
     reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
 }
+
+//ACLINT_MTIMECMP0HI
 inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t* reg){
     return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
 }
 inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t* reg, uint32_t value){
     reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
 }
+
+//ACLINT_MTIME_LO
 inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t* reg){
     return (reg->MTIME_LO >> 0) & 0xffffffff;
 }
 inline void set_aclint_mtime_lo(volatile apb3aclint_t* reg, uint32_t value){
     reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
 }
+
+//ACLINT_MTIME_HI
 inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t* reg){
     return (reg->MTIME_HI >> 0) & 0xffffffff;
 }
 inline void set_aclint_mtime_hi(volatile apb3aclint_t* reg, uint32_t value){
     reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
 }
+
 #endif /* _BSP_APB3ACLINT_H */

include/ehrenberg/devices/gen/Apb3Gpio.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-02-19 14:24:37 UTC 
+* Generated at 2024-03-28 09:32:44 UTC 
-* by peakrdl_mnrs version 1.2.2
+* by peakrdl_mnrs version 1.2.4
 */
 
 #ifndef _BSP_APB3GPIO_H
@@ -18,19 +18,37 @@ typedef struct __attribute((__packed__)) {
     volatile uint32_t WRITEENABLE;
 }apb3gpio_t;
 
+#define GPIO_VALUE_OFFS 0
+#define GPIO_VALUE_MASK 0xffffffff
+#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
+
+#define GPIO_WRITE_OFFS 0
+#define GPIO_WRITE_MASK 0xffffffff
+#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
+
+#define GPIO_WRITEENABLE_OFFS 0
+#define GPIO_WRITEENABLE_MASK 0xffffffff
+#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
+
+//GPIO_VALUE
 inline uint32_t get_gpio_value(volatile apb3gpio_t* reg){
     return (reg->VALUE >> 0) & 0xffffffff;
 }
+
+//GPIO_WRITE
 inline uint32_t get_gpio_write(volatile apb3gpio_t* reg){
     return (reg->WRITE >> 0) & 0xffffffff;
 }
 inline void set_gpio_write(volatile apb3gpio_t* reg, uint32_t value){
     reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
 }
+
+//GPIO_WRITEENABLE
 inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t* reg){
     return (reg->WRITEENABLE >> 0) & 0xffffffff;
 }
 inline void set_gpio_writeEnable(volatile apb3gpio_t* reg, uint32_t value){
     reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
 }
+
 #endif /* _BSP_APB3GPIO_H */

include/ehrenberg/devices/gen/Apb3IrqCtrl.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-02-19 14:24:37 UTC 
+* Generated at 2024-03-28 09:32:44 UTC 
-* by peakrdl_mnrs version 1.2.2
+* by peakrdl_mnrs version 1.2.4
 */
 
 #ifndef _BSP_APB3IRQCTRL_H
@@ -17,16 +17,28 @@ typedef struct __attribute((__packed__)) {
     volatile uint32_t MASKSREG;
 }apb3irqctrl_t;
 
+#define IRQ_PENDINGSREG_OFFS 0
+#define IRQ_PENDINGSREG_MASK 0xf
+#define IRQ_PENDINGSREG(V) ((V & IRQ_PENDINGSREG_MASK) << IRQ_PENDINGSREG_OFFS)
+
+#define IRQ_MASKSREG_OFFS 0
+#define IRQ_MASKSREG_MASK 0xf
+#define IRQ_MASKSREG(V) ((V & IRQ_MASKSREG_MASK) << IRQ_MASKSREG_OFFS)
+
+//IRQ_PENDINGSREG
 inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t* reg){
     return (reg->PENDINGSREG >> 0) & 0xf;
 }
 inline void set_irq_pendingsReg(volatile apb3irqctrl_t* reg, uint8_t value){
     reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
 }
+
+//IRQ_MASKSREG
 inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t* reg){
     return (reg->MASKSREG >> 0) & 0xf;
 }
 inline void set_irq_masksReg(volatile apb3irqctrl_t* reg, uint8_t value){
     reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
 }
+
 #endif /* _BSP_APB3IRQCTRL_H */

include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-02-19 14:24:37 UTC 
+* Generated at 2024-03-28 09:32:44 UTC 
-* by peakrdl_mnrs version 1.2.2
+* by peakrdl_mnrs version 1.2.4
 */
 
 #ifndef _BSP_APB3SPIXDRMASTERCTRL_H
@@ -17,28 +17,108 @@ typedef struct __attribute((__packed__)) {
     volatile uint32_t STATUS;
     volatile uint32_t CONFIG;
     volatile uint32_t INTR;
-    uint32_t fill0[4];
+    uint8_t fill0 [16];
     volatile uint32_t SCLK_CONFIG;
     volatile uint32_t SSGEN_SETUP;
     volatile uint32_t SSGEN_HOLD;
     volatile uint32_t SSGEN_DISABLE;
     volatile uint32_t SSGEN_ACTIVE_HIGH;
-    uint32_t fill1[3];
+    uint8_t fill0 [12];
     volatile uint32_t XIP_ENABLE;
     volatile uint32_t XIP_CONFIG;
     volatile uint32_t XIP_MODE;
-    uint32_t fill2[1];
+    uint8_t fill0 [4];
     volatile uint32_t XIP_WRITE;
     volatile uint32_t XIP_READ_WRITE;
     volatile uint32_t XIP_READ;
 }apb3spixdrmasterctrl_t;
 
+#define SPI_DATA_DATA_OFFS 0
+#define SPI_DATA_DATA_MASK 0xff
+#define SPI_DATA_DATA(V) ((V & SPI_DATA_DATA_MASK) << SPI_DATA_DATA_OFFS)
+
+#define SPI_DATA_WRITE_OFFS 8
+#define SPI_DATA_WRITE_MASK 0x1
+#define SPI_DATA_WRITE(V) ((V & SPI_DATA_WRITE_MASK) << SPI_DATA_WRITE_OFFS)
+
+#define SPI_DATA_READ_OFFS 9
+#define SPI_DATA_READ_MASK 0x1
+#define SPI_DATA_READ(V) ((V & SPI_DATA_READ_MASK) << SPI_DATA_READ_OFFS)
+
+#define SPI_DATA_KIND_OFFS 11
+#define SPI_DATA_KIND_MASK 0x1
+#define SPI_DATA_KIND(V) ((V & SPI_DATA_KIND_MASK) << SPI_DATA_KIND_OFFS)
+
+#define SPI_DATA_RX_DATA_INVALID_OFFS 31
+#define SPI_DATA_RX_DATA_INVALID_MASK 0x1
+#define SPI_DATA_RX_DATA_INVALID(V) ((V & SPI_DATA_RX_DATA_INVALID_MASK) << SPI_DATA_RX_DATA_INVALID_OFFS)
+
+#define SPI_STATUS_TX_FREE_OFFS 0
+#define SPI_STATUS_TX_FREE_MASK 0x3f
+#define SPI_STATUS_TX_FREE(V) ((V & SPI_STATUS_TX_FREE_MASK) << SPI_STATUS_TX_FREE_OFFS)
+
+#define SPI_STATUS_RX_AVAIL_OFFS 16
+#define SPI_STATUS_RX_AVAIL_MASK 0x3f
+#define SPI_STATUS_RX_AVAIL(V) ((V & SPI_STATUS_RX_AVAIL_MASK) << SPI_STATUS_RX_AVAIL_OFFS)
+
+#define SPI_CONFIG_KIND_OFFS 0
+#define SPI_CONFIG_KIND_MASK 0x3
+#define SPI_CONFIG_KIND(V) ((V & SPI_CONFIG_KIND_MASK) << SPI_CONFIG_KIND_OFFS)
+
+#define SPI_CONFIG_MODE_OFFS 4
+#define SPI_CONFIG_MODE_MASK 0x7
+#define SPI_CONFIG_MODE(V) ((V & SPI_CONFIG_MODE_MASK) << SPI_CONFIG_MODE_OFFS)
+
+#define SPI_INTR_TX_IE_OFFS 0
+#define SPI_INTR_TX_IE_MASK 0x1
+#define SPI_INTR_TX_IE(V) ((V & SPI_INTR_TX_IE_MASK) << SPI_INTR_TX_IE_OFFS)
+
+#define SPI_INTR_RX_IE_OFFS 1
+#define SPI_INTR_RX_IE_MASK 0x1
+#define SPI_INTR_RX_IE(V) ((V & SPI_INTR_RX_IE_MASK) << SPI_INTR_RX_IE_OFFS)
+
+#define SPI_INTR_TX_IP_OFFS 8
+#define SPI_INTR_TX_IP_MASK 0x1
+#define SPI_INTR_TX_IP(V) ((V & SPI_INTR_TX_IP_MASK) << SPI_INTR_TX_IP_OFFS)
+
+#define SPI_INTR_RX_IP_OFFS 9
+#define SPI_INTR_RX_IP_MASK 0x1
+#define SPI_INTR_RX_IP(V) ((V & SPI_INTR_RX_IP_MASK) << SPI_INTR_RX_IP_OFFS)
+
+#define SPI_INTR_TX_ACTIVE_OFFS 16
+#define SPI_INTR_TX_ACTIVE_MASK 0x1
+#define SPI_INTR_TX_ACTIVE(V) ((V & SPI_INTR_TX_ACTIVE_MASK) << SPI_INTR_TX_ACTIVE_OFFS)
+
+#define SPI_SCLK_CONFIG_OFFS 0
+#define SPI_SCLK_CONFIG_MASK 0xfff
+#define SPI_SCLK_CONFIG(V) ((V & SPI_SCLK_CONFIG_MASK) << SPI_SCLK_CONFIG_OFFS)
+
+#define SPI_SSGEN_SETUP_OFFS 0
+#define SPI_SSGEN_SETUP_MASK 0xfff
+#define SPI_SSGEN_SETUP(V) ((V & SPI_SSGEN_SETUP_MASK) << SPI_SSGEN_SETUP_OFFS)
+
+#define SPI_SSGEN_HOLD_OFFS 0
+#define SPI_SSGEN_HOLD_MASK 0xfff
+#define SPI_SSGEN_HOLD(V) ((V & SPI_SSGEN_HOLD_MASK) << SPI_SSGEN_HOLD_OFFS)
+
+#define SPI_SSGEN_DISABLE_OFFS 0
+#define SPI_SSGEN_DISABLE_MASK 0xfff
+#define SPI_SSGEN_DISABLE(V) ((V & SPI_SSGEN_DISABLE_MASK) << SPI_SSGEN_DISABLE_OFFS)
+
+#define SPI_SSGEN_ACTIVE_HIGH_OFFS 0
+#define SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
+#define SPI_SSGEN_ACTIVE_HIGH(V) ((V & SPI_SSGEN_ACTIVE_HIGH_MASK) << SPI_SSGEN_ACTIVE_HIGH_OFFS)
+
+#define SPI_XIP_ENABLE_OFFS 0
+#define SPI_XIP_ENABLE_MASK 0x1
+#define SPI_XIP_ENABLE(V) ((V & SPI_XIP_ENABLE_MASK) << SPI_XIP_ENABLE_OFFS)
+
 #define SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
 #define SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
 #define SPI_XIP_CONFIG_INSTRUCTION(V) ((V & SPI_XIP_CONFIG_INSTRUCTION_MASK) << SPI_XIP_CONFIG_INSTRUCTION_OFFS)
 
 #define SPI_XIP_CONFIG_ENABLE_OFFS 8
-#define SPI_XIP_CONFIG_ENABLE_MASK 1
+#define SPI_XIP_CONFIG_ENABLE_MASK 0x1
 #define SPI_XIP_CONFIG_ENABLE(V) ((V & SPI_XIP_CONFIG_ENABLE_MASK) << SPI_XIP_CONFIG_ENABLE_OFFS)
 
 #define SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
@@ -49,6 +129,41 @@ typedef struct __attribute((__packed__)) {
 #define SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
 #define SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
 
+#define SPI_XIP_MODE_INSTRUCTION_OFFS 0
+#define SPI_XIP_MODE_INSTRUCTION_MASK 0x7
+#define SPI_XIP_MODE_INSTRUCTION(V) ((V & SPI_XIP_MODE_INSTRUCTION_MASK) << SPI_XIP_MODE_INSTRUCTION_OFFS)
+
+#define SPI_XIP_MODE_ADDRESS_OFFS 8
+#define SPI_XIP_MODE_ADDRESS_MASK 0x7
+#define SPI_XIP_MODE_ADDRESS(V) ((V & SPI_XIP_MODE_ADDRESS_MASK) << SPI_XIP_MODE_ADDRESS_OFFS)
+
+#define SPI_XIP_MODE_DUMMY_OFFS 16
+#define SPI_XIP_MODE_DUMMY_MASK 0x7
+#define SPI_XIP_MODE_DUMMY(V) ((V & SPI_XIP_MODE_DUMMY_MASK) << SPI_XIP_MODE_DUMMY_OFFS)
+
+#define SPI_XIP_MODE_PAYLOAD_OFFS 24
+#define SPI_XIP_MODE_PAYLOAD_MASK 0x7
+#define SPI_XIP_MODE_PAYLOAD(V) ((V & SPI_XIP_MODE_PAYLOAD_MASK) << SPI_XIP_MODE_PAYLOAD_OFFS)
+
+#define SPI_XIP_WRITE_OFFS 0
+#define SPI_XIP_WRITE_MASK 0xff
+#define SPI_XIP_WRITE(V) ((V & SPI_XIP_WRITE_MASK) << SPI_XIP_WRITE_OFFS)
+
+#define SPI_XIP_READ_WRITE_OFFS 0
+#define SPI_XIP_READ_WRITE_MASK 0xff
+#define SPI_XIP_READ_WRITE(V) ((V & SPI_XIP_READ_WRITE_MASK) << SPI_XIP_READ_WRITE_OFFS)
+
+#define SPI_XIP_READ_OFFS 0
+#define SPI_XIP_READ_MASK 0xff
+#define SPI_XIP_READ(V) ((V & SPI_XIP_READ_MASK) << SPI_XIP_READ_OFFS)
+
+//SPI_DATA
+inline uint32_t get_spi_data(volatile apb3spixdrmasterctrl_t* reg){
+     return reg->DATA;
+}
+inline void set_spi_data(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
+     reg->DATA = value;
+}
 inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
 }
@@ -73,12 +188,28 @@ inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t valu
 inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->DATA >> 31) & 0x1;
 }
+
+//SPI_STATUS
+inline uint32_t get_spi_status(volatile apb3spixdrmasterctrl_t* reg){
+     return reg->STATUS;
+}
+inline void set_spi_status(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
+     reg->STATUS = value;
+}
 inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->STATUS >> 0) & 0x3f;
 }
 inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->STATUS >> 16) & 0x3f;
 }
+
+//SPI_CONFIG
+inline uint32_t get_spi_config(volatile apb3spixdrmasterctrl_t* reg){
+     return reg->CONFIG;
+}
+inline void set_spi_config(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
+     reg->CONFIG = value;
+}
 inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->CONFIG >> 0) & 0x3;
 }
@@ -91,6 +222,14 @@ inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg){
 inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
 }
+
+//SPI_INTR
+inline uint32_t get_spi_intr(volatile apb3spixdrmasterctrl_t* reg){
+     return reg->INTR;
+}
+inline void set_spi_intr(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
+     reg->INTR = value;
+}
 inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->INTR >> 0) & 0x1;
 }
@@ -112,42 +251,56 @@ inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t *reg){
 inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->INTR >> 16) & 0x1;
 }
+
+//SPI_SCLK_CONFIG
 inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->SCLK_CONFIG >> 0) & 0xfff;
 }
 inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
     reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
 }
+
+//SPI_SSGEN_SETUP
 inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->SSGEN_SETUP >> 0) & 0xfff;
 }
 inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
     reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
 }
+
+//SPI_SSGEN_HOLD
 inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->SSGEN_HOLD >> 0) & 0xfff;
 }
 inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
     reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
 }
+
+//SPI_SSGEN_DISABLE
 inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->SSGEN_DISABLE >> 0) & 0xfff;
 }
 inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t* reg, uint16_t value){
     reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
 }
+
+//SPI_SSGEN_ACTIVE_HIGH
 inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
 }
 inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
 }
+
+//SPI_XIP_ENABLE
 inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->XIP_ENABLE >> 0) & 0x1;
 }
 inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
 }
+
+//SPI_XIP_CONFIG
 inline uint32_t get_spi_xip_config(volatile apb3spixdrmasterctrl_t* reg){
      return reg->XIP_CONFIG;
 }
@@ -178,6 +331,14 @@ inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *
 inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
 }
+
+//SPI_XIP_MODE
+inline uint32_t get_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg){
+     return reg->XIP_MODE;
+}
+inline void set_spi_xip_mode(volatile apb3spixdrmasterctrl_t* reg, uint32_t value){
+     reg->XIP_MODE = value;
+}
 inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->XIP_MODE >> 0) & 0x7;
 }
@@ -202,13 +363,20 @@ inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg){
 inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
 }
+
+//SPI_XIP_WRITE
 inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
 }
+
+//SPI_XIP_READ_WRITE
 inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t* reg, uint8_t value){
     reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
 }
+
+//SPI_XIP_READ
 inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t* reg){
     return (reg->XIP_READ >> 0) & 0xff;
 }
+
 #endif /* _BSP_APB3SPIXDRMASTERCTRL_H */

include/ehrenberg/devices/gen/Apb3Timer.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-02-19 14:24:37 UTC 
+* Generated at 2024-03-28 09:32:44 UTC 
-* by peakrdl_mnrs version 1.2.2
+* by peakrdl_mnrs version 1.2.4
 */
 
 #ifndef _BSP_APB3TIMER_H
@@ -22,12 +22,57 @@ typedef struct __attribute((__packed__)) {
     volatile uint32_t T1_VALUE;
 }apb3timer_t;
 
+#define TIMER_PRESCALER_OFFS 0
+#define TIMER_PRESCALER_MASK 0xffff
+#define TIMER_PRESCALER(V) ((V & TIMER_PRESCALER_MASK) << TIMER_PRESCALER_OFFS)
+
+#define TIMER_T0_CTRL_ENABLE_OFFS 0
+#define TIMER_T0_CTRL_ENABLE_MASK 0x7
+#define TIMER_T0_CTRL_ENABLE(V) ((V & TIMER_T0_CTRL_ENABLE_MASK) << TIMER_T0_CTRL_ENABLE_OFFS)
+
+#define TIMER_T0_CTRL_CLEAR_OFFS 3
+#define TIMER_T0_CTRL_CLEAR_MASK 0x3
+#define TIMER_T0_CTRL_CLEAR(V) ((V & TIMER_T0_CTRL_CLEAR_MASK) << TIMER_T0_CTRL_CLEAR_OFFS)
+
+#define TIMER_T0_OVERFLOW_OFFS 0
+#define TIMER_T0_OVERFLOW_MASK 0xffffffff
+#define TIMER_T0_OVERFLOW(V) ((V & TIMER_T0_OVERFLOW_MASK) << TIMER_T0_OVERFLOW_OFFS)
+
+#define TIMER_T0_VALUE_OFFS 0
+#define TIMER_T0_VALUE_MASK 0xffffffff
+#define TIMER_T0_VALUE(V) ((V & TIMER_T0_VALUE_MASK) << TIMER_T0_VALUE_OFFS)
+
+#define TIMER_T1_CTRL_ENABLE_OFFS 0
+#define TIMER_T1_CTRL_ENABLE_MASK 0x7
+#define TIMER_T1_CTRL_ENABLE(V) ((V & TIMER_T1_CTRL_ENABLE_MASK) << TIMER_T1_CTRL_ENABLE_OFFS)
+
+#define TIMER_T1_CTRL_CLEAR_OFFS 3
+#define TIMER_T1_CTRL_CLEAR_MASK 0x3
+#define TIMER_T1_CTRL_CLEAR(V) ((V & TIMER_T1_CTRL_CLEAR_MASK) << TIMER_T1_CTRL_CLEAR_OFFS)
+
+#define TIMER_T1_OVERFLOW_OFFS 0
+#define TIMER_T1_OVERFLOW_MASK 0xffffffff
+#define TIMER_T1_OVERFLOW(V) ((V & TIMER_T1_OVERFLOW_MASK) << TIMER_T1_OVERFLOW_OFFS)
+
+#define TIMER_T1_VALUE_OFFS 0
+#define TIMER_T1_VALUE_MASK 0xffffffff
+#define TIMER_T1_VALUE(V) ((V & TIMER_T1_VALUE_MASK) << TIMER_T1_VALUE_OFFS)
+
+//TIMER_PRESCALER
 inline uint32_t get_timer_prescaler(volatile apb3timer_t* reg){
     return (reg->PRESCALER >> 0) & 0xffff;
 }
 inline void set_timer_prescaler(volatile apb3timer_t* reg, uint16_t value){
     reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
 }
+
+//TIMER_T0_CTRL
+inline uint32_t get_timer_t0_ctrl(volatile apb3timer_t* reg){
+     return reg->T0_CTRL;
+}
+inline void set_timer_t0_ctrl(volatile apb3timer_t* reg, uint32_t value){
+     reg->T0_CTRL = value;
+}
 inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t* reg){
     return (reg->T0_CTRL >> 0) & 0x7;
 }
@@ -40,15 +85,27 @@ inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t *reg){
 inline void set_timer_t0_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
     reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
 }
+
+//TIMER_T0_OVERFLOW
 inline uint32_t get_timer_t0_overflow(volatile apb3timer_t* reg){
     return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
 }
 inline void set_timer_t0_overflow(volatile apb3timer_t* reg, uint32_t value){
     reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
 }
+
+//TIMER_T0_VALUE
 inline uint32_t get_timer_t0_value(volatile apb3timer_t* reg){
     return (reg->T0_VALUE >> 0) & 0xffffffff;
 }
+
+//TIMER_T1_CTRL
+inline uint32_t get_timer_t1_ctrl(volatile apb3timer_t* reg){
+     return reg->T1_CTRL;
+}
+inline void set_timer_t1_ctrl(volatile apb3timer_t* reg, uint32_t value){
+     reg->T1_CTRL = value;
+}
 inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t* reg){
     return (reg->T1_CTRL >> 0) & 0x7;
 }
@@ -61,13 +118,18 @@ inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t *reg){
 inline void set_timer_t1_ctrl_clear(volatile apb3timer_t* reg, uint8_t value){
     reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
 }
+
+//TIMER_T1_OVERFLOW
 inline uint32_t get_timer_t1_overflow(volatile apb3timer_t* reg){
     return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
 }
 inline void set_timer_t1_overflow(volatile apb3timer_t* reg, uint32_t value){
     reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
 }
+
+//TIMER_T1_VALUE
 inline uint32_t get_timer_t1_value(volatile apb3timer_t* reg){
     return (reg->T1_VALUE >> 0) & 0xffffffff;
 }
+
 #endif /* _BSP_APB3TIMER_H */

include/ehrenberg/devices/gen/Apb3Uart.h

@@ -3,8 +3,8 @@
 *
 * SPDX-License-Identifier: Apache-2.0
 *
-* Generated at 2024-02-19 14:24:37 UTC 
+* Generated at 2024-03-28 09:32:44 UTC 
-* by peakrdl_mnrs version 1.2.2
+* by peakrdl_mnrs version 1.2.4
 */
 
 #ifndef _BSP_APB3UART_H
@@ -20,6 +20,81 @@ typedef struct __attribute((__packed__)) {
     volatile uint32_t STATUS_REG;
 }apb3uart_t;
 
+#define UART_RX_TX_REG_DATA_OFFS 0
+#define UART_RX_TX_REG_DATA_MASK 0xff
+#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
+
+#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
+#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
+#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
+
+#define UART_RX_TX_REG_TX_FREE_OFFS 15
+#define UART_RX_TX_REG_TX_FREE_MASK 0x1
+#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
+#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
+
+#define UART_CLK_DIVIDER_REG_OFFS 0
+#define UART_CLK_DIVIDER_REG_MASK 0xfffff
+#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
+
+#define UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS 0
+#define UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK 0x7
+#define UART_FRAME_CONFIG_REG_DATA_LENGHT(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGHT_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGHT_OFFS)
+
+#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
+#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
+#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
+
+#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
+#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
+#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
+
+#define UART_STATUS_REG_READ_ERROR_OFFS 0
+#define UART_STATUS_REG_READ_ERROR_MASK 0x1
+#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
+
+#define UART_STATUS_REG_STALL_OFFS 1
+#define UART_STATUS_REG_STALL_MASK 0x1
+#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
+
+#define UART_STATUS_REG_BREAK_OFFS 8
+#define UART_STATUS_REG_BREAK_MASK 0x1
+#define UART_STATUS_REG_BREAK(V) ((V & UART_STATUS_REG_BREAK_MASK) << UART_STATUS_REG_BREAK_OFFS)
+
+#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
+#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
+#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
+
+#define UART_STATUS_REG_SET_BREAK_OFFS 10
+#define UART_STATUS_REG_SET_BREAK_MASK 0x1
+#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
+
+#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
+#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
+#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
+
+//UART_RX_TX_REG
+inline uint32_t get_uart_rx_tx_reg(volatile apb3uart_t* reg){
+     return reg->RX_TX_REG;
+}
+inline void set_uart_rx_tx_reg(volatile apb3uart_t* reg, uint32_t value){
+     reg->RX_TX_REG = value;
+}
 inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t* reg){
     return (reg->RX_TX_REG >> 0) & 0xff;
 }
@@ -32,6 +107,14 @@ inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t *reg){
 inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t* reg){
     return (reg->RX_TX_REG >> 15) & 0x1;
 }
+
+//UART_INT_CTRL_REG
+inline uint32_t get_uart_int_ctrl_reg(volatile apb3uart_t* reg){
+     return reg->INT_CTRL_REG;
+}
+inline void set_uart_int_ctrl_reg(volatile apb3uart_t* reg, uint32_t value){
+     reg->INT_CTRL_REG = value;
+}
 inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t* reg){
     return (reg->INT_CTRL_REG >> 0) & 0x1;
 }
@@ -50,12 +133,22 @@ inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t *reg){
 inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t* reg){
     return (reg->INT_CTRL_REG >> 9) & 0x1;
 }
+
+//UART_CLK_DIVIDER_REG
 inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t* reg){
     return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
 }
 inline void set_uart_clk_divider_reg(volatile apb3uart_t* reg, uint32_t value){
     reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
 }
+
+//UART_FRAME_CONFIG_REG
+inline uint32_t get_uart_frame_config_reg(volatile apb3uart_t* reg){
+     return reg->FRAME_CONFIG_REG;
+}
+inline void set_uart_frame_config_reg(volatile apb3uart_t* reg, uint32_t value){
+     reg->FRAME_CONFIG_REG = value;
+}
 inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t* reg){
     return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
 }
@@ -74,6 +167,14 @@ inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg){
 inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t* reg, uint8_t value){
     reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
 }
+
+//UART_STATUS_REG
+inline uint32_t get_uart_status_reg(volatile apb3uart_t* reg){
+     return reg->STATUS_REG;
+}
+inline void set_uart_status_reg(volatile apb3uart_t* reg, uint32_t value){
+     reg->STATUS_REG = value;
+}
 inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t* reg){
     return (reg->STATUS_REG >> 0) & 0x1;
 }
@@ -101,4 +202,5 @@ inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t *reg){
 inline void set_uart_status_reg_clear_break(volatile apb3uart_t* reg, uint8_t value){
     reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
 }
+
 #endif /* _BSP_APB3UART_H */