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update moonlight register headers. Remove unused control register in 

camera
This commit is contained in:
Stanislaw Kaushanski 2024-09-10 15:46:32 +02:00
parent f632436fda
commit b36a42b386
3 changed files with 36 additions and 59 deletions
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14
include/ehrenberg/devices/gen/apb3spi.h
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@ -3,8 +3,8 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-08-02 08:46:07 UTC * Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.7 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_APB3SPI_H #ifndef _BSP_APB3SPI_H
@ -17,17 +17,17 @@ typedef struct {
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t CONFIG; volatile uint32_t CONFIG;
volatile uint32_t INTR; volatile uint32_t INTR;
uint32_t fill0[4]; uint8_t fill0[16];
volatile uint32_t SCLK_CONFIG; volatile uint32_t SCLK_CONFIG;
volatile uint32_t SSGEN_SETUP; volatile uint32_t SSGEN_SETUP;
volatile uint32_t SSGEN_HOLD; volatile uint32_t SSGEN_HOLD;
volatile uint32_t SSGEN_DISABLE; volatile uint32_t SSGEN_DISABLE;
volatile uint32_t SSGEN_ACTIVE_HIGH; volatile uint32_t SSGEN_ACTIVE_HIGH;
uint32_t fill1[3]; uint8_t fill1[12];
volatile uint32_t XIP_ENABLE; volatile uint32_t XIP_ENABLE;
volatile uint32_t XIP_CONFIG; volatile uint32_t XIP_CONFIG;
volatile uint32_t XIP_MODE; volatile uint32_t XIP_MODE;
uint32_t fill2[1]; uint8_t fill2[4];
volatile uint32_t XIP_WRITE; volatile uint32_t XIP_WRITE;
volatile uint32_t XIP_READ_WRITE; volatile uint32_t XIP_READ_WRITE;
volatile uint32_t XIP_READ; volatile uint32_t XIP_READ;
@ -312,10 +312,10 @@ inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){ inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
reg->SSGEN_ACTIVE_HIGH = value; reg->SSGEN_ACTIVE_HIGH = value;
} }
inline uint32_t get_apb3spi_ssgen_active_high_high_cycles(volatile apb3spi_t* reg){ inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1; return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
} }
inline void set_apb3spi_ssgen_active_high_high_cycles(volatile apb3spi_t* reg, uint8_t value){ inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0); reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
} }

45
include/ehrenberg/devices/gen/camera.h
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@ -3,8 +3,8 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-08-02 08:46:07 UTC * Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.7 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_CAMERA_H #ifndef _BSP_CAMERA_H
@ -14,7 +14,6 @@
typedef struct { typedef struct {
volatile uint32_t PIXEL; volatile uint32_t PIXEL;
volatile uint32_t CONTROL;
volatile uint32_t STATUS; volatile uint32_t STATUS;
volatile uint32_t CAMERA_CLOCK_CTRL; volatile uint32_t CAMERA_CLOCK_CTRL;
volatile uint32_t IE; volatile uint32_t IE;
@ -25,21 +24,9 @@ typedef struct {
#define CAMERA_PIXEL_MASK 0x7ff #define CAMERA_PIXEL_MASK 0x7ff
#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS) #define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
#define CAMERA_CONTROL_OFFS 0 #define CAMERA_STATUS_OFFS 0
#define CAMERA_CONTROL_MASK 0x1 #define CAMERA_STATUS_MASK 0x1
#define CAMERA_CONTROL(V) ((V & CAMERA_CONTROL_MASK) << CAMERA_CONTROL_OFFS) #define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
#define CAMERA_STATUS_ENABLED_OFFS 0
#define CAMERA_STATUS_ENABLED_MASK 0x1
#define CAMERA_STATUS_ENABLED(V) ((V & CAMERA_STATUS_ENABLED_MASK) << CAMERA_STATUS_ENABLED_OFFS)
#define CAMERA_STATUS_ACTIVE_OFFS 1
#define CAMERA_STATUS_ACTIVE_MASK 0x1
#define CAMERA_STATUS_ACTIVE(V) ((V & CAMERA_STATUS_ACTIVE_MASK) << CAMERA_STATUS_ACTIVE_OFFS)
#define CAMERA_STATUS_PIXEL_AVAIL_OFFS 2
#define CAMERA_STATUS_PIXEL_AVAIL_MASK 0x1
#define CAMERA_STATUS_PIXEL_AVAIL(V) ((V & CAMERA_STATUS_PIXEL_AVAIL_MASK) << CAMERA_STATUS_PIXEL_AVAIL_OFFS)
#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0 #define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff #define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff
@ -75,32 +62,12 @@ inline void set_camera_pixel_data(volatile camera_t* reg, uint16_t value){
reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0); reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0);
} }
//CAMERA_CONTROL
inline uint32_t get_camera_control(volatile camera_t* reg){
return reg->CONTROL;
}
inline void set_camera_control(volatile camera_t* reg, uint32_t value){
reg->CONTROL = value;
}
inline uint32_t get_camera_control_active_clock(volatile camera_t* reg){
return (reg->CONTROL >> 0) & 0x1;
}
inline void set_camera_control_active_clock(volatile camera_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
}
//CAMERA_STATUS //CAMERA_STATUS
inline uint32_t get_camera_status(volatile camera_t* reg){ inline uint32_t get_camera_status(volatile camera_t* reg){
return reg->STATUS; return reg->STATUS;
} }
inline uint32_t get_camera_status_enabled(volatile camera_t* reg){
return (reg->STATUS >> 0) & 0x1;
}
inline uint32_t get_camera_status_active(volatile camera_t* reg){
return (reg->STATUS >> 1) & 0x1;
}
inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){ inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
return (reg->STATUS >> 2) & 0x1; return (reg->STATUS >> 0) & 0x1;
} }
//CAMERA_CAMERA_CLOCK_CTRL //CAMERA_CAMERA_CLOCK_CTRL

30
include/ehrenberg/devices/gen/i2s.h
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@ -3,8 +3,8 @@
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
* Generated at 2024-08-02 08:46:07 UTC * Generated at 2024-09-10 14:29:50 UTC
* by peakrdl_mnrs version 1.2.7 * by peakrdl_mnrs version 1.2.9
*/ */
#ifndef _BSP_I2S_H #ifndef _BSP_I2S_H
@ -43,11 +43,15 @@ typedef struct {
#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1 #define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS) #define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
#define I2S_CONTROL_ACTIVE_CLOCK_OFFS 4 #define I2S_CONTROL_IS_MASTER_OFFS 4
#define I2S_CONTROL_ACTIVE_CLOCK_MASK 0x1 #define I2S_CONTROL_IS_MASTER_MASK 0x1
#define I2S_CONTROL_ACTIVE_CLOCK(V) ((V & I2S_CONTROL_ACTIVE_CLOCK_MASK) << I2S_CONTROL_ACTIVE_CLOCK_OFFS) #define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
#define I2S_CONTROL_PDM_SCALE_OFFS 5 #define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
#define I2S_CONTROL_PDM_SCALE_OFFS 7
#define I2S_CONTROL_PDM_SCALE_MASK 0x7 #define I2S_CONTROL_PDM_SCALE_MASK 0x7
#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS) #define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
@ -126,17 +130,23 @@ inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){ inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3); reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
} }
inline uint32_t get_i2s_control_active_clock(volatile i2s_t* reg){ inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
return (reg->CONTROL >> 4) & 0x1; return (reg->CONTROL >> 4) & 0x1;
} }
inline void set_i2s_control_active_clock(volatile i2s_t* reg, uint8_t value){ inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4); reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
} }
inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
return (reg->CONTROL >> 5) & 0x3;
}
inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
}
inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){ inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
return (reg->CONTROL >> 5) & 0x7; return (reg->CONTROL >> 7) & 0x7;
} }
inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){ inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
reg->CONTROL = (reg->CONTROL & ~(0x7U << 5)) | (value << 5); reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
} }
//I2S_STATUS //I2S_STATUS