replaces ehrenberg with new implementations

2025-01-06 20:15:44 +01:00
parent f419b1a3e6
commit 9ff9727bd6
25 changed files with 0 additions and 0 deletions
--- a/include/minres/devices/aclint.h
+++ b/include/minres/devices/aclint.h
@ -0,0 +1,28 @@
+#ifndef _DEVICES_ACLINT_H
+#define _DEVICES_ACLINT_H
+
+#include <stdint.h>
+#include "gen/aclint.h"
+
+
+static void set_aclint_mtime(volatile aclint_t* reg, uint64_t value){
+    set_aclint_mtime_hi(reg, (uint32_t)(value >> 32));
+    set_aclint_mtime_lo(reg, (uint32_t)value);
+}
+
+static uint64_t get_aclint_mtime(volatile aclint_t* reg){
+    uint64_t value = ((uint64_t)get_aclint_mtime_hi(reg) << 32) | (uint64_t)get_aclint_mtime_lo(reg);
+    return value;
+}
+
+static void set_aclint_mtimecmp(volatile aclint_t* reg, uint64_t value){
+    set_aclint_mtimecmp0hi(reg, (uint32_t)(value >> 32));
+    set_aclint_mtimecmp0lo(reg, (uint32_t)value);
+}
+
+static uint64_t get_aclint_mtimecmp(volatile aclint_t* reg){
+    uint64_t value = ((uint64_t)get_aclint_mtimecmp0hi(reg) << 32) | (uint64_t)get_aclint_mtimecmp0lo(reg);
+    return value;
+}
+
+#endif /* _DEVICES_ACLINT_H */
--- a/include/minres/devices/camera.h
+++ b/include/minres/devices/camera.h
@ -0,0 +1,6 @@
+#ifndef _DEVICES_CAM_H
+#define _DEVICES_CAM_H
+
+#include "gen/camera.h"
+
+#endif /* _DEVICES_CAM_H */
--- a/include/minres/devices/dma.h
+++ b/include/minres/devices/dma.h
@ -0,0 +1,11 @@
+#ifndef _DEVICES_DMA_H
+#define _DEVICES_DMA_H
+
+#include "gen/dma.h"
+
+#define EVENT_UART 1
+#define I2S_LEFT_SAMPLE_AVAIL 2
+#define I2S_RIGHT_SAMPLE_AVAIL 4
+#define CAMERA_PIXEL_AVAIL 8
+
+#endif /* _BSP_DMA_H */
--- a/include/minres/devices/gen/aclint.h
+++ b/include/minres/devices/gen/aclint.h
@ -0,0 +1,91 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-02 08:46:07 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_ACLINT_H
+#define _BSP_ACLINT_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t MSIP0;
+    uint8_t fill0[16380];
+    volatile uint32_t MTIMECMP0LO;
+    volatile uint32_t MTIMECMP0HI;
+    uint8_t fill1[32752];
+    volatile uint32_t MTIME_LO;
+    volatile uint32_t MTIME_HI;
+}aclint_t;
+
+#define ACLINT_MSIP0_OFFS 0
+#define ACLINT_MSIP0_MASK 0x1
+#define ACLINT_MSIP0(V) ((V & ACLINT_MSIP0_MASK) << ACLINT_MSIP0_OFFS)
+
+#define ACLINT_MTIMECMP0LO_OFFS 0
+#define ACLINT_MTIMECMP0LO_MASK 0xffffffff
+#define ACLINT_MTIMECMP0LO(V) ((V & ACLINT_MTIMECMP0LO_MASK) << ACLINT_MTIMECMP0LO_OFFS)
+
+#define ACLINT_MTIMECMP0HI_OFFS 0
+#define ACLINT_MTIMECMP0HI_MASK 0xffffffff
+#define ACLINT_MTIMECMP0HI(V) ((V & ACLINT_MTIMECMP0HI_MASK) << ACLINT_MTIMECMP0HI_OFFS)
+
+#define ACLINT_MTIME_LO_OFFS 0
+#define ACLINT_MTIME_LO_MASK 0xffffffff
+#define ACLINT_MTIME_LO(V) ((V & ACLINT_MTIME_LO_MASK) << ACLINT_MTIME_LO_OFFS)
+
+#define ACLINT_MTIME_HI_OFFS 0
+#define ACLINT_MTIME_HI_MASK 0xffffffff
+#define ACLINT_MTIME_HI(V) ((V & ACLINT_MTIME_HI_MASK) << ACLINT_MTIME_HI_OFFS)
+
+//ACLINT_MSIP0
+inline uint32_t get_aclint_msip0(volatile aclint_t* reg){
+     return reg->MSIP0;
+}
+inline void set_aclint_msip0(volatile aclint_t* reg, uint32_t value){
+     reg->MSIP0 = value;
+}
+inline uint32_t get_aclint_msip0_msip(volatile aclint_t* reg){
+    return (reg->MSIP0 >> 0) & 0x1;
+}
+inline void set_aclint_msip0_msip(volatile aclint_t* reg, uint8_t value){
+    reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
+}
+
+//ACLINT_MTIMECMP0LO
+inline uint32_t get_aclint_mtimecmp0lo(volatile aclint_t* reg){
+    return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0lo(volatile aclint_t* reg, uint32_t value){
+    reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIMECMP0HI
+inline uint32_t get_aclint_mtimecmp0hi(volatile aclint_t* reg){
+    return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtimecmp0hi(volatile aclint_t* reg, uint32_t value){
+    reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIME_LO
+inline uint32_t get_aclint_mtime_lo(volatile aclint_t* reg){
+    return (reg->MTIME_LO >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_lo(volatile aclint_t* reg, uint32_t value){
+    reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//ACLINT_MTIME_HI
+inline uint32_t get_aclint_mtime_hi(volatile aclint_t* reg){
+    return (reg->MTIME_HI >> 0) & 0xffffffff;
+}
+inline void set_aclint_mtime_hi(volatile aclint_t* reg, uint32_t value){
+    reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_ACLINT_H */
--- a/include/minres/devices/gen/apb3spi.h
+++ b/include/minres/devices/gen/apb3spi.h
@ -0,0 +1,424 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-09-10 14:29:50 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_APB3SPI_H
+#define _BSP_APB3SPI_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t DATA;
+    volatile uint32_t STATUS;
+    volatile uint32_t CONFIG;
+    volatile uint32_t INTR;
+    uint8_t fill0[16];
+    volatile uint32_t SCLK_CONFIG;
+    volatile uint32_t SSGEN_SETUP;
+    volatile uint32_t SSGEN_HOLD;
+    volatile uint32_t SSGEN_DISABLE;
+    volatile uint32_t SSGEN_ACTIVE_HIGH;
+    uint8_t fill1[12];
+    volatile uint32_t XIP_ENABLE;
+    volatile uint32_t XIP_CONFIG;
+    volatile uint32_t XIP_MODE;
+    uint8_t fill2[4];
+    volatile uint32_t XIP_WRITE;
+    volatile uint32_t XIP_READ_WRITE;
+    volatile uint32_t XIP_READ;
+}apb3spi_t;
+
+#define APB3SPI_DATA_DATA_OFFS 0
+#define APB3SPI_DATA_DATA_MASK 0xff
+#define APB3SPI_DATA_DATA(V) ((V & APB3SPI_DATA_DATA_MASK) << APB3SPI_DATA_DATA_OFFS)
+
+#define APB3SPI_DATA_WRITE_OFFS 8
+#define APB3SPI_DATA_WRITE_MASK 0x1
+#define APB3SPI_DATA_WRITE(V) ((V & APB3SPI_DATA_WRITE_MASK) << APB3SPI_DATA_WRITE_OFFS)
+
+#define APB3SPI_DATA_READ_OFFS 9
+#define APB3SPI_DATA_READ_MASK 0x1
+#define APB3SPI_DATA_READ(V) ((V & APB3SPI_DATA_READ_MASK) << APB3SPI_DATA_READ_OFFS)
+
+#define APB3SPI_DATA_KIND_OFFS 11
+#define APB3SPI_DATA_KIND_MASK 0x1
+#define APB3SPI_DATA_KIND(V) ((V & APB3SPI_DATA_KIND_MASK) << APB3SPI_DATA_KIND_OFFS)
+
+#define APB3SPI_DATA_RX_DATA_INVALID_OFFS 31
+#define APB3SPI_DATA_RX_DATA_INVALID_MASK 0x1
+#define APB3SPI_DATA_RX_DATA_INVALID(V) ((V & APB3SPI_DATA_RX_DATA_INVALID_MASK) << APB3SPI_DATA_RX_DATA_INVALID_OFFS)
+
+#define APB3SPI_STATUS_TX_FREE_OFFS 0
+#define APB3SPI_STATUS_TX_FREE_MASK 0x3f
+#define APB3SPI_STATUS_TX_FREE(V) ((V & APB3SPI_STATUS_TX_FREE_MASK) << APB3SPI_STATUS_TX_FREE_OFFS)
+
+#define APB3SPI_STATUS_RX_AVAIL_OFFS 16
+#define APB3SPI_STATUS_RX_AVAIL_MASK 0x3f
+#define APB3SPI_STATUS_RX_AVAIL(V) ((V & APB3SPI_STATUS_RX_AVAIL_MASK) << APB3SPI_STATUS_RX_AVAIL_OFFS)
+
+#define APB3SPI_CONFIG_KIND_OFFS 0
+#define APB3SPI_CONFIG_KIND_MASK 0x3
+#define APB3SPI_CONFIG_KIND(V) ((V & APB3SPI_CONFIG_KIND_MASK) << APB3SPI_CONFIG_KIND_OFFS)
+
+#define APB3SPI_CONFIG_MODE_OFFS 4
+#define APB3SPI_CONFIG_MODE_MASK 0x3
+#define APB3SPI_CONFIG_MODE(V) ((V & APB3SPI_CONFIG_MODE_MASK) << APB3SPI_CONFIG_MODE_OFFS)
+
+#define APB3SPI_INTR_TX_IE_OFFS 0
+#define APB3SPI_INTR_TX_IE_MASK 0x1
+#define APB3SPI_INTR_TX_IE(V) ((V & APB3SPI_INTR_TX_IE_MASK) << APB3SPI_INTR_TX_IE_OFFS)
+
+#define APB3SPI_INTR_RX_IE_OFFS 1
+#define APB3SPI_INTR_RX_IE_MASK 0x1
+#define APB3SPI_INTR_RX_IE(V) ((V & APB3SPI_INTR_RX_IE_MASK) << APB3SPI_INTR_RX_IE_OFFS)
+
+#define APB3SPI_INTR_TX_IP_OFFS 8
+#define APB3SPI_INTR_TX_IP_MASK 0x1
+#define APB3SPI_INTR_TX_IP(V) ((V & APB3SPI_INTR_TX_IP_MASK) << APB3SPI_INTR_TX_IP_OFFS)
+
+#define APB3SPI_INTR_RX_IP_OFFS 9
+#define APB3SPI_INTR_RX_IP_MASK 0x1
+#define APB3SPI_INTR_RX_IP(V) ((V & APB3SPI_INTR_RX_IP_MASK) << APB3SPI_INTR_RX_IP_OFFS)
+
+#define APB3SPI_INTR_TX_ACTIVE_OFFS 16
+#define APB3SPI_INTR_TX_ACTIVE_MASK 0x1
+#define APB3SPI_INTR_TX_ACTIVE(V) ((V & APB3SPI_INTR_TX_ACTIVE_MASK) << APB3SPI_INTR_TX_ACTIVE_OFFS)
+
+#define APB3SPI_SCLK_CONFIG_OFFS 0
+#define APB3SPI_SCLK_CONFIG_MASK 0xfff
+#define APB3SPI_SCLK_CONFIG(V) ((V & APB3SPI_SCLK_CONFIG_MASK) << APB3SPI_SCLK_CONFIG_OFFS)
+
+#define APB3SPI_SSGEN_SETUP_OFFS 0
+#define APB3SPI_SSGEN_SETUP_MASK 0xfff
+#define APB3SPI_SSGEN_SETUP(V) ((V & APB3SPI_SSGEN_SETUP_MASK) << APB3SPI_SSGEN_SETUP_OFFS)
+
+#define APB3SPI_SSGEN_HOLD_OFFS 0
+#define APB3SPI_SSGEN_HOLD_MASK 0xfff
+#define APB3SPI_SSGEN_HOLD(V) ((V & APB3SPI_SSGEN_HOLD_MASK) << APB3SPI_SSGEN_HOLD_OFFS)
+
+#define APB3SPI_SSGEN_DISABLE_OFFS 0
+#define APB3SPI_SSGEN_DISABLE_MASK 0xfff
+#define APB3SPI_SSGEN_DISABLE(V) ((V & APB3SPI_SSGEN_DISABLE_MASK) << APB3SPI_SSGEN_DISABLE_OFFS)
+
+#define APB3SPI_SSGEN_ACTIVE_HIGH_OFFS 0
+#define APB3SPI_SSGEN_ACTIVE_HIGH_MASK 0x1
+#define APB3SPI_SSGEN_ACTIVE_HIGH(V) ((V & APB3SPI_SSGEN_ACTIVE_HIGH_MASK) << APB3SPI_SSGEN_ACTIVE_HIGH_OFFS)
+
+#define APB3SPI_XIP_ENABLE_OFFS 0
+#define APB3SPI_XIP_ENABLE_MASK 0x1
+#define APB3SPI_XIP_ENABLE(V) ((V & APB3SPI_XIP_ENABLE_MASK) << APB3SPI_XIP_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_CONFIG_INSTRUCTION_MASK 0xff
+#define APB3SPI_XIP_CONFIG_INSTRUCTION(V) ((V & APB3SPI_XIP_CONFIG_INSTRUCTION_MASK) << APB3SPI_XIP_CONFIG_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_CONFIG_ENABLE_OFFS 8
+#define APB3SPI_XIP_CONFIG_ENABLE_MASK 0x1
+#define APB3SPI_XIP_CONFIG_ENABLE(V) ((V & APB3SPI_XIP_CONFIG_ENABLE_MASK) << APB3SPI_XIP_CONFIG_ENABLE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS 16
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK 0xff
+#define APB3SPI_XIP_CONFIG_DUMMY_VALUE(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_VALUE_MASK) << APB3SPI_XIP_CONFIG_DUMMY_VALUE_OFFS)
+
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS 24
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK 0xf
+#define APB3SPI_XIP_CONFIG_DUMMY_COUNT(V) ((V & APB3SPI_XIP_CONFIG_DUMMY_COUNT_MASK) << APB3SPI_XIP_CONFIG_DUMMY_COUNT_OFFS)
+
+#define APB3SPI_XIP_MODE_INSTRUCTION_OFFS 0
+#define APB3SPI_XIP_MODE_INSTRUCTION_MASK 0x3
+#define APB3SPI_XIP_MODE_INSTRUCTION(V) ((V & APB3SPI_XIP_MODE_INSTRUCTION_MASK) << APB3SPI_XIP_MODE_INSTRUCTION_OFFS)
+
+#define APB3SPI_XIP_MODE_ADDRESS_OFFS 8
+#define APB3SPI_XIP_MODE_ADDRESS_MASK 0x3
+#define APB3SPI_XIP_MODE_ADDRESS(V) ((V & APB3SPI_XIP_MODE_ADDRESS_MASK) << APB3SPI_XIP_MODE_ADDRESS_OFFS)
+
+#define APB3SPI_XIP_MODE_DUMMY_OFFS 16
+#define APB3SPI_XIP_MODE_DUMMY_MASK 0x3
+#define APB3SPI_XIP_MODE_DUMMY(V) ((V & APB3SPI_XIP_MODE_DUMMY_MASK) << APB3SPI_XIP_MODE_DUMMY_OFFS)
+
+#define APB3SPI_XIP_MODE_PAYLOAD_OFFS 24
+#define APB3SPI_XIP_MODE_PAYLOAD_MASK 0x3
+#define APB3SPI_XIP_MODE_PAYLOAD(V) ((V & APB3SPI_XIP_MODE_PAYLOAD_MASK) << APB3SPI_XIP_MODE_PAYLOAD_OFFS)
+
+#define APB3SPI_XIP_WRITE_OFFS 0
+#define APB3SPI_XIP_WRITE_MASK 0xff
+#define APB3SPI_XIP_WRITE(V) ((V & APB3SPI_XIP_WRITE_MASK) << APB3SPI_XIP_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_WRITE_OFFS 0
+#define APB3SPI_XIP_READ_WRITE_MASK 0xff
+#define APB3SPI_XIP_READ_WRITE(V) ((V & APB3SPI_XIP_READ_WRITE_MASK) << APB3SPI_XIP_READ_WRITE_OFFS)
+
+#define APB3SPI_XIP_READ_OFFS 0
+#define APB3SPI_XIP_READ_MASK 0xff
+#define APB3SPI_XIP_READ(V) ((V & APB3SPI_XIP_READ_MASK) << APB3SPI_XIP_READ_OFFS)
+
+//APB3SPI_DATA
+inline uint32_t get_apb3spi_data(volatile apb3spi_t* reg){
+     return reg->DATA;
+}
+inline void set_apb3spi_data(volatile apb3spi_t* reg, uint32_t value){
+     reg->DATA = value;
+}
+inline void set_apb3spi_data_data(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_data_write(volatile apb3spi_t* reg){
+    return (reg->DATA >> 8) & 0x1;
+}
+inline void set_apb3spi_data_write(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_data_read(volatile apb3spi_t* reg){
+    return (reg->DATA >> 9) & 0x1;
+}
+inline void set_apb3spi_data_read(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_apb3spi_data_kind(volatile apb3spi_t* reg){
+    return (reg->DATA >> 11) & 0x1;
+}
+inline void set_apb3spi_data_kind(volatile apb3spi_t* reg, uint8_t value){
+    reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
+}
+inline uint32_t get_apb3spi_data_rx_data_invalid(volatile apb3spi_t* reg){
+    return (reg->DATA >> 31) & 0x1;
+}
+
+//APB3SPI_STATUS
+inline uint32_t get_apb3spi_status(volatile apb3spi_t* reg){
+     return reg->STATUS;
+}
+inline uint32_t get_apb3spi_status_tx_free(volatile apb3spi_t* reg){
+    return (reg->STATUS >> 0) & 0x3f;
+}
+inline uint32_t get_apb3spi_status_rx_avail(volatile apb3spi_t* reg){
+    return (reg->STATUS >> 16) & 0x3f;
+}
+
+//APB3SPI_CONFIG
+inline uint32_t get_apb3spi_config(volatile apb3spi_t* reg){
+     return reg->CONFIG;
+}
+inline void set_apb3spi_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->CONFIG = value;
+}
+inline uint32_t get_apb3spi_config_kind(volatile apb3spi_t* reg){
+    return (reg->CONFIG >> 0) & 0x3;
+}
+inline void set_apb3spi_config_kind(volatile apb3spi_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_config_mode(volatile apb3spi_t* reg){
+    return (reg->CONFIG >> 4) & 0x3;
+}
+inline void set_apb3spi_config_mode(volatile apb3spi_t* reg, uint8_t value){
+    reg->CONFIG = (reg->CONFIG & ~(0x3U << 4)) | (value << 4);
+}
+
+//APB3SPI_INTR
+inline uint32_t get_apb3spi_intr(volatile apb3spi_t* reg){
+     return reg->INTR;
+}
+inline void set_apb3spi_intr(volatile apb3spi_t* reg, uint32_t value){
+     reg->INTR = value;
+}
+inline uint32_t get_apb3spi_intr_tx_ie(volatile apb3spi_t* reg){
+    return (reg->INTR >> 0) & 0x1;
+}
+inline void set_apb3spi_intr_tx_ie(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_intr_rx_ie(volatile apb3spi_t* reg){
+    return (reg->INTR >> 1) & 0x1;
+}
+inline void set_apb3spi_intr_rx_ie(volatile apb3spi_t* reg, uint8_t value){
+    reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_apb3spi_intr_tx_ip(volatile apb3spi_t* reg){
+    return (reg->INTR >> 8) & 0x1;
+}
+inline uint32_t get_apb3spi_intr_rx_ip(volatile apb3spi_t* reg){
+    return (reg->INTR >> 9) & 0x1;
+}
+inline uint32_t get_apb3spi_intr_tx_active(volatile apb3spi_t* reg){
+    return (reg->INTR >> 16) & 0x1;
+}
+
+//APB3SPI_SCLK_CONFIG
+inline uint32_t get_apb3spi_sclk_config(volatile apb3spi_t* reg){
+     return reg->SCLK_CONFIG;
+}
+inline void set_apb3spi_sclk_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->SCLK_CONFIG = value;
+}
+inline uint32_t get_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg){
+    return (reg->SCLK_CONFIG >> 0) & 0xfff;
+}
+inline void set_apb3spi_sclk_config_clk_divider(volatile apb3spi_t* reg, uint16_t value){
+    reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_SETUP
+inline uint32_t get_apb3spi_ssgen_setup(volatile apb3spi_t* reg){
+     return reg->SSGEN_SETUP;
+}
+inline void set_apb3spi_ssgen_setup(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_SETUP = value;
+}
+inline uint32_t get_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg){
+    return (reg->SSGEN_SETUP >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_setup_setup_cycles(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_HOLD
+inline uint32_t get_apb3spi_ssgen_hold(volatile apb3spi_t* reg){
+     return reg->SSGEN_HOLD;
+}
+inline void set_apb3spi_ssgen_hold(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_HOLD = value;
+}
+inline uint32_t get_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg){
+    return (reg->SSGEN_HOLD >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_hold_hold_cycles(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_DISABLE
+inline uint32_t get_apb3spi_ssgen_disable(volatile apb3spi_t* reg){
+     return reg->SSGEN_DISABLE;
+}
+inline void set_apb3spi_ssgen_disable(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_DISABLE = value;
+}
+inline uint32_t get_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg){
+    return (reg->SSGEN_DISABLE >> 0) & 0xfff;
+}
+inline void set_apb3spi_ssgen_disable_disable_cycles(volatile apb3spi_t* reg, uint16_t value){
+    reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
+}
+
+//APB3SPI_SSGEN_ACTIVE_HIGH
+inline uint32_t get_apb3spi_ssgen_active_high(volatile apb3spi_t* reg){
+     return reg->SSGEN_ACTIVE_HIGH;
+}
+inline void set_apb3spi_ssgen_active_high(volatile apb3spi_t* reg, uint32_t value){
+     reg->SSGEN_ACTIVE_HIGH = value;
+}
+inline uint32_t get_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg){
+    return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
+}
+inline void set_apb3spi_ssgen_active_high_spi_cs_active_high(volatile apb3spi_t* reg, uint8_t value){
+    reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_ENABLE
+inline uint32_t get_apb3spi_xip_enable(volatile apb3spi_t* reg){
+     return reg->XIP_ENABLE;
+}
+inline void set_apb3spi_xip_enable(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_ENABLE = value;
+}
+inline uint32_t get_apb3spi_xip_enable_enable(volatile apb3spi_t* reg){
+    return (reg->XIP_ENABLE >> 0) & 0x1;
+}
+inline void set_apb3spi_xip_enable_enable(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_CONFIG
+inline uint32_t get_apb3spi_xip_config(volatile apb3spi_t* reg){
+     return reg->XIP_CONFIG;
+}
+inline void set_apb3spi_xip_config(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_CONFIG = value;
+}
+inline uint32_t get_apb3spi_xip_config_instruction(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 0) & 0xff;
+}
+inline void set_apb3spi_xip_config_instruction(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_xip_config_enable(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 8) & 0x1;
+}
+inline void set_apb3spi_xip_config_enable(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 16) & 0xff;
+}
+inline void set_apb3spi_xip_config_dummy_value(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
+}
+inline uint32_t get_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg){
+    return (reg->XIP_CONFIG >> 24) & 0xf;
+}
+inline void set_apb3spi_xip_config_dummy_count(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
+}
+
+//APB3SPI_XIP_MODE
+inline uint32_t get_apb3spi_xip_mode(volatile apb3spi_t* reg){
+     return reg->XIP_MODE;
+}
+inline void set_apb3spi_xip_mode(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_MODE = value;
+}
+inline uint32_t get_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 0) & 0x3;
+}
+inline void set_apb3spi_xip_mode_instruction(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_apb3spi_xip_mode_address(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 8) & 0x3;
+}
+inline void set_apb3spi_xip_mode_address(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 8)) | (value << 8);
+}
+inline uint32_t get_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 16) & 0x3;
+}
+inline void set_apb3spi_xip_mode_dummy(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 16)) | (value << 16);
+}
+inline uint32_t get_apb3spi_xip_mode_payload(volatile apb3spi_t* reg){
+    return (reg->XIP_MODE >> 24) & 0x3;
+}
+inline void set_apb3spi_xip_mode_payload(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_MODE = (reg->XIP_MODE & ~(0x3U << 24)) | (value << 24);
+}
+
+//APB3SPI_XIP_WRITE
+inline void set_apb3spi_xip_write(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_WRITE = value;
+}
+inline void set_apb3spi_xip_write_data(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_READ_WRITE
+inline void set_apb3spi_xip_read_write(volatile apb3spi_t* reg, uint32_t value){
+     reg->XIP_READ_WRITE = value;
+}
+inline void set_apb3spi_xip_read_write_data(volatile apb3spi_t* reg, uint8_t value){
+    reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
+}
+
+//APB3SPI_XIP_READ
+inline uint32_t get_apb3spi_xip_read(volatile apb3spi_t* reg){
+     return reg->XIP_READ;
+}
+inline uint32_t get_apb3spi_xip_read_data(volatile apb3spi_t* reg){
+    return (reg->XIP_READ >> 0) & 0xff;
+}
+
+#endif /* _BSP_APB3SPI_H */
--- a/include/minres/devices/gen/camera.h
+++ b/include/minres/devices/gen/camera.h
@ -0,0 +1,127 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-09-10 14:29:50 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_CAMERA_H
+#define _BSP_CAMERA_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t PIXEL;
+    volatile uint32_t STATUS;
+    volatile uint32_t CAMERA_CLOCK_CTRL;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+}camera_t;
+
+#define CAMERA_PIXEL_OFFS 0
+#define CAMERA_PIXEL_MASK 0x7ff
+#define CAMERA_PIXEL(V) ((V & CAMERA_PIXEL_MASK) << CAMERA_PIXEL_OFFS)
+
+#define CAMERA_STATUS_OFFS 0
+#define CAMERA_STATUS_MASK 0x1
+#define CAMERA_STATUS(V) ((V & CAMERA_STATUS_MASK) << CAMERA_STATUS_OFFS)
+
+#define CAMERA_CAMERA_CLOCK_CTRL_OFFS 0
+#define CAMERA_CAMERA_CLOCK_CTRL_MASK 0xfffff
+#define CAMERA_CAMERA_CLOCK_CTRL(V) ((V & CAMERA_CAMERA_CLOCK_CTRL_MASK) << CAMERA_CAMERA_CLOCK_CTRL_OFFS)
+
+#define CAMERA_IE_EN_PIXEL_AVAIL_OFFS 0
+#define CAMERA_IE_EN_PIXEL_AVAIL_MASK 0x1
+#define CAMERA_IE_EN_PIXEL_AVAIL(V) ((V & CAMERA_IE_EN_PIXEL_AVAIL_MASK) << CAMERA_IE_EN_PIXEL_AVAIL_OFFS)
+
+#define CAMERA_IE_EN_FRAME_FINISHED_OFFS 1
+#define CAMERA_IE_EN_FRAME_FINISHED_MASK 0x1
+#define CAMERA_IE_EN_FRAME_FINISHED(V) ((V & CAMERA_IE_EN_FRAME_FINISHED_MASK) << CAMERA_IE_EN_FRAME_FINISHED_OFFS)
+
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS 0
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_PIXEL_AVAIL_IRQ_PEND(V) ((V & CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_MASK) << CAMERA_IP_PIXEL_AVAIL_IRQ_PEND_OFFS)
+
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS 1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK 0x1
+#define CAMERA_IP_FRAME_FINISHED_IRQ_PEND(V) ((V & CAMERA_IP_FRAME_FINISHED_IRQ_PEND_MASK) << CAMERA_IP_FRAME_FINISHED_IRQ_PEND_OFFS)
+
+//CAMERA_PIXEL
+inline uint32_t get_camera_pixel(volatile camera_t* reg){
+     return reg->PIXEL;
+}
+inline void set_camera_pixel(volatile camera_t* reg, uint32_t value){
+     reg->PIXEL = value;
+}
+inline uint32_t get_camera_pixel_data(volatile camera_t* reg){
+    return (reg->PIXEL >> 0) & 0x7ff;
+}
+inline void set_camera_pixel_data(volatile camera_t* reg, uint16_t value){
+    reg->PIXEL = (reg->PIXEL & ~(0x7ffU << 0)) | (value << 0);
+}
+
+//CAMERA_STATUS
+inline uint32_t get_camera_status(volatile camera_t* reg){
+     return reg->STATUS;
+}
+inline uint32_t get_camera_status_pixel_avail(volatile camera_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+
+//CAMERA_CAMERA_CLOCK_CTRL
+inline uint32_t get_camera_camera_clock_ctrl(volatile camera_t* reg){
+     return reg->CAMERA_CLOCK_CTRL;
+}
+inline void set_camera_camera_clock_ctrl(volatile camera_t* reg, uint32_t value){
+     reg->CAMERA_CLOCK_CTRL = value;
+}
+inline uint32_t get_camera_camera_clock_ctrl_divider(volatile camera_t* reg){
+    return (reg->CAMERA_CLOCK_CTRL >> 0) & 0xfffff;
+}
+inline void set_camera_camera_clock_ctrl_divider(volatile camera_t* reg, uint32_t value){
+    reg->CAMERA_CLOCK_CTRL = (reg->CAMERA_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//CAMERA_IE
+inline uint32_t get_camera_ie(volatile camera_t* reg){
+     return reg->IE;
+}
+inline void set_camera_ie(volatile camera_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_camera_ie_en_pixel_avail(volatile camera_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_camera_ie_en_pixel_avail(volatile camera_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_ie_en_frame_finished(volatile camera_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_camera_ie_en_frame_finished(volatile camera_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+//CAMERA_IP
+inline uint32_t get_camera_ip(volatile camera_t* reg){
+     return reg->IP;
+}
+inline void set_camera_ip(volatile camera_t* reg, uint32_t value){
+     reg->IP = value;
+}
+inline uint32_t get_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline void set_camera_ip_pixel_avail_irq_pend(volatile camera_t* reg, uint8_t value){
+    reg->IP = (reg->IP & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_camera_ip_frame_finished_irq_pend(volatile camera_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+inline void set_camera_ip_frame_finished_irq_pend(volatile camera_t* reg, uint8_t value){
+    reg->IP = (reg->IP & ~(0x1U << 1)) | (value << 1);
+}
+
+#endif /* _BSP_CAMERA_H */
--- a/include/minres/devices/gen/dma.h
+++ b/include/minres/devices/gen/dma.h
@ -0,0 +1,454 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-02 08:46:07 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_DMA_H
+#define _BSP_DMA_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t CONTROL;
+    volatile uint32_t STATUS;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+    volatile uint32_t CH0_EVENT;
+    volatile uint32_t CH0_TRANSFER;
+    volatile uint32_t CH0_SRC_START_ADDR;
+    volatile uint32_t CH0_SRC_ADDR_INC;
+    volatile uint32_t CH0_DST_START_ADDR;
+    volatile uint32_t CH0_DST_ADDR_INC;
+    volatile uint32_t CH1_EVENT;
+    volatile uint32_t CH1_TRANSFER;
+    volatile uint32_t CH1_SRC_START_ADDR;
+    volatile uint32_t CH1_SRC_ADDR_INC;
+    volatile uint32_t CH1_DST_START_ADDR;
+    volatile uint32_t CH1_DST_ADDR_INC;
+}dma_t;
+
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS 0
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK 0x1
+#define DMA_CONTROL_CH0_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH0_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH0_ENABLE_TRANSFER_OFFS)
+
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS 1
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK 0x1
+#define DMA_CONTROL_CH1_ENABLE_TRANSFER(V) ((V & DMA_CONTROL_CH1_ENABLE_TRANSFER_MASK) << DMA_CONTROL_CH1_ENABLE_TRANSFER_OFFS)
+
+#define DMA_STATUS_CH0_BUSY_OFFS 0
+#define DMA_STATUS_CH0_BUSY_MASK 0x1
+#define DMA_STATUS_CH0_BUSY(V) ((V & DMA_STATUS_CH0_BUSY_MASK) << DMA_STATUS_CH0_BUSY_OFFS)
+
+#define DMA_STATUS_CH1_BUSY_OFFS 1
+#define DMA_STATUS_CH1_BUSY_MASK 0x1
+#define DMA_STATUS_CH1_BUSY(V) ((V & DMA_STATUS_CH1_BUSY_MASK) << DMA_STATUS_CH1_BUSY_OFFS)
+
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS 0
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH0_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH0_IE_TRANSFER_DONE_OFFS 1
+#define DMA_IE_CH0_IE_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH0_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH0_IE_TRANSFER_DONE_MASK) << DMA_IE_CH0_IE_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS 2
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH1_IE_SEG_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_SEG_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IE_CH1_IE_TRANSFER_DONE_OFFS 3
+#define DMA_IE_CH1_IE_TRANSFER_DONE_MASK 0x1
+#define DMA_IE_CH1_IE_TRANSFER_DONE(V) ((V & DMA_IE_CH1_IE_TRANSFER_DONE_MASK) << DMA_IE_CH1_IE_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS 0
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH0_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH0_IP_TRANSFER_DONE_OFFS 1
+#define DMA_IP_CH0_IP_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH0_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH0_IP_TRANSFER_DONE_MASK) << DMA_IP_CH0_IP_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS 2
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH1_IP_SEG_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_SEG_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_SEG_TRANSFER_DONE_OFFS)
+
+#define DMA_IP_CH1_IP_TRANSFER_DONE_OFFS 3
+#define DMA_IP_CH1_IP_TRANSFER_DONE_MASK 0x1
+#define DMA_IP_CH1_IP_TRANSFER_DONE(V) ((V & DMA_IP_CH1_IP_TRANSFER_DONE_MASK) << DMA_IP_CH1_IP_TRANSFER_DONE_OFFS)
+
+#define DMA_CH0_EVENT_SELECT_OFFS 0
+#define DMA_CH0_EVENT_SELECT_MASK 0x1f
+#define DMA_CH0_EVENT_SELECT(V) ((V & DMA_CH0_EVENT_SELECT_MASK) << DMA_CH0_EVENT_SELECT_OFFS)
+
+#define DMA_CH0_EVENT_COMBINE_OFFS 31
+#define DMA_CH0_EVENT_COMBINE_MASK 0x1
+#define DMA_CH0_EVENT_COMBINE(V) ((V & DMA_CH0_EVENT_COMBINE_MASK) << DMA_CH0_EVENT_COMBINE_OFFS)
+
+#define DMA_CH0_TRANSFER_WIDTH_OFFS 0
+#define DMA_CH0_TRANSFER_WIDTH_MASK 0x3
+#define DMA_CH0_TRANSFER_WIDTH(V) ((V & DMA_CH0_TRANSFER_WIDTH_MASK) << DMA_CH0_TRANSFER_WIDTH_OFFS)
+
+#define DMA_CH0_TRANSFER_SEG_LENGTH_OFFS 2
+#define DMA_CH0_TRANSFER_SEG_LENGTH_MASK 0x3ff
+#define DMA_CH0_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH0_TRANSFER_SEG_LENGTH_MASK) << DMA_CH0_TRANSFER_SEG_LENGTH_OFFS)
+
+#define DMA_CH0_TRANSFER_SEG_COUNT_OFFS 12
+#define DMA_CH0_TRANSFER_SEG_COUNT_MASK 0xfffff
+#define DMA_CH0_TRANSFER_SEG_COUNT(V) ((V & DMA_CH0_TRANSFER_SEG_COUNT_MASK) << DMA_CH0_TRANSFER_SEG_COUNT_OFFS)
+
+#define DMA_CH0_SRC_START_ADDR_OFFS 0
+#define DMA_CH0_SRC_START_ADDR_MASK 0xffffffff
+#define DMA_CH0_SRC_START_ADDR(V) ((V & DMA_CH0_SRC_START_ADDR_MASK) << DMA_CH0_SRC_START_ADDR_OFFS)
+
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS 0
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
+#define DMA_CH0_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STEP_OFFS)
+
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
+#define DMA_CH0_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH0_SRC_ADDR_INC_SRC_STRIDE_OFFS)
+
+#define DMA_CH0_DST_START_ADDR_OFFS 0
+#define DMA_CH0_DST_START_ADDR_MASK 0xffffffff
+#define DMA_CH0_DST_START_ADDR(V) ((V & DMA_CH0_DST_START_ADDR_MASK) << DMA_CH0_DST_START_ADDR_OFFS)
+
+#define DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS 0
+#define DMA_CH0_DST_ADDR_INC_DST_STEP_MASK 0xfff
+#define DMA_CH0_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH0_DST_ADDR_INC_DST_STEP_OFFS)
+
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS 12
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
+#define DMA_CH0_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH0_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH0_DST_ADDR_INC_DST_STRIDE_OFFS)
+
+#define DMA_CH1_EVENT_SELECT_OFFS 0
+#define DMA_CH1_EVENT_SELECT_MASK 0x1f
+#define DMA_CH1_EVENT_SELECT(V) ((V & DMA_CH1_EVENT_SELECT_MASK) << DMA_CH1_EVENT_SELECT_OFFS)
+
+#define DMA_CH1_EVENT_COMBINE_OFFS 31
+#define DMA_CH1_EVENT_COMBINE_MASK 0x1
+#define DMA_CH1_EVENT_COMBINE(V) ((V & DMA_CH1_EVENT_COMBINE_MASK) << DMA_CH1_EVENT_COMBINE_OFFS)
+
+#define DMA_CH1_TRANSFER_WIDTH_OFFS 0
+#define DMA_CH1_TRANSFER_WIDTH_MASK 0x3
+#define DMA_CH1_TRANSFER_WIDTH(V) ((V & DMA_CH1_TRANSFER_WIDTH_MASK) << DMA_CH1_TRANSFER_WIDTH_OFFS)
+
+#define DMA_CH1_TRANSFER_SEG_LENGTH_OFFS 2
+#define DMA_CH1_TRANSFER_SEG_LENGTH_MASK 0x3ff
+#define DMA_CH1_TRANSFER_SEG_LENGTH(V) ((V & DMA_CH1_TRANSFER_SEG_LENGTH_MASK) << DMA_CH1_TRANSFER_SEG_LENGTH_OFFS)
+
+#define DMA_CH1_TRANSFER_SEG_COUNT_OFFS 12
+#define DMA_CH1_TRANSFER_SEG_COUNT_MASK 0xfffff
+#define DMA_CH1_TRANSFER_SEG_COUNT(V) ((V & DMA_CH1_TRANSFER_SEG_COUNT_MASK) << DMA_CH1_TRANSFER_SEG_COUNT_OFFS)
+
+#define DMA_CH1_SRC_START_ADDR_OFFS 0
+#define DMA_CH1_SRC_START_ADDR_MASK 0xffffffff
+#define DMA_CH1_SRC_START_ADDR(V) ((V & DMA_CH1_SRC_START_ADDR_MASK) << DMA_CH1_SRC_START_ADDR_OFFS)
+
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS 0
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK 0xfff
+#define DMA_CH1_SRC_ADDR_INC_SRC_STEP(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STEP_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STEP_OFFS)
+
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS 12
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK 0xfffff
+#define DMA_CH1_SRC_ADDR_INC_SRC_STRIDE(V) ((V & DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_MASK) << DMA_CH1_SRC_ADDR_INC_SRC_STRIDE_OFFS)
+
+#define DMA_CH1_DST_START_ADDR_OFFS 0
+#define DMA_CH1_DST_START_ADDR_MASK 0xffffffff
+#define DMA_CH1_DST_START_ADDR(V) ((V & DMA_CH1_DST_START_ADDR_MASK) << DMA_CH1_DST_START_ADDR_OFFS)
+
+#define DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS 0
+#define DMA_CH1_DST_ADDR_INC_DST_STEP_MASK 0xfff
+#define DMA_CH1_DST_ADDR_INC_DST_STEP(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STEP_MASK) << DMA_CH1_DST_ADDR_INC_DST_STEP_OFFS)
+
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS 12
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK 0xfffff
+#define DMA_CH1_DST_ADDR_INC_DST_STRIDE(V) ((V & DMA_CH1_DST_ADDR_INC_DST_STRIDE_MASK) << DMA_CH1_DST_ADDR_INC_DST_STRIDE_OFFS)
+
+//DMA_CONTROL
+inline uint32_t get_dma_control(volatile dma_t* reg){
+     return reg->CONTROL;
+}
+inline void set_dma_control(volatile dma_t* reg, uint32_t value){
+     reg->CONTROL = value;
+}
+inline uint32_t get_dma_control_ch0_enable_transfer(volatile dma_t* reg){
+    return (reg->CONTROL >> 0) & 0x1;
+}
+inline void set_dma_control_ch0_enable_transfer(volatile dma_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_control_ch1_enable_transfer(volatile dma_t* reg){
+    return (reg->CONTROL >> 1) & 0x1;
+}
+inline void set_dma_control_ch1_enable_transfer(volatile dma_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 1)) | (value << 1);
+}
+
+//DMA_STATUS
+inline uint32_t get_dma_status(volatile dma_t* reg){
+     return reg->STATUS;
+}
+inline uint32_t get_dma_status_ch0_busy(volatile dma_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+inline uint32_t get_dma_status_ch1_busy(volatile dma_t* reg){
+    return (reg->STATUS >> 1) & 0x1;
+}
+
+//DMA_IE
+inline uint32_t get_dma_ie(volatile dma_t* reg){
+     return reg->IE;
+}
+inline void set_dma_ie(volatile dma_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_dma_ie_ch0_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_dma_ie_ch0_ie_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 2) & 0x1;
+}
+inline void set_dma_ie_ch1_ie_seg_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg){
+    return (reg->IE >> 3) & 0x1;
+}
+inline void set_dma_ie_ch1_ie_transfer_done(volatile dma_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 3)) | (value << 3);
+}
+
+//DMA_IP
+inline uint32_t get_dma_ip(volatile dma_t* reg){
+     return reg->IP;
+}
+inline uint32_t get_dma_ip_ch0_ip_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline uint32_t get_dma_ip_ch0_ip_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+inline uint32_t get_dma_ip_ch1_ip_seg_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 2) & 0x1;
+}
+inline uint32_t get_dma_ip_ch1_ip_transfer_done(volatile dma_t* reg){
+    return (reg->IP >> 3) & 0x1;
+}
+
+//DMA_CH0_EVENT
+inline uint32_t get_dma_ch0_event(volatile dma_t* reg){
+     return reg->CH0_EVENT;
+}
+inline void set_dma_ch0_event(volatile dma_t* reg, uint32_t value){
+     reg->CH0_EVENT = value;
+}
+inline uint32_t get_dma_ch0_event_select(volatile dma_t* reg){
+    return (reg->CH0_EVENT >> 0) & 0x1f;
+}
+inline void set_dma_ch0_event_select(volatile dma_t* reg, uint8_t value){
+    reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1fU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_event_combine(volatile dma_t* reg){
+    return (reg->CH0_EVENT >> 31) & 0x1;
+}
+inline void set_dma_ch0_event_combine(volatile dma_t* reg, uint8_t value){
+    reg->CH0_EVENT = (reg->CH0_EVENT & ~(0x1U << 31)) | (value << 31);
+}
+
+//DMA_CH0_TRANSFER
+inline uint32_t get_dma_ch0_transfer(volatile dma_t* reg){
+     return reg->CH0_TRANSFER;
+}
+inline void set_dma_ch0_transfer(volatile dma_t* reg, uint32_t value){
+     reg->CH0_TRANSFER = value;
+}
+inline uint32_t get_dma_ch0_transfer_width(volatile dma_t* reg){
+    return (reg->CH0_TRANSFER >> 0) & 0x3;
+}
+inline void set_dma_ch0_transfer_width(volatile dma_t* reg, uint8_t value){
+    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_transfer_seg_length(volatile dma_t* reg){
+    return (reg->CH0_TRANSFER >> 2) & 0x3ff;
+}
+inline void set_dma_ch0_transfer_seg_length(volatile dma_t* reg, uint16_t value){
+    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
+}
+inline uint32_t get_dma_ch0_transfer_seg_count(volatile dma_t* reg){
+    return (reg->CH0_TRANSFER >> 12) & 0xfffff;
+}
+inline void set_dma_ch0_transfer_seg_count(volatile dma_t* reg, uint32_t value){
+    reg->CH0_TRANSFER = (reg->CH0_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH0_SRC_START_ADDR
+inline uint32_t get_dma_ch0_src_start_addr(volatile dma_t* reg){
+    return (reg->CH0_SRC_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch0_src_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH0_SRC_START_ADDR = (reg->CH0_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH0_SRC_ADDR_INC
+inline uint32_t get_dma_ch0_src_addr_inc(volatile dma_t* reg){
+     return reg->CH0_SRC_ADDR_INC;
+}
+inline void set_dma_ch0_src_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH0_SRC_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg){
+    return (reg->CH0_SRC_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch0_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
+    reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg){
+    return (reg->CH0_SRC_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch0_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH0_SRC_ADDR_INC = (reg->CH0_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH0_DST_START_ADDR
+inline uint32_t get_dma_ch0_dst_start_addr(volatile dma_t* reg){
+    return (reg->CH0_DST_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch0_dst_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH0_DST_START_ADDR = (reg->CH0_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH0_DST_ADDR_INC
+inline uint32_t get_dma_ch0_dst_addr_inc(volatile dma_t* reg){
+     return reg->CH0_DST_ADDR_INC;
+}
+inline void set_dma_ch0_dst_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH0_DST_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg){
+    return (reg->CH0_DST_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch0_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
+    reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg){
+    return (reg->CH0_DST_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch0_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH0_DST_ADDR_INC = (reg->CH0_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH1_EVENT
+inline uint32_t get_dma_ch1_event(volatile dma_t* reg){
+     return reg->CH1_EVENT;
+}
+inline void set_dma_ch1_event(volatile dma_t* reg, uint32_t value){
+     reg->CH1_EVENT = value;
+}
+inline uint32_t get_dma_ch1_event_select(volatile dma_t* reg){
+    return (reg->CH1_EVENT >> 0) & 0x1f;
+}
+inline void set_dma_ch1_event_select(volatile dma_t* reg, uint8_t value){
+    reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1fU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_event_combine(volatile dma_t* reg){
+    return (reg->CH1_EVENT >> 31) & 0x1;
+}
+inline void set_dma_ch1_event_combine(volatile dma_t* reg, uint8_t value){
+    reg->CH1_EVENT = (reg->CH1_EVENT & ~(0x1U << 31)) | (value << 31);
+}
+
+//DMA_CH1_TRANSFER
+inline uint32_t get_dma_ch1_transfer(volatile dma_t* reg){
+     return reg->CH1_TRANSFER;
+}
+inline void set_dma_ch1_transfer(volatile dma_t* reg, uint32_t value){
+     reg->CH1_TRANSFER = value;
+}
+inline uint32_t get_dma_ch1_transfer_width(volatile dma_t* reg){
+    return (reg->CH1_TRANSFER >> 0) & 0x3;
+}
+inline void set_dma_ch1_transfer_width(volatile dma_t* reg, uint8_t value){
+    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_transfer_seg_length(volatile dma_t* reg){
+    return (reg->CH1_TRANSFER >> 2) & 0x3ff;
+}
+inline void set_dma_ch1_transfer_seg_length(volatile dma_t* reg, uint16_t value){
+    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0x3ffU << 2)) | (value << 2);
+}
+inline uint32_t get_dma_ch1_transfer_seg_count(volatile dma_t* reg){
+    return (reg->CH1_TRANSFER >> 12) & 0xfffff;
+}
+inline void set_dma_ch1_transfer_seg_count(volatile dma_t* reg, uint32_t value){
+    reg->CH1_TRANSFER = (reg->CH1_TRANSFER & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH1_SRC_START_ADDR
+inline uint32_t get_dma_ch1_src_start_addr(volatile dma_t* reg){
+    return (reg->CH1_SRC_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch1_src_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH1_SRC_START_ADDR = (reg->CH1_SRC_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH1_SRC_ADDR_INC
+inline uint32_t get_dma_ch1_src_addr_inc(volatile dma_t* reg){
+     return reg->CH1_SRC_ADDR_INC;
+}
+inline void set_dma_ch1_src_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH1_SRC_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg){
+    return (reg->CH1_SRC_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch1_src_addr_inc_src_step(volatile dma_t* reg, uint16_t value){
+    reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg){
+    return (reg->CH1_SRC_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch1_src_addr_inc_src_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH1_SRC_ADDR_INC = (reg->CH1_SRC_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+//DMA_CH1_DST_START_ADDR
+inline uint32_t get_dma_ch1_dst_start_addr(volatile dma_t* reg){
+    return (reg->CH1_DST_START_ADDR >> 0) & 0xffffffff;
+}
+inline void set_dma_ch1_dst_start_addr(volatile dma_t* reg, uint32_t value){
+    reg->CH1_DST_START_ADDR = (reg->CH1_DST_START_ADDR & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//DMA_CH1_DST_ADDR_INC
+inline uint32_t get_dma_ch1_dst_addr_inc(volatile dma_t* reg){
+     return reg->CH1_DST_ADDR_INC;
+}
+inline void set_dma_ch1_dst_addr_inc(volatile dma_t* reg, uint32_t value){
+     reg->CH1_DST_ADDR_INC = value;
+}
+inline uint32_t get_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg){
+    return (reg->CH1_DST_ADDR_INC >> 0) & 0xfff;
+}
+inline void set_dma_ch1_dst_addr_inc_dst_step(volatile dma_t* reg, uint16_t value){
+    reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffU << 0)) | (value << 0);
+}
+inline uint32_t get_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg){
+    return (reg->CH1_DST_ADDR_INC >> 12) & 0xfffff;
+}
+inline void set_dma_ch1_dst_addr_inc_dst_stride(volatile dma_t* reg, uint32_t value){
+    reg->CH1_DST_ADDR_INC = (reg->CH1_DST_ADDR_INC & ~(0xfffffU << 12)) | (value << 12);
+}
+
+#endif /* _BSP_DMA_H */
--- a/include/minres/devices/gen/gpio.h
+++ b/include/minres/devices/gen/gpio.h
@ -0,0 +1,119 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-09 14:18:51 UTC 
+* by peakrdl_mnrs version 1.2.8
+*/
+
+#ifndef _BSP_GPIO_H
+#define _BSP_GPIO_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t VALUE;
+    volatile uint32_t WRITE;
+    volatile uint32_t WRITEENABLE;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+    volatile uint32_t IRQ_TRIGGER;
+    volatile uint32_t IRQ_TYPE;
+    volatile uint32_t BOOT_SEL;
+}gpio_t;
+
+#define GPIO_VALUE_OFFS 0
+#define GPIO_VALUE_MASK 0xffffffff
+#define GPIO_VALUE(V) ((V & GPIO_VALUE_MASK) << GPIO_VALUE_OFFS)
+
+#define GPIO_WRITE_OFFS 0
+#define GPIO_WRITE_MASK 0xffffffff
+#define GPIO_WRITE(V) ((V & GPIO_WRITE_MASK) << GPIO_WRITE_OFFS)
+
+#define GPIO_WRITEENABLE_OFFS 0
+#define GPIO_WRITEENABLE_MASK 0xffffffff
+#define GPIO_WRITEENABLE(V) ((V & GPIO_WRITEENABLE_MASK) << GPIO_WRITEENABLE_OFFS)
+
+#define GPIO_IE_OFFS 0
+#define GPIO_IE_MASK 0xffffffff
+#define GPIO_IE(V) ((V & GPIO_IE_MASK) << GPIO_IE_OFFS)
+
+#define GPIO_IP_OFFS 0
+#define GPIO_IP_MASK 0xffffffff
+#define GPIO_IP(V) ((V & GPIO_IP_MASK) << GPIO_IP_OFFS)
+
+#define GPIO_IRQ_TRIGGER_OFFS 0
+#define GPIO_IRQ_TRIGGER_MASK 0xffffffff
+#define GPIO_IRQ_TRIGGER(V) ((V & GPIO_IRQ_TRIGGER_MASK) << GPIO_IRQ_TRIGGER_OFFS)
+
+#define GPIO_IRQ_TYPE_OFFS 0
+#define GPIO_IRQ_TYPE_MASK 0xffffffff
+#define GPIO_IRQ_TYPE(V) ((V & GPIO_IRQ_TYPE_MASK) << GPIO_IRQ_TYPE_OFFS)
+
+#define GPIO_BOOT_SEL_OFFS 0
+#define GPIO_BOOT_SEL_MASK 0x7
+#define GPIO_BOOT_SEL(V) ((V & GPIO_BOOT_SEL_MASK) << GPIO_BOOT_SEL_OFFS)
+
+//GPIO_VALUE
+inline uint32_t get_gpio_value(volatile gpio_t* reg){
+    return (reg->VALUE >> 0) & 0xffffffff;
+}
+
+//GPIO_WRITE
+inline uint32_t get_gpio_write(volatile gpio_t* reg){
+    return (reg->WRITE >> 0) & 0xffffffff;
+}
+inline void set_gpio_write(volatile gpio_t* reg, uint32_t value){
+    reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_WRITEENABLE
+inline uint32_t get_gpio_writeEnable(volatile gpio_t* reg){
+    return (reg->WRITEENABLE >> 0) & 0xffffffff;
+}
+inline void set_gpio_writeEnable(volatile gpio_t* reg, uint32_t value){
+    reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_IE
+inline uint32_t get_gpio_ie(volatile gpio_t* reg){
+    return (reg->IE >> 0) & 0xffffffff;
+}
+inline void set_gpio_ie(volatile gpio_t* reg, uint32_t value){
+    reg->IE = (reg->IE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_IP
+inline uint32_t get_gpio_ip(volatile gpio_t* reg){
+    return (reg->IP >> 0) & 0xffffffff;
+}
+inline void set_gpio_ip(volatile gpio_t* reg, uint32_t value){
+    reg->IP = (reg->IP & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_IRQ_TRIGGER
+inline uint32_t get_gpio_irq_trigger(volatile gpio_t* reg){
+    return (reg->IRQ_TRIGGER >> 0) & 0xffffffff;
+}
+inline void set_gpio_irq_trigger(volatile gpio_t* reg, uint32_t value){
+    reg->IRQ_TRIGGER = (reg->IRQ_TRIGGER & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_IRQ_TYPE
+inline uint32_t get_gpio_irq_type(volatile gpio_t* reg){
+    return (reg->IRQ_TYPE >> 0) & 0xffffffff;
+}
+inline void set_gpio_irq_type(volatile gpio_t* reg, uint32_t value){
+    reg->IRQ_TYPE = (reg->IRQ_TYPE & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//GPIO_BOOT_SEL
+inline uint32_t get_gpio_boot_sel(volatile gpio_t* reg){
+     return reg->BOOT_SEL;
+}
+inline uint32_t get_gpio_boot_sel_bootSel(volatile gpio_t* reg){
+    return (reg->BOOT_SEL >> 0) & 0x7;
+}
+
+#endif /* _BSP_GPIO_H */
--- a/include/minres/devices/gen/i2s.h
+++ b/include/minres/devices/gen/i2s.h
@ -0,0 +1,228 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-09-10 14:29:50 UTC 
+* by peakrdl_mnrs version 1.2.9
+*/
+
+#ifndef _BSP_I2S_H
+#define _BSP_I2S_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t LEFT_CH;
+    volatile uint32_t RIGHT_CH;
+    volatile uint32_t CONTROL;
+    volatile uint32_t STATUS;
+    volatile uint32_t I2S_CLOCK_CTRL;
+    volatile uint32_t PDM_CLOCK_CTRL;
+    volatile uint32_t IE;
+    volatile uint32_t IP;
+}i2s_t;
+
+#define I2S_LEFT_CH_OFFS 0
+#define I2S_LEFT_CH_MASK 0xffffffff
+#define I2S_LEFT_CH(V) ((V & I2S_LEFT_CH_MASK) << I2S_LEFT_CH_OFFS)
+
+#define I2S_RIGHT_CH_OFFS 0
+#define I2S_RIGHT_CH_MASK 0xffffffff
+#define I2S_RIGHT_CH(V) ((V & I2S_RIGHT_CH_MASK) << I2S_RIGHT_CH_OFFS)
+
+#define I2S_CONTROL_MODE_OFFS 0
+#define I2S_CONTROL_MODE_MASK 0x3
+#define I2S_CONTROL_MODE(V) ((V & I2S_CONTROL_MODE_MASK) << I2S_CONTROL_MODE_OFFS)
+
+#define I2S_CONTROL_DISABLE_LEFT_OFFS 2
+#define I2S_CONTROL_DISABLE_LEFT_MASK 0x1
+#define I2S_CONTROL_DISABLE_LEFT(V) ((V & I2S_CONTROL_DISABLE_LEFT_MASK) << I2S_CONTROL_DISABLE_LEFT_OFFS)
+
+#define I2S_CONTROL_DISABLE_RIGHT_OFFS 3
+#define I2S_CONTROL_DISABLE_RIGHT_MASK 0x1
+#define I2S_CONTROL_DISABLE_RIGHT(V) ((V & I2S_CONTROL_DISABLE_RIGHT_MASK) << I2S_CONTROL_DISABLE_RIGHT_OFFS)
+
+#define I2S_CONTROL_IS_MASTER_OFFS 4
+#define I2S_CONTROL_IS_MASTER_MASK 0x1
+#define I2S_CONTROL_IS_MASTER(V) ((V & I2S_CONTROL_IS_MASTER_MASK) << I2S_CONTROL_IS_MASTER_OFFS)
+
+#define I2S_CONTROL_SAMPLE_SIZE_OFFS 5
+#define I2S_CONTROL_SAMPLE_SIZE_MASK 0x3
+#define I2S_CONTROL_SAMPLE_SIZE(V) ((V & I2S_CONTROL_SAMPLE_SIZE_MASK) << I2S_CONTROL_SAMPLE_SIZE_OFFS)
+
+#define I2S_CONTROL_PDM_SCALE_OFFS 7
+#define I2S_CONTROL_PDM_SCALE_MASK 0x7
+#define I2S_CONTROL_PDM_SCALE(V) ((V & I2S_CONTROL_PDM_SCALE_MASK) << I2S_CONTROL_PDM_SCALE_OFFS)
+
+#define I2S_STATUS_ENABLED_OFFS 0
+#define I2S_STATUS_ENABLED_MASK 0x1
+#define I2S_STATUS_ENABLED(V) ((V & I2S_STATUS_ENABLED_MASK) << I2S_STATUS_ENABLED_OFFS)
+
+#define I2S_STATUS_ACTIVE_OFFS 1
+#define I2S_STATUS_ACTIVE_MASK 0x1
+#define I2S_STATUS_ACTIVE(V) ((V & I2S_STATUS_ACTIVE_MASK) << I2S_STATUS_ACTIVE_OFFS)
+
+#define I2S_STATUS_LEFT_AVAIL_OFFS 2
+#define I2S_STATUS_LEFT_AVAIL_MASK 0x1
+#define I2S_STATUS_LEFT_AVAIL(V) ((V & I2S_STATUS_LEFT_AVAIL_MASK) << I2S_STATUS_LEFT_AVAIL_OFFS)
+
+#define I2S_STATUS_RIGHT_AVAIL_OFFS 3
+#define I2S_STATUS_RIGHT_AVAIL_MASK 0x1
+#define I2S_STATUS_RIGHT_AVAIL(V) ((V & I2S_STATUS_RIGHT_AVAIL_MASK) << I2S_STATUS_RIGHT_AVAIL_OFFS)
+
+#define I2S_I2S_CLOCK_CTRL_OFFS 0
+#define I2S_I2S_CLOCK_CTRL_MASK 0xfffff
+#define I2S_I2S_CLOCK_CTRL(V) ((V & I2S_I2S_CLOCK_CTRL_MASK) << I2S_I2S_CLOCK_CTRL_OFFS)
+
+#define I2S_PDM_CLOCK_CTRL_OFFS 0
+#define I2S_PDM_CLOCK_CTRL_MASK 0x3ff
+#define I2S_PDM_CLOCK_CTRL(V) ((V & I2S_PDM_CLOCK_CTRL_MASK) << I2S_PDM_CLOCK_CTRL_OFFS)
+
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_LEFT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IE_EN_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IE_EN_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IE_EN_RIGHT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_LEFT_SAMPLE_AVAIL_OFFS 0
+#define I2S_IP_LEFT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_LEFT_SAMPLE_AVAIL(V) ((V & I2S_IP_LEFT_SAMPLE_AVAIL_MASK) << I2S_IP_LEFT_SAMPLE_AVAIL_OFFS)
+
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS 1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL_MASK 0x1
+#define I2S_IP_RIGHT_SAMPLE_AVAIL(V) ((V & I2S_IP_RIGHT_SAMPLE_AVAIL_MASK) << I2S_IP_RIGHT_SAMPLE_AVAIL_OFFS)
+
+//I2S_LEFT_CH
+inline uint32_t get_i2s_left_ch(volatile i2s_t* reg){
+    return (reg->LEFT_CH >> 0) & 0xffffffff;
+}
+
+//I2S_RIGHT_CH
+inline uint32_t get_i2s_right_ch(volatile i2s_t* reg){
+    return (reg->RIGHT_CH >> 0) & 0xffffffff;
+}
+
+//I2S_CONTROL
+inline uint32_t get_i2s_control(volatile i2s_t* reg){
+     return reg->CONTROL;
+}
+inline void set_i2s_control(volatile i2s_t* reg, uint32_t value){
+     reg->CONTROL = value;
+}
+inline uint32_t get_i2s_control_mode(volatile i2s_t* reg){
+    return (reg->CONTROL >> 0) & 0x3;
+}
+inline void set_i2s_control_mode(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x3U << 0)) | (value << 0);
+}
+inline uint32_t get_i2s_control_disable_left(volatile i2s_t* reg){
+    return (reg->CONTROL >> 2) & 0x1;
+}
+inline void set_i2s_control_disable_left(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_i2s_control_disable_right(volatile i2s_t* reg){
+    return (reg->CONTROL >> 3) & 0x1;
+}
+inline void set_i2s_control_disable_right(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 3)) | (value << 3);
+}
+inline uint32_t get_i2s_control_is_master(volatile i2s_t* reg){
+    return (reg->CONTROL >> 4) & 0x1;
+}
+inline void set_i2s_control_is_master(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x1U << 4)) | (value << 4);
+}
+inline uint32_t get_i2s_control_sample_size(volatile i2s_t* reg){
+    return (reg->CONTROL >> 5) & 0x3;
+}
+inline void set_i2s_control_sample_size(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x3U << 5)) | (value << 5);
+}
+inline uint32_t get_i2s_control_pdm_scale(volatile i2s_t* reg){
+    return (reg->CONTROL >> 7) & 0x7;
+}
+inline void set_i2s_control_pdm_scale(volatile i2s_t* reg, uint8_t value){
+    reg->CONTROL = (reg->CONTROL & ~(0x7U << 7)) | (value << 7);
+}
+
+//I2S_STATUS
+inline uint32_t get_i2s_status(volatile i2s_t* reg){
+     return reg->STATUS;
+}
+inline uint32_t get_i2s_status_enabled(volatile i2s_t* reg){
+    return (reg->STATUS >> 0) & 0x1;
+}
+inline uint32_t get_i2s_status_active(volatile i2s_t* reg){
+    return (reg->STATUS >> 1) & 0x1;
+}
+inline uint32_t get_i2s_status_left_avail(volatile i2s_t* reg){
+    return (reg->STATUS >> 2) & 0x1;
+}
+inline uint32_t get_i2s_status_right_avail(volatile i2s_t* reg){
+    return (reg->STATUS >> 3) & 0x1;
+}
+
+//I2S_I2S_CLOCK_CTRL
+inline uint32_t get_i2s_i2s_clock_ctrl(volatile i2s_t* reg){
+     return reg->I2S_CLOCK_CTRL;
+}
+inline void set_i2s_i2s_clock_ctrl(volatile i2s_t* reg, uint32_t value){
+     reg->I2S_CLOCK_CTRL = value;
+}
+inline uint32_t get_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg){
+    return (reg->I2S_CLOCK_CTRL >> 0) & 0xfffff;
+}
+inline void set_i2s_i2s_clock_ctrl_divider(volatile i2s_t* reg, uint32_t value){
+    reg->I2S_CLOCK_CTRL = (reg->I2S_CLOCK_CTRL & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//I2S_PDM_CLOCK_CTRL
+inline uint32_t get_i2s_pdm_clock_ctrl(volatile i2s_t* reg){
+     return reg->PDM_CLOCK_CTRL;
+}
+inline void set_i2s_pdm_clock_ctrl(volatile i2s_t* reg, uint32_t value){
+     reg->PDM_CLOCK_CTRL = value;
+}
+inline uint32_t get_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg){
+    return (reg->PDM_CLOCK_CTRL >> 0) & 0x3ff;
+}
+inline void set_i2s_pdm_clock_ctrl_divider(volatile i2s_t* reg, uint16_t value){
+    reg->PDM_CLOCK_CTRL = (reg->PDM_CLOCK_CTRL & ~(0x3ffU << 0)) | (value << 0);
+}
+
+//I2S_IE
+inline uint32_t get_i2s_ie(volatile i2s_t* reg){
+     return reg->IE;
+}
+inline void set_i2s_ie(volatile i2s_t* reg, uint32_t value){
+     reg->IE = value;
+}
+inline uint32_t get_i2s_ie_en_left_sample_avail(volatile i2s_t* reg){
+    return (reg->IE >> 0) & 0x1;
+}
+inline void set_i2s_ie_en_left_sample_avail(volatile i2s_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_i2s_ie_en_right_sample_avail(volatile i2s_t* reg){
+    return (reg->IE >> 1) & 0x1;
+}
+inline void set_i2s_ie_en_right_sample_avail(volatile i2s_t* reg, uint8_t value){
+    reg->IE = (reg->IE & ~(0x1U << 1)) | (value << 1);
+}
+
+//I2S_IP
+inline uint32_t get_i2s_ip(volatile i2s_t* reg){
+     return reg->IP;
+}
+inline uint32_t get_i2s_ip_left_sample_avail(volatile i2s_t* reg){
+    return (reg->IP >> 0) & 0x1;
+}
+inline uint32_t get_i2s_ip_right_sample_avail(volatile i2s_t* reg){
+    return (reg->IP >> 1) & 0x1;
+}
+
+#endif /* _BSP_I2S_H */
--- a/include/minres/devices/gen/msgif.h
+++ b/include/minres/devices/gen/msgif.h
@ -0,0 +1,197 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-11-05 12:12:15 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_MSGIF_H
+#define _BSP_MSGIF_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t REG_SEND;
+    volatile uint32_t REG_HEADER;
+    volatile uint32_t REG_ACK;
+    volatile uint32_t REG_RECV_ID;
+    volatile uint32_t REG_RECV_PAYLOAD;
+    uint8_t fill0[12];
+    volatile uint32_t REG_PAYLOAD_0;
+    volatile uint32_t REG_PAYLOAD_1;
+    volatile uint32_t REG_PAYLOAD_2;
+    volatile uint32_t REG_PAYLOAD_3;
+    volatile uint32_t REG_PAYLOAD_4;
+    volatile uint32_t REG_PAYLOAD_5;
+    volatile uint32_t REG_PAYLOAD_6;
+    volatile uint32_t REG_PAYLOAD_7;
+}msgif_t;
+
+#define MSGIF_REG_SEND_OFFS 0
+#define MSGIF_REG_SEND_MASK 0x1
+#define MSGIF_REG_SEND(V) ((V & MSGIF_REG_SEND_MASK) << MSGIF_REG_SEND_OFFS)
+
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS 0
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK 0x7
+#define MSGIF_REG_HEADER_RECIPIENT_COMPONENT(V) ((V & MSGIF_REG_HEADER_RECIPIENT_COMPONENT_MASK) << MSGIF_REG_HEADER_RECIPIENT_COMPONENT_OFFS)
+
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS 3
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK 0x3
+#define MSGIF_REG_HEADER_RECIPIENT_CLUSTER(V) ((V & MSGIF_REG_HEADER_RECIPIENT_CLUSTER_MASK) << MSGIF_REG_HEADER_RECIPIENT_CLUSTER_OFFS)
+
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS 5
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK 0xf
+#define MSGIF_REG_HEADER_MESSAGE_LENGTH(V) ((V & MSGIF_REG_HEADER_MESSAGE_LENGTH_MASK) << MSGIF_REG_HEADER_MESSAGE_LENGTH_OFFS)
+
+#define MSGIF_REG_HEADER_MESSAGE_ID_OFFS 9
+#define MSGIF_REG_HEADER_MESSAGE_ID_MASK 0xf
+#define MSGIF_REG_HEADER_MESSAGE_ID(V) ((V & MSGIF_REG_HEADER_MESSAGE_ID_MASK) << MSGIF_REG_HEADER_MESSAGE_ID_OFFS)
+
+#define MSGIF_REG_ACK_OFFS 0
+#define MSGIF_REG_ACK_MASK 0x1
+#define MSGIF_REG_ACK(V) ((V & MSGIF_REG_ACK_MASK) << MSGIF_REG_ACK_OFFS)
+
+#define MSGIF_REG_RECV_ID_OFFS 0
+#define MSGIF_REG_RECV_ID_MASK 0xf
+#define MSGIF_REG_RECV_ID(V) ((V & MSGIF_REG_RECV_ID_MASK) << MSGIF_REG_RECV_ID_OFFS)
+
+#define MSGIF_REG_RECV_PAYLOAD_OFFS 0
+#define MSGIF_REG_RECV_PAYLOAD_MASK 0xffffffff
+#define MSGIF_REG_RECV_PAYLOAD(V) ((V & MSGIF_REG_RECV_PAYLOAD_MASK) << MSGIF_REG_RECV_PAYLOAD_OFFS)
+
+#define MSGIF_REG_PAYLOAD_0_OFFS 0
+#define MSGIF_REG_PAYLOAD_0_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_0(V) ((V & MSGIF_REG_PAYLOAD_0_MASK) << MSGIF_REG_PAYLOAD_0_OFFS)
+
+#define MSGIF_REG_PAYLOAD_1_OFFS 0
+#define MSGIF_REG_PAYLOAD_1_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_1(V) ((V & MSGIF_REG_PAYLOAD_1_MASK) << MSGIF_REG_PAYLOAD_1_OFFS)
+
+#define MSGIF_REG_PAYLOAD_2_OFFS 0
+#define MSGIF_REG_PAYLOAD_2_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_2(V) ((V & MSGIF_REG_PAYLOAD_2_MASK) << MSGIF_REG_PAYLOAD_2_OFFS)
+
+#define MSGIF_REG_PAYLOAD_3_OFFS 0
+#define MSGIF_REG_PAYLOAD_3_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_3(V) ((V & MSGIF_REG_PAYLOAD_3_MASK) << MSGIF_REG_PAYLOAD_3_OFFS)
+
+#define MSGIF_REG_PAYLOAD_4_OFFS 0
+#define MSGIF_REG_PAYLOAD_4_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_4(V) ((V & MSGIF_REG_PAYLOAD_4_MASK) << MSGIF_REG_PAYLOAD_4_OFFS)
+
+#define MSGIF_REG_PAYLOAD_5_OFFS 0
+#define MSGIF_REG_PAYLOAD_5_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_5(V) ((V & MSGIF_REG_PAYLOAD_5_MASK) << MSGIF_REG_PAYLOAD_5_OFFS)
+
+#define MSGIF_REG_PAYLOAD_6_OFFS 0
+#define MSGIF_REG_PAYLOAD_6_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_6(V) ((V & MSGIF_REG_PAYLOAD_6_MASK) << MSGIF_REG_PAYLOAD_6_OFFS)
+
+#define MSGIF_REG_PAYLOAD_7_OFFS 0
+#define MSGIF_REG_PAYLOAD_7_MASK 0xffffffff
+#define MSGIF_REG_PAYLOAD_7(V) ((V & MSGIF_REG_PAYLOAD_7_MASK) << MSGIF_REG_PAYLOAD_7_OFFS)
+
+//MSGIF_REG_SEND
+inline void set_msgif_REG_SEND(volatile msgif_t* reg, uint32_t value){
+     reg->REG_SEND = value;
+}
+inline void set_msgif_REG_SEND_SEND(volatile msgif_t* reg, uint8_t value){
+    reg->REG_SEND = (reg->REG_SEND & ~(0x1U << 0)) | (value << 0);
+}
+
+//MSGIF_REG_HEADER
+inline uint32_t get_msgif_REG_HEADER(volatile msgif_t* reg){
+     return reg->REG_HEADER;
+}
+inline void set_msgif_REG_HEADER(volatile msgif_t* reg, uint32_t value){
+     reg->REG_HEADER = value;
+}
+inline uint32_t get_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 0) & 0x7;
+}
+inline void set_msgif_REG_HEADER_RECIPIENT_COMPONENT(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 3) & 0x3;
+}
+inline void set_msgif_REG_HEADER_RECIPIENT_CLUSTER(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0x3U << 3)) | (value << 3);
+}
+inline uint32_t get_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 5) & 0xf;
+}
+inline void set_msgif_REG_HEADER_MESSAGE_LENGTH(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 5)) | (value << 5);
+}
+inline uint32_t get_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg){
+    return (reg->REG_HEADER >> 9) & 0xf;
+}
+inline void set_msgif_REG_HEADER_MESSAGE_ID(volatile msgif_t* reg, uint8_t value){
+    reg->REG_HEADER = (reg->REG_HEADER & ~(0xfU << 9)) | (value << 9);
+}
+
+//MSGIF_REG_ACK
+inline void set_msgif_REG_ACK(volatile msgif_t* reg, uint32_t value){
+     reg->REG_ACK = value;
+}
+inline void set_msgif_REG_ACK_ACK(volatile msgif_t* reg, uint8_t value){
+    reg->REG_ACK = (reg->REG_ACK & ~(0x1U << 0)) | (value << 0);
+}
+
+//MSGIF_REG_RECV_ID
+inline uint32_t get_msgif_REG_RECV_ID(volatile msgif_t* reg){
+     return reg->REG_RECV_ID;
+}
+inline uint32_t get_msgif_REG_RECV_ID_RECV_ID(volatile msgif_t* reg){
+    return (reg->REG_RECV_ID >> 0) & 0xf;
+}
+
+//MSGIF_REG_RECV_PAYLOAD
+inline uint32_t get_msgif_REG_RECV_PAYLOAD(volatile msgif_t* reg){
+    return (reg->REG_RECV_PAYLOAD >> 0) & 0xffffffff;
+}
+
+//MSGIF_REG_PAYLOAD_0
+inline void set_msgif_REG_PAYLOAD_0(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_0 = (reg->REG_PAYLOAD_0 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_1
+inline void set_msgif_REG_PAYLOAD_1(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_1 = (reg->REG_PAYLOAD_1 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_2
+inline void set_msgif_REG_PAYLOAD_2(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_2 = (reg->REG_PAYLOAD_2 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_3
+inline void set_msgif_REG_PAYLOAD_3(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_3 = (reg->REG_PAYLOAD_3 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_4
+inline void set_msgif_REG_PAYLOAD_4(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_4 = (reg->REG_PAYLOAD_4 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_5
+inline void set_msgif_REG_PAYLOAD_5(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_5 = (reg->REG_PAYLOAD_5 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_6
+inline void set_msgif_REG_PAYLOAD_6(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_6 = (reg->REG_PAYLOAD_6 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//MSGIF_REG_PAYLOAD_7
+inline void set_msgif_REG_PAYLOAD_7(volatile msgif_t* reg, uint32_t value){
+    reg->REG_PAYLOAD_7 = (reg->REG_PAYLOAD_7 & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+#endif /* _BSP_MSGIF_H */
--- a/include/minres/devices/gen/timercounter.h
+++ b/include/minres/devices/gen/timercounter.h
@ -0,0 +1,141 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-02 08:46:07 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_TIMERCOUNTER_H
+#define _BSP_TIMERCOUNTER_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t PRESCALER;
+    volatile uint32_t T0_CTRL;
+    volatile uint32_t T0_OVERFLOW;
+    volatile uint32_t T0_VALUE;
+    volatile uint32_t T1_CTRL;
+    volatile uint32_t T1_OVERFLOW;
+    volatile uint32_t T1_VALUE;
+}timercounter_t;
+
+#define TIMERCOUNTER_PRESCALER_OFFS 0
+#define TIMERCOUNTER_PRESCALER_MASK 0xffff
+#define TIMERCOUNTER_PRESCALER(V) ((V & TIMERCOUNTER_PRESCALER_MASK) << TIMERCOUNTER_PRESCALER_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T0_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T0_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T0_CTRL_ENABLE_MASK) << TIMERCOUNTER_T0_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T0_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T0_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T0_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T0_CTRL_CLEAR_MASK) << TIMERCOUNTER_T0_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T0_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T0_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T0_OVERFLOW(V) ((V & TIMERCOUNTER_T0_OVERFLOW_MASK) << TIMERCOUNTER_T0_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T0_VALUE_OFFS 0
+#define TIMERCOUNTER_T0_VALUE_MASK 0xffffffff
+#define TIMERCOUNTER_T0_VALUE(V) ((V & TIMERCOUNTER_T0_VALUE_MASK) << TIMERCOUNTER_T0_VALUE_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_ENABLE_OFFS 0
+#define TIMERCOUNTER_T1_CTRL_ENABLE_MASK 0x7
+#define TIMERCOUNTER_T1_CTRL_ENABLE(V) ((V & TIMERCOUNTER_T1_CTRL_ENABLE_MASK) << TIMERCOUNTER_T1_CTRL_ENABLE_OFFS)
+
+#define TIMERCOUNTER_T1_CTRL_CLEAR_OFFS 3
+#define TIMERCOUNTER_T1_CTRL_CLEAR_MASK 0x3
+#define TIMERCOUNTER_T1_CTRL_CLEAR(V) ((V & TIMERCOUNTER_T1_CTRL_CLEAR_MASK) << TIMERCOUNTER_T1_CTRL_CLEAR_OFFS)
+
+#define TIMERCOUNTER_T1_OVERFLOW_OFFS 0
+#define TIMERCOUNTER_T1_OVERFLOW_MASK 0xffffffff
+#define TIMERCOUNTER_T1_OVERFLOW(V) ((V & TIMERCOUNTER_T1_OVERFLOW_MASK) << TIMERCOUNTER_T1_OVERFLOW_OFFS)
+
+#define TIMERCOUNTER_T1_VALUE_OFFS 0
+#define TIMERCOUNTER_T1_VALUE_MASK 0xffffffff
+#define TIMERCOUNTER_T1_VALUE(V) ((V & TIMERCOUNTER_T1_VALUE_MASK) << TIMERCOUNTER_T1_VALUE_OFFS)
+
+//TIMERCOUNTER_PRESCALER
+inline uint32_t get_timercounter_prescaler(volatile timercounter_t* reg){
+     return reg->PRESCALER;
+}
+inline void set_timercounter_prescaler(volatile timercounter_t* reg, uint32_t value){
+     reg->PRESCALER = value;
+}
+inline uint32_t get_timercounter_prescaler_limit(volatile timercounter_t* reg){
+    return (reg->PRESCALER >> 0) & 0xffff;
+}
+inline void set_timercounter_prescaler_limit(volatile timercounter_t* reg, uint16_t value){
+    reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T0_CTRL
+inline uint32_t get_timercounter_t0_ctrl(volatile timercounter_t* reg){
+     return reg->T0_CTRL;
+}
+inline void set_timercounter_t0_ctrl(volatile timercounter_t* reg, uint32_t value){
+     reg->T0_CTRL = value;
+}
+inline uint32_t get_timercounter_t0_ctrl_enable(volatile timercounter_t* reg){
+    return (reg->T0_CTRL >> 0) & 0x7;
+}
+inline void set_timercounter_t0_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timercounter_t0_ctrl_clear(volatile timercounter_t* reg){
+    return (reg->T0_CTRL >> 3) & 0x3;
+}
+inline void set_timercounter_t0_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
+    reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+//TIMERCOUNTER_T0_OVERFLOW
+inline uint32_t get_timercounter_t0_overflow(volatile timercounter_t* reg){
+    return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timercounter_t0_overflow(volatile timercounter_t* reg, uint32_t value){
+    reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T0_VALUE
+inline uint32_t get_timercounter_t0_value(volatile timercounter_t* reg){
+    return (reg->T0_VALUE >> 0) & 0xffffffff;
+}
+
+//TIMERCOUNTER_T1_CTRL
+inline uint32_t get_timercounter_t1_ctrl(volatile timercounter_t* reg){
+     return reg->T1_CTRL;
+}
+inline void set_timercounter_t1_ctrl(volatile timercounter_t* reg, uint32_t value){
+     reg->T1_CTRL = value;
+}
+inline uint32_t get_timercounter_t1_ctrl_enable(volatile timercounter_t* reg){
+    return (reg->T1_CTRL >> 0) & 0x7;
+}
+inline void set_timercounter_t1_ctrl_enable(volatile timercounter_t* reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_timercounter_t1_ctrl_clear(volatile timercounter_t* reg){
+    return (reg->T1_CTRL >> 3) & 0x3;
+}
+inline void set_timercounter_t1_ctrl_clear(volatile timercounter_t* reg, uint8_t value){
+    reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
+}
+
+//TIMERCOUNTER_T1_OVERFLOW
+inline uint32_t get_timercounter_t1_overflow(volatile timercounter_t* reg){
+    return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
+}
+inline void set_timercounter_t1_overflow(volatile timercounter_t* reg, uint32_t value){
+    reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
+}
+
+//TIMERCOUNTER_T1_VALUE
+inline uint32_t get_timercounter_t1_value(volatile timercounter_t* reg){
+    return (reg->T1_VALUE >> 0) & 0xffffffff;
+}
+
+#endif /* _BSP_TIMERCOUNTER_H */
--- a/include/minres/devices/gen/uart.h
+++ b/include/minres/devices/gen/uart.h
@ -0,0 +1,236 @@
+/*
+* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
+*
+* SPDX-License-Identifier: Apache-2.0
+*
+* Generated at 2024-08-02 08:46:07 UTC 
+* by peakrdl_mnrs version 1.2.7
+*/
+
+#ifndef _BSP_UART_H
+#define _BSP_UART_H
+
+#include <stdint.h>
+
+typedef struct {
+    volatile uint32_t RX_TX_REG;
+    volatile uint32_t INT_CTRL_REG;
+    volatile uint32_t CLK_DIVIDER_REG;
+    volatile uint32_t FRAME_CONFIG_REG;
+    volatile uint32_t STATUS_REG;
+}uart_t;
+
+#define UART_RX_TX_REG_DATA_OFFS 0
+#define UART_RX_TX_REG_DATA_MASK 0xff
+#define UART_RX_TX_REG_DATA(V) ((V & UART_RX_TX_REG_DATA_MASK) << UART_RX_TX_REG_DATA_OFFS)
+
+#define UART_RX_TX_REG_RX_AVAIL_OFFS 14
+#define UART_RX_TX_REG_RX_AVAIL_MASK 0x1
+#define UART_RX_TX_REG_RX_AVAIL(V) ((V & UART_RX_TX_REG_RX_AVAIL_MASK) << UART_RX_TX_REG_RX_AVAIL_OFFS)
+
+#define UART_RX_TX_REG_TX_FREE_OFFS 15
+#define UART_RX_TX_REG_TX_FREE_MASK 0x1
+#define UART_RX_TX_REG_TX_FREE(V) ((V & UART_RX_TX_REG_TX_FREE_MASK) << UART_RX_TX_REG_TX_FREE_OFFS)
+
+#define UART_RX_TX_REG_TX_EMPTY_OFFS 16
+#define UART_RX_TX_REG_TX_EMPTY_MASK 0x1
+#define UART_RX_TX_REG_TX_EMPTY(V) ((V & UART_RX_TX_REG_TX_EMPTY_MASK) << UART_RX_TX_REG_TX_EMPTY_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS 0
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_WRITE_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS 1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_READ_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_READ_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS 2
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_ENABLE(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_ENABLE_MASK) << UART_INT_CTRL_REG_BREAK_INTR_ENABLE_OFFS)
+
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS 8
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_WRITE_INTR_PEND(V) ((V & UART_INT_CTRL_REG_WRITE_INTR_PEND_MASK) << UART_INT_CTRL_REG_WRITE_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_READ_INTR_PEND_OFFS 9
+#define UART_INT_CTRL_REG_READ_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_READ_INTR_PEND(V) ((V & UART_INT_CTRL_REG_READ_INTR_PEND_MASK) << UART_INT_CTRL_REG_READ_INTR_PEND_OFFS)
+
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS 10
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK 0x1
+#define UART_INT_CTRL_REG_BREAK_INTR_PEND(V) ((V & UART_INT_CTRL_REG_BREAK_INTR_PEND_MASK) << UART_INT_CTRL_REG_BREAK_INTR_PEND_OFFS)
+
+#define UART_CLK_DIVIDER_REG_OFFS 0
+#define UART_CLK_DIVIDER_REG_MASK 0xfffff
+#define UART_CLK_DIVIDER_REG(V) ((V & UART_CLK_DIVIDER_REG_MASK) << UART_CLK_DIVIDER_REG_OFFS)
+
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS 0
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK 0x7
+#define UART_FRAME_CONFIG_REG_DATA_LENGTH(V) ((V & UART_FRAME_CONFIG_REG_DATA_LENGTH_MASK) << UART_FRAME_CONFIG_REG_DATA_LENGTH_OFFS)
+
+#define UART_FRAME_CONFIG_REG_PARITY_OFFS 3
+#define UART_FRAME_CONFIG_REG_PARITY_MASK 0x3
+#define UART_FRAME_CONFIG_REG_PARITY(V) ((V & UART_FRAME_CONFIG_REG_PARITY_MASK) << UART_FRAME_CONFIG_REG_PARITY_OFFS)
+
+#define UART_FRAME_CONFIG_REG_STOP_BIT_OFFS 5
+#define UART_FRAME_CONFIG_REG_STOP_BIT_MASK 0x1
+#define UART_FRAME_CONFIG_REG_STOP_BIT(V) ((V & UART_FRAME_CONFIG_REG_STOP_BIT_MASK) << UART_FRAME_CONFIG_REG_STOP_BIT_OFFS)
+
+#define UART_STATUS_REG_READ_ERROR_OFFS 0
+#define UART_STATUS_REG_READ_ERROR_MASK 0x1
+#define UART_STATUS_REG_READ_ERROR(V) ((V & UART_STATUS_REG_READ_ERROR_MASK) << UART_STATUS_REG_READ_ERROR_OFFS)
+
+#define UART_STATUS_REG_STALL_OFFS 1
+#define UART_STATUS_REG_STALL_MASK 0x1
+#define UART_STATUS_REG_STALL(V) ((V & UART_STATUS_REG_STALL_MASK) << UART_STATUS_REG_STALL_OFFS)
+
+#define UART_STATUS_REG_BREAK_LINE_OFFS 8
+#define UART_STATUS_REG_BREAK_LINE_MASK 0x1
+#define UART_STATUS_REG_BREAK_LINE(V) ((V & UART_STATUS_REG_BREAK_LINE_MASK) << UART_STATUS_REG_BREAK_LINE_OFFS)
+
+#define UART_STATUS_REG_BREAK_DETECTED_OFFS 9
+#define UART_STATUS_REG_BREAK_DETECTED_MASK 0x1
+#define UART_STATUS_REG_BREAK_DETECTED(V) ((V & UART_STATUS_REG_BREAK_DETECTED_MASK) << UART_STATUS_REG_BREAK_DETECTED_OFFS)
+
+#define UART_STATUS_REG_SET_BREAK_OFFS 10
+#define UART_STATUS_REG_SET_BREAK_MASK 0x1
+#define UART_STATUS_REG_SET_BREAK(V) ((V & UART_STATUS_REG_SET_BREAK_MASK) << UART_STATUS_REG_SET_BREAK_OFFS)
+
+#define UART_STATUS_REG_CLEAR_BREAK_OFFS 11
+#define UART_STATUS_REG_CLEAR_BREAK_MASK 0x1
+#define UART_STATUS_REG_CLEAR_BREAK(V) ((V & UART_STATUS_REG_CLEAR_BREAK_MASK) << UART_STATUS_REG_CLEAR_BREAK_OFFS)
+
+//UART_RX_TX_REG
+inline uint32_t get_uart_rx_tx_reg(volatile uart_t* reg){
+     return reg->RX_TX_REG;
+}
+inline void set_uart_rx_tx_reg(volatile uart_t* reg, uint32_t value){
+     reg->RX_TX_REG = value;
+}
+inline uint32_t get_uart_rx_tx_reg_data(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 0) & 0xff;
+}
+inline void set_uart_rx_tx_reg_data(volatile uart_t* reg, uint8_t value){
+    reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
+}
+inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 14) & 0x1;
+}
+inline uint32_t get_uart_rx_tx_reg_tx_free(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 15) & 0x1;
+}
+inline uint32_t get_uart_rx_tx_reg_tx_empty(volatile uart_t* reg){
+    return (reg->RX_TX_REG >> 16) & 0x1;
+}
+
+//UART_INT_CTRL_REG
+inline uint32_t get_uart_int_ctrl_reg(volatile uart_t* reg){
+     return reg->INT_CTRL_REG;
+}
+inline void set_uart_int_ctrl_reg(volatile uart_t* reg, uint32_t value){
+     reg->INT_CTRL_REG = value;
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 0) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_write_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 1) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_read_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
+}
+inline uint32_t get_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 2) & 0x1;
+}
+inline void set_uart_int_ctrl_reg_break_intr_enable(volatile uart_t* reg, uint8_t value){
+    reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 2)) | (value << 2);
+}
+inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 9) & 0x1;
+}
+inline uint32_t get_uart_int_ctrl_reg_break_intr_pend(volatile uart_t* reg){
+    return (reg->INT_CTRL_REG >> 10) & 0x1;
+}
+
+//UART_CLK_DIVIDER_REG
+inline uint32_t get_uart_clk_divider_reg(volatile uart_t* reg){
+     return reg->CLK_DIVIDER_REG;
+}
+inline void set_uart_clk_divider_reg(volatile uart_t* reg, uint32_t value){
+     reg->CLK_DIVIDER_REG = value;
+}
+inline uint32_t get_uart_clk_divider_reg_clock_divider(volatile uart_t* reg){
+    return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
+}
+inline void set_uart_clk_divider_reg_clock_divider(volatile uart_t* reg, uint32_t value){
+    reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
+}
+
+//UART_FRAME_CONFIG_REG
+inline uint32_t get_uart_frame_config_reg(volatile uart_t* reg){
+     return reg->FRAME_CONFIG_REG;
+}
+inline void set_uart_frame_config_reg(volatile uart_t* reg, uint32_t value){
+     reg->FRAME_CONFIG_REG = value;
+}
+inline uint32_t get_uart_frame_config_reg_data_length(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
+}
+inline void set_uart_frame_config_reg_data_length(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
+}
+inline uint32_t get_uart_frame_config_reg_parity(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
+}
+inline void set_uart_frame_config_reg_parity(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
+}
+inline uint32_t get_uart_frame_config_reg_stop_bit(volatile uart_t* reg){
+    return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
+}
+inline void set_uart_frame_config_reg_stop_bit(volatile uart_t* reg, uint8_t value){
+    reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
+}
+
+//UART_STATUS_REG
+inline uint32_t get_uart_status_reg(volatile uart_t* reg){
+     return reg->STATUS_REG;
+}
+inline void set_uart_status_reg(volatile uart_t* reg, uint32_t value){
+     reg->STATUS_REG = value;
+}
+inline uint32_t get_uart_status_reg_read_error(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 0) & 0x1;
+}
+inline uint32_t get_uart_status_reg_stall(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 1) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_line(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 8) & 0x1;
+}
+inline uint32_t get_uart_status_reg_break_detected(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 9) & 0x1;
+}
+inline void set_uart_status_reg_break_detected(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
+}
+inline uint32_t get_uart_status_reg_set_break(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 10) & 0x1;
+}
+inline void set_uart_status_reg_set_break(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
+}
+inline uint32_t get_uart_status_reg_clear_break(volatile uart_t* reg){
+    return (reg->STATUS_REG >> 11) & 0x1;
+}
+inline void set_uart_status_reg_clear_break(volatile uart_t* reg, uint8_t value){
+    reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
+}
+
+#endif /* _BSP_UART_H */
--- a/include/minres/devices/gpio.h
+++ b/include/minres/devices/gpio.h
@ -0,0 +1,12 @@
+#ifndef _DEVICES_GPIO_H
+#define _DEVICES_GPIO_H
+
+#include <stdint.h>
+#include "gen/gpio.h"
+
+inline void gpio_init(volatile gpio_t* reg) {
+    set_gpio_write(reg, 0);
+    set_gpio_writeEnable(reg, 0);
+}
+
+#endif /* _DEVICES_GPIO_H */
--- a/include/minres/devices/i2s.h
+++ b/include/minres/devices/i2s.h
@ -0,0 +1,9 @@
+#ifndef _DEVICES_IIS_H
+#define _DEVICES_IIS_H
+
+#include "gen/i2s.h"
+
+#define MODE_I2S 1
+#define MODE_PDM 2
+
+#endif /* _DEVICES_IIS_H */
--- a/include/minres/devices/interrupt.h
+++ b/include/minres/devices/interrupt.h
@ -0,0 +1,11 @@
+#ifndef _DEVICES_INTERRUPT_H
+#define _DEVICES_INTERRUPT_H
+
+#include <stdint.h>
+
+#define irq_t void*
+
+inline void irq_init(volatile irq_t* reg){
+}
+
+#endif /* _DEVICES_INTERRUPT_H */
--- a/include/minres/devices/msg_if.h
+++ b/include/minres/devices/msg_if.h
@ -0,0 +1,6 @@
+#ifndef _DEVICES_MSG_IF_H
+#define _DEVICES_MSG_IF_H
+
+#include "gen/msgif.h"
+
+#endif /* _DEVICES_MSG_IF_H */
--- a/include/minres/devices/qspi.h
+++ b/include/minres/devices/qspi.h
@ -0,0 +1,82 @@
+#ifndef _DEVICES_QSPI_H
+#define _DEVICES_QSPI_H
+
+#include <stdint.h>
+#include "gen/apb3spi.h"
+
+#define qspi_t apb3spi_t
+typedef struct {
+    uint32_t cpol;
+    uint32_t cpha;
+    uint32_t mode;
+    uint32_t clkDivider;
+    uint32_t ssSetup;
+    uint32_t ssHold;
+    uint32_t ssDisable;
+} spi_cfg;
+
+#define SPI_CMD_WRITE (1 << 8)
+#define SPI_CMD_READ (1 << 9)
+#define SPI_CMD_SS (1 << 11)
+
+#define SPI_RSP_VALID (1 << 31)
+
+#define SPI_STATUS_CMD_INT_ENABLE = (1 << 0)
+#define SPI_STATUS_RSP_INT_ENABLE = (1 << 1)
+#define SPI_STATUS_CMD_INT_FLAG = (1 << 8)
+#define SPI_STATUS_RSP_INT_FLAG = (1 << 9)
+
+static inline void spi_configure(volatile qspi_t* qspi, spi_cfg *config){
+    set_apb3spi_config(qspi, (config->cpol << 0) | (config->cpha << 1) | (config->mode << 4));
+    set_apb3spi_sclk_config(qspi, config->clkDivider);
+    set_apb3spi_ssgen_setup(qspi, config->ssSetup);
+    set_apb3spi_ssgen_hold(qspi, config->ssHold);
+    set_apb3spi_ssgen_disable(qspi, config->ssDisable);
+}
+
+static inline void spi_init(volatile qspi_t* spi){
+    spi_cfg spiCfg;
+    spiCfg.cpol = 0;
+    spiCfg.cpha = 0;
+    spiCfg.mode = 0;
+    spiCfg.clkDivider = 2;
+    spiCfg.ssSetup = 2;
+    spiCfg.ssHold = 2;
+    spiCfg.ssDisable = 2;
+    spi_configure(spi, &spiCfg);
+}
+
+static inline uint32_t spi_cmd_avail(volatile qspi_t* qspi){
+    return qspi->STATUS & 0xFFFF;
+}
+static inline uint32_t spi_rsp_occupied(volatile qspi_t* qspi){
+    return qspi->STATUS >> 16;
+}
+
+static inline void spi_write(volatile qspi_t* qspi, uint8_t data){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = data | SPI_CMD_WRITE;
+}
+
+static inline uint8_t spi_read(volatile qspi_t* qspi){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = SPI_CMD_READ;
+    while(spi_rsp_occupied(qspi) == 0);
+    while((qspi->DATA & 0x80000000)==0);
+    return qspi->DATA;
+}
+
+static inline void spi_select(volatile qspi_t* qspi, uint32_t slaveId){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = slaveId | 0x80 | SPI_CMD_SS;
+}
+
+static inline void spi_deselect(volatile qspi_t* qspi, uint32_t slaveId){
+    while(spi_cmd_avail(qspi) == 0);
+    qspi->DATA = slaveId | SPI_CMD_SS;
+}
+
+static inline void spi_wait_tx_idle(volatile qspi_t* qspi){
+    while(spi_cmd_avail(qspi) < 0x20);
+}
+#endif /* _DEVICES_QSPI_H */
--- a/include/minres/devices/timer.h
+++ b/include/minres/devices/timer.h
@ -0,0 +1,19 @@
+#ifndef _DEVICES_TIMER_H
+#define _DEVICES_TIMER_H
+
+#include <stdint.h>
+#include "gen/timercounter.h"
+
+inline void prescaler_init(timercounter_t* reg, uint16_t value){
+    set_timercounter_prescaler(reg, value);
+}
+
+inline void timer_t0__init(timercounter_t *reg){
+    set_timercounter_t0_overflow(reg, 0xffffffff);
+}
+
+inline void timer_t1__init(timercounter_t *reg){
+    set_timercounter_t1_overflow(reg, 0xffffffff);
+}
+
+#endif /* _DEVICES_TIMER_H */
--- a/include/minres/devices/uart.h
+++ b/include/minres/devices/uart.h
@ -0,0 +1,30 @@
+#ifndef _DEVICES_UART_H
+#define _DEVICES_UART_H
+
+#include <stdint.h>
+#include "gen/uart.h"
+
+static inline uint32_t uart_get_tx_free(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_free(reg);
+}
+
+static inline uint32_t uart_get_tx_empty(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_tx_empty(reg);
+}
+
+static inline uint32_t uart_get_rx_avail(volatile uart_t* reg){
+    return get_uart_rx_tx_reg_rx_avail(reg);
+}
+
+static inline void uart_write(volatile uart_t* reg, uint8_t data){
+    while(get_uart_rx_tx_reg_tx_free(reg) == 0);
+    set_uart_rx_tx_reg_data(reg, data);
+}
+
+static inline inline uint8_t uart_read(volatile uart_t* reg){
+    uint32_t res = get_uart_rx_tx_reg_data(reg);
+    while((res&0x10000) == 0) res = get_uart_rx_tx_reg_data(reg);
+    return res;
+}
+
+#endif /* _DEVICES_UART_H */