adds support for new mnrs peripherals

include/ehrenberg/devices/qspi.h

@@ -2,31 +2,9 @@
 #define _BSP_QSPI_H
 
 #include <stdint.h>
+#include "gen/Apb3SpiXdrMasterCtrl.h"
 
-#define __IO volatile
-
-typedef struct {
-    __IO uint32_t data;             // 0x0/0: data, 8bits, 8:write, 9:read, 11:data/ctrl, 31:rxdata valid
-    __IO uint32_t status;           // 0x4/0: txavail, 16: rxused
-    __IO uint32_t config;           // 0x8/0:1 cpol/cpha, 4: transfer mode (0-FullDuplex)
-    __IO uint32_t intr;             // 0xc/0: txien, 1: rxien, 8: txip, 9: rxip, 16: valid?
-    __IO uint32_t __fill0[4];
-    __IO uint32_t clk_divider;      // 0x20/0: sclkToogle
-    // ssGen config
-    __IO uint32_t ss_setup;         // 0x24/0: setup
-    __IO uint32_t ss_hold;          // 0x28/0: hold
-    __IO uint32_t ss_disable;       // 0x2c/0: disable
-    __IO uint32_t ss_activeHigh;    // 0x30/0: disable
-    __IO uint32_t __fill1[3];
-    __IO uint32_t xip_enable;       // 0x40/0: enable
-    __IO uint32_t xip_instr;        // 0x44/0:7 data, 8: enable, 16:23 dummy data, 24:27 dummy count
-    __IO uint32_t xip_mode;         // 0x48/0: instr transfer mode, 8: addr transfer mode, 16: dummy transfer mode, 24: data transfer mode
-    __IO uint32_t __fill2[2];
-    __IO uint32_t xip_write32;      // 0x50
-    __IO uint32_t xip_readwrite32;  // 0x54
-    __IO uint32_t xip_read32;       // 0x58
-}  __attribute((__packed__)) qspi_t;
-
+#define qspi_t apb3spixdrmasterctrl_t
 typedef struct {
     uint32_t cpol;
     uint32_t cpha;