adds support for new mnrs peripherals
This commit is contained in:
53
include/ehrenberg/devices/gen/Apb3AClint.h
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53
include/ehrenberg/devices/gen/Apb3AClint.h
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@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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*/
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#ifndef _BSP_APB3ACLINT_H
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#define _BSP_APB3ACLINT_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t MSIP0;
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volatile uint32_t MTIMECMP0LO;
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volatile uint32_t MTIMECMP0HI;
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volatile uint32_t MTIME_LO;
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volatile uint32_t MTIME_HI;
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}apb3aclint_t;
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inline uint32_t get_aclint_msip0(volatile apb3aclint_t *reg){
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return (reg->MSIP0 >> 0) & 0x1;
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}
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inline void set_aclint_msip0(volatile apb3aclint_t *reg, uint8_t value){
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reg->MSIP0 = (reg->MSIP0 & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtimecmp0lo(volatile apb3aclint_t *reg){
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return (reg->MTIMECMP0LO >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtimecmp0lo(volatile apb3aclint_t *reg, uint32_t value){
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reg->MTIMECMP0LO = (reg->MTIMECMP0LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtimecmp0hi(volatile apb3aclint_t *reg){
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return (reg->MTIMECMP0HI >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtimecmp0hi(volatile apb3aclint_t *reg, uint32_t value){
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reg->MTIMECMP0HI = (reg->MTIMECMP0HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtime_lo(volatile apb3aclint_t *reg){
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return (reg->MTIME_LO >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtime_lo(volatile apb3aclint_t *reg, uint32_t value){
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reg->MTIME_LO = (reg->MTIME_LO & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_aclint_mtime_hi(volatile apb3aclint_t *reg){
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return (reg->MTIME_HI >> 0) & 0xffffffff;
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}
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inline void set_aclint_mtime_hi(volatile apb3aclint_t *reg, uint32_t value){
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reg->MTIME_HI = (reg->MTIME_HI & ~(0xffffffffU << 0)) | (value << 0);
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}
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#endif /* _BSP_APB3ACLINT_H */
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36
include/ehrenberg/devices/gen/Apb3Gpio.h
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36
include/ehrenberg/devices/gen/Apb3Gpio.h
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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*/
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#ifndef _BSP_APB3GPIO_H
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#define _BSP_APB3GPIO_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t VALUE;
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volatile uint32_t WRITE;
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volatile uint32_t WRITEENABLE;
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}apb3gpio_t;
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inline uint32_t get_gpio_value(volatile apb3gpio_t *reg){
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return (reg->VALUE >> 0) & 0xffffffff;
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}
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inline uint32_t get_gpio_write(volatile apb3gpio_t *reg){
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return (reg->WRITE >> 0) & 0xffffffff;
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}
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inline void set_gpio_write(volatile apb3gpio_t *reg, uint32_t value){
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reg->WRITE = (reg->WRITE & ~(0xffffffffU << 0)) | (value << 0);
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}
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inline uint32_t get_gpio_writeEnable(volatile apb3gpio_t *reg){
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return (reg->WRITEENABLE >> 0) & 0xffffffff;
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}
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inline void set_gpio_writeEnable(volatile apb3gpio_t *reg, uint32_t value){
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reg->WRITEENABLE = (reg->WRITEENABLE & ~(0xffffffffU << 0)) | (value << 0);
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}
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#endif /* _BSP_APB3GPIO_H */
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32
include/ehrenberg/devices/gen/Apb3IrqCtrl.h
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32
include/ehrenberg/devices/gen/Apb3IrqCtrl.h
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@ -0,0 +1,32 @@
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/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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*/
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#ifndef _BSP_APB3IRQCTRL_H
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#define _BSP_APB3IRQCTRL_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t PENDINGSREG;
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volatile uint32_t MASKSREG;
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}apb3irqctrl_t;
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inline uint32_t get_irq_pendingsReg(volatile apb3irqctrl_t *reg){
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return (reg->PENDINGSREG >> 0) & 0xf;
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}
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inline void set_irq_pendingsReg(volatile apb3irqctrl_t *reg, uint8_t value){
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reg->PENDINGSREG = (reg->PENDINGSREG & ~(0xfU << 0)) | (value << 0);
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}
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inline uint32_t get_irq_masksReg(volatile apb3irqctrl_t *reg){
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return (reg->MASKSREG >> 0) & 0xf;
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}
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inline void set_irq_masksReg(volatile apb3irqctrl_t *reg, uint8_t value){
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reg->MASKSREG = (reg->MASKSREG & ~(0xfU << 0)) | (value << 0);
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}
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#endif /* _BSP_APB3IRQCTRL_H */
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189
include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
Normal file
189
include/ehrenberg/devices/gen/Apb3SpiXdrMasterCtrl.h
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@ -0,0 +1,189 @@
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/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
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*/
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#ifndef _BSP_APB3SPIXDRMASTERCTRL_H
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#define _BSP_APB3SPIXDRMASTERCTRL_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t DATA;
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volatile uint32_t STATUS;
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volatile uint32_t CONFIG;
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volatile uint32_t INTR;
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volatile uint32_t SCLK_CONFIG;
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volatile uint32_t SSGEN_SETUP;
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volatile uint32_t SSGEN_HOLD;
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volatile uint32_t SSGEN_DISABLE;
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volatile uint32_t SSGEN_ACTIVE_HIGH;
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volatile uint32_t XIP_ENABLE;
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volatile uint32_t XIP_CONFIG;
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volatile uint32_t XIP_MODE;
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volatile uint32_t XIP_WRITE;
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volatile uint32_t XIP_READ_WRITE;
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volatile uint32_t XIP_READ;
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}apb3spixdrmasterctrl_t;
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inline void set_spi_data_data(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0xffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_data_write(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->DATA >> 8) & 0x1;
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}
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inline void set_spi_data_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0x1U << 8)) | (value << 8);
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}
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inline uint32_t get_spi_data_read(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->DATA >> 9) & 0x1;
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}
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inline void set_spi_data_read(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0x1U << 9)) | (value << 9);
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}
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inline uint32_t get_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->DATA >> 11) & 0x1;
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}
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inline void set_spi_data_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->DATA = (reg->DATA & ~(0x1U << 11)) | (value << 11);
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}
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inline uint32_t get_spi_data_rx_data_invalid(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->DATA >> 31) & 0x1;
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}
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inline uint32_t get_spi_status_tx_free(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->STATUS >> 0) & 0x3f;
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}
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inline uint32_t get_spi_status_rx_avail(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->STATUS >> 16) & 0x3f;
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}
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inline uint32_t get_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->CONFIG >> 0) & 0x3;
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}
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inline void set_spi_config_kind(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->CONFIG = (reg->CONFIG & ~(0x3U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->CONFIG >> 4) & 0x7;
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}
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inline void set_spi_config_mode(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->CONFIG = (reg->CONFIG & ~(0x7U << 4)) | (value << 4);
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}
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inline uint32_t get_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->INTR >> 0) & 0x1;
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}
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inline void set_spi_intr_tx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->INTR = (reg->INTR & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->INTR >> 1) & 0x1;
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}
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inline void set_spi_intr_rx_ie(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->INTR = (reg->INTR & ~(0x1U << 1)) | (value << 1);
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}
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inline uint32_t get_spi_intr_tx_ip(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->INTR >> 8) & 0x1;
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}
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inline uint32_t get_spi_intr_rx_ip(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->INTR >> 9) & 0x1;
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}
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inline uint32_t get_spi_intr_tx_active(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->INTR >> 16) & 0x1;
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}
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inline uint32_t get_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->SCLK_CONFIG >> 0) & 0xfff;
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}
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inline void set_spi_sclk_config(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
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reg->SCLK_CONFIG = (reg->SCLK_CONFIG & ~(0xfffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->SSGEN_SETUP >> 0) & 0xfff;
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}
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inline void set_spi_ssgen_setup(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
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reg->SSGEN_SETUP = (reg->SSGEN_SETUP & ~(0xfffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->SSGEN_HOLD >> 0) & 0xfff;
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}
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inline void set_spi_ssgen_hold(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
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reg->SSGEN_HOLD = (reg->SSGEN_HOLD & ~(0xfffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->SSGEN_DISABLE >> 0) & 0xfff;
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}
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inline void set_spi_ssgen_disable(volatile apb3spixdrmasterctrl_t *reg, uint16_t value){
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reg->SSGEN_DISABLE = (reg->SSGEN_DISABLE & ~(0xfffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->SSGEN_ACTIVE_HIGH >> 0) & 0x1;
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}
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inline void set_spi_ssgen_active_high(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->SSGEN_ACTIVE_HIGH = (reg->SSGEN_ACTIVE_HIGH & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_ENABLE >> 0) & 0x1;
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}
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inline void set_spi_xip_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_ENABLE = (reg->XIP_ENABLE & ~(0x1U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_CONFIG >> 0) & 0xff;
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}
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inline void set_spi_xip_config_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_CONFIG >> 8) & 0x1;
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}
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inline void set_spi_xip_config_enable(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0x1U << 8)) | (value << 8);
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}
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inline uint32_t get_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_CONFIG >> 16) & 0xff;
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}
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inline void set_spi_xip_config_dummy_value(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xffU << 16)) | (value << 16);
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}
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inline uint32_t get_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_CONFIG >> 24) & 0xf;
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}
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inline void set_spi_xip_config_dummy_count(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_CONFIG = (reg->XIP_CONFIG & ~(0xfU << 24)) | (value << 24);
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}
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inline uint32_t get_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_MODE >> 0) & 0x7;
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}
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inline void set_spi_xip_mode_instruction(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 0)) | (value << 0);
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}
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inline uint32_t get_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_MODE >> 8) & 0x7;
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}
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inline void set_spi_xip_mode_address(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 8)) | (value << 8);
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}
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inline uint32_t get_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_MODE >> 16) & 0x7;
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}
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inline void set_spi_xip_mode_dummy(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 16)) | (value << 16);
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}
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inline uint32_t get_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_MODE >> 24) & 0x7;
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}
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inline void set_spi_xip_mode_payload(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_MODE = (reg->XIP_MODE & ~(0x7U << 24)) | (value << 24);
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}
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inline void set_spi_xip_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_WRITE = (reg->XIP_WRITE & ~(0xffU << 0)) | (value << 0);
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}
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inline void set_spi_xip_read_write(volatile apb3spixdrmasterctrl_t *reg, uint8_t value){
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reg->XIP_READ_WRITE = (reg->XIP_READ_WRITE & ~(0xffU << 0)) | (value << 0);
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}
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inline uint32_t get_spi_xip_read(volatile apb3spixdrmasterctrl_t *reg){
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return (reg->XIP_READ >> 0) & 0xff;
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}
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#endif /* _BSP_APB3SPIXDRMASTERCTRL_H */
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73
include/ehrenberg/devices/gen/Apb3Timer.h
Normal file
73
include/ehrenberg/devices/gen/Apb3Timer.h
Normal file
@ -0,0 +1,73 @@
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/*
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* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated at 2024-02-19 14:24:37 UTC
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* by peakrdl_mnrs version 1.2.2
|
||||
*/
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#ifndef _BSP_APB3TIMER_H
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#define _BSP_APB3TIMER_H
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#include <stdint.h>
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typedef struct __attribute((__packed__)) {
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volatile uint32_t PRESCALER;
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volatile uint32_t T0_CTRL;
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volatile uint32_t T0_OVERFLOW;
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volatile uint32_t T0_VALUE;
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volatile uint32_t T1_CTRL;
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volatile uint32_t T1_OVERFLOW;
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volatile uint32_t T1_VALUE;
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}apb3timer_t;
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inline uint32_t get_timer_prescaler(volatile apb3timer_t *reg){
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return (reg->PRESCALER >> 0) & 0xffff;
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}
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inline void set_timer_prescaler(volatile apb3timer_t *reg, uint16_t value){
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reg->PRESCALER = (reg->PRESCALER & ~(0xffffU << 0)) | (value << 0);
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}
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inline uint32_t get_timer_t0_ctrl_enable(volatile apb3timer_t *reg){
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return (reg->T0_CTRL >> 0) & 0x7;
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}
|
||||
inline void set_timer_t0_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t0_ctrl_clear(volatile apb3timer_t *reg){
|
||||
return (reg->T0_CTRL >> 3) & 0x3;
|
||||
}
|
||||
inline void set_timer_t0_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
|
||||
reg->T0_CTRL = (reg->T0_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
inline uint32_t get_timer_t0_overflow(volatile apb3timer_t *reg){
|
||||
return (reg->T0_OVERFLOW >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_timer_t0_overflow(volatile apb3timer_t *reg, uint32_t value){
|
||||
reg->T0_OVERFLOW = (reg->T0_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t0_value(volatile apb3timer_t *reg){
|
||||
return (reg->T0_VALUE >> 0) & 0xffffffff;
|
||||
}
|
||||
inline uint32_t get_timer_t1_ctrl_enable(volatile apb3timer_t *reg){
|
||||
return (reg->T1_CTRL >> 0) & 0x7;
|
||||
}
|
||||
inline void set_timer_t1_ctrl_enable(volatile apb3timer_t *reg, uint8_t value){
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t1_ctrl_clear(volatile apb3timer_t *reg){
|
||||
return (reg->T1_CTRL >> 3) & 0x3;
|
||||
}
|
||||
inline void set_timer_t1_ctrl_clear(volatile apb3timer_t *reg, uint8_t value){
|
||||
reg->T1_CTRL = (reg->T1_CTRL & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
inline uint32_t get_timer_t1_overflow(volatile apb3timer_t *reg){
|
||||
return (reg->T1_OVERFLOW >> 0) & 0xffffffff;
|
||||
}
|
||||
inline void set_timer_t1_overflow(volatile apb3timer_t *reg, uint32_t value){
|
||||
reg->T1_OVERFLOW = (reg->T1_OVERFLOW & ~(0xffffffffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_timer_t1_value(volatile apb3timer_t *reg){
|
||||
return (reg->T1_VALUE >> 0) & 0xffffffff;
|
||||
}
|
||||
#endif /* _BSP_APB3TIMER_H */
|
||||
104
include/ehrenberg/devices/gen/Apb3Uart.h
Normal file
104
include/ehrenberg/devices/gen/Apb3Uart.h
Normal file
@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright (c) 2023 - 2024 MINRES Technologies GmbH
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Generated at 2024-02-19 14:24:37 UTC
|
||||
* by peakrdl_mnrs version 1.2.2
|
||||
*/
|
||||
|
||||
#ifndef _BSP_APB3UART_H
|
||||
#define _BSP_APB3UART_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct __attribute((__packed__)) {
|
||||
volatile uint32_t RX_TX_REG;
|
||||
volatile uint32_t INT_CTRL_REG;
|
||||
volatile uint32_t CLK_DIVIDER_REG;
|
||||
volatile uint32_t FRAME_CONFIG_REG;
|
||||
volatile uint32_t STATUS_REG;
|
||||
}apb3uart_t;
|
||||
|
||||
inline uint32_t get_uart_rx_tx_reg_data(volatile apb3uart_t *reg){
|
||||
return (reg->RX_TX_REG >> 0) & 0xff;
|
||||
}
|
||||
inline void set_uart_rx_tx_reg_data(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->RX_TX_REG = (reg->RX_TX_REG & ~(0xffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_rx_tx_reg_rx_avail(volatile apb3uart_t *reg){
|
||||
return (reg->RX_TX_REG >> 14) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_rx_tx_reg_tx_free(volatile apb3uart_t *reg){
|
||||
return (reg->RX_TX_REG >> 15) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg){
|
||||
return (reg->INT_CTRL_REG >> 0) & 0x1;
|
||||
}
|
||||
inline void set_uart_int_ctrl_reg_write_intr_enable(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg){
|
||||
return (reg->INT_CTRL_REG >> 1) & 0x1;
|
||||
}
|
||||
inline void set_uart_int_ctrl_reg_read_intr_enable(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->INT_CTRL_REG = (reg->INT_CTRL_REG & ~(0x1U << 1)) | (value << 1);
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_write_intr_pend(volatile apb3uart_t *reg){
|
||||
return (reg->INT_CTRL_REG >> 8) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_int_ctrl_reg_read_intr_pend(volatile apb3uart_t *reg){
|
||||
return (reg->INT_CTRL_REG >> 9) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_clk_divider_reg(volatile apb3uart_t *reg){
|
||||
return (reg->CLK_DIVIDER_REG >> 0) & 0xfffff;
|
||||
}
|
||||
inline void set_uart_clk_divider_reg(volatile apb3uart_t *reg, uint32_t value){
|
||||
reg->CLK_DIVIDER_REG = (reg->CLK_DIVIDER_REG & ~(0xfffffU << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg){
|
||||
return (reg->FRAME_CONFIG_REG >> 0) & 0x7;
|
||||
}
|
||||
inline void set_uart_frame_config_reg_data_lenght(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x7U << 0)) | (value << 0);
|
||||
}
|
||||
inline uint32_t get_uart_frame_config_reg_parity(volatile apb3uart_t *reg){
|
||||
return (reg->FRAME_CONFIG_REG >> 3) & 0x3;
|
||||
}
|
||||
inline void set_uart_frame_config_reg_parity(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x3U << 3)) | (value << 3);
|
||||
}
|
||||
inline uint32_t get_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg){
|
||||
return (reg->FRAME_CONFIG_REG >> 5) & 0x1;
|
||||
}
|
||||
inline void set_uart_frame_config_reg_stop_bit(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->FRAME_CONFIG_REG = (reg->FRAME_CONFIG_REG & ~(0x1U << 5)) | (value << 5);
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_read_error(volatile apb3uart_t *reg){
|
||||
return (reg->STATUS_REG >> 0) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_stall(volatile apb3uart_t *reg){
|
||||
return (reg->STATUS_REG >> 1) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_break(volatile apb3uart_t *reg){
|
||||
return (reg->STATUS_REG >> 8) & 0x1;
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_break_detected(volatile apb3uart_t *reg){
|
||||
return (reg->STATUS_REG >> 9) & 0x1;
|
||||
}
|
||||
inline void set_uart_status_reg_break_detected(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 9)) | (value << 9);
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_set_break(volatile apb3uart_t *reg){
|
||||
return (reg->STATUS_REG >> 10) & 0x1;
|
||||
}
|
||||
inline void set_uart_status_reg_set_break(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 10)) | (value << 10);
|
||||
}
|
||||
inline uint32_t get_uart_status_reg_clear_break(volatile apb3uart_t *reg){
|
||||
return (reg->STATUS_REG >> 11) & 0x1;
|
||||
}
|
||||
inline void set_uart_status_reg_clear_break(volatile apb3uart_t *reg, uint8_t value){
|
||||
reg->STATUS_REG = (reg->STATUS_REG & ~(0x1U << 11)) | (value << 11);
|
||||
}
|
||||
#endif /* _BSP_APB3UART_H */
|
||||
Reference in New Issue
Block a user